Synopsys DesignWare ARC AXC003, User Manual, Page: 71 / 145

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Memory Map of the Local Peripherals DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018 Synopsys, Inc.
May 2017
Likewise, the slave address of the AXI TUNNEL1 slave on the ARC SDP Mainboard is
forwarded to the AXI Tunnel master on the HAPS system. It is then decoded according to
your custom design.
7.4 Memory Map of the Local Peripherals
All peripherals of the APB subsystem inside the AXC003 Processor FPGA are mapped into
the AXI2APB segment of the system memory map, which has the default base address
0xF000_0000
. Table 32 shows the address offsets of the individual peripherals and the
corresponding aperture within the AXI2APB section. This means that the address offset listed
in Table 32 has to be added to the base address of the AXI2APB section to obtain the correct
base address (to be used by the master) of the peripheral.
Example: If the AXI2APB segment is located at its default address
0xF000_0000
, the CREG
base address within the memory map of the master is
0xF000_1000
.
Table 32 Peripheral Memory Map
Peripheral Address Offset Aperture
[Bytes] Description
CGU
0x0000_0000
4096 Clock Generation Unit
CREG
0x0000_1000
4096 Control Registers
ICTL
0x0000_2000
128 Interrupt Controller
GPIO
0x0000_3000
128 General Purpose I/O
UART
0x0000_5000
128 UART