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ST STM32WL5 Series Reference Manual Download Page 785

RM0453 Rev 2

785/1454

RM0453

Advanced-control timer (TIM1)

822

         

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20

MMS2[3:0]

: Master mode selection 2

These bits allow the information to be sent to ADC for synchronization (TRGO2) to be 
selected. The combination is as follows:
0000:

Reset

 - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If 

the reset is generated by the trigger input (slave mode controller configured in reset 
mode), the signal on TRGO2 is delayed compared to the actual reset.

0001:

Enable

 - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is 

useful to start several timers at the same time or to control a window in which a slave 
timer is enabled. The Counter Enable signal is generated by a logic AND between the 
CEN control bit and the trigger input when configured in Gated mode. When the 
Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, 
except if the Master/Slave mode is selected (see the MSM bit description in 
TIMx_SMCR register).

0010:

Update

 - the update event is selected as trigger output (TRGO2). For instance, a 

master timer can then be used as a prescaler for a slave timer.

0011:

Compare pulse

 - the trigger output sends a positive pulse when the CC1IF flag is to 

be set (even if it was already high), as soon as a capture or compare match occurs 
(TRGO2).

0100:

Compare

 - OC1REFC signal is used as trigger output (TRGO2)

0101:

Compare

 - OC2REFC signal is used as trigger output (TRGO2)

0110:

Compare

 - OC3REFC signal is used as trigger output (TRGO2)

0111:

Compare

 - OC4REFC signal is used as trigger output (TRGO2)

1000:

Compare

 - OC5REFC signal is used as trigger output (TRGO2)

1001:

Compare

 - OC6REFC signal is used as trigger output (TRGO2)

1010:

Compare Pulse

 - OC4REFC rising or falling edges generate pulses on TRGO2

1011:

Compare Pulse

 - OC6REFC rising or falling edges generate pulses on TRGO2

1100:

Compare Pulse

 - OC4REFC or OC6REFC rising edges generate pulses on TRGO2

1101:

Compare Pulse

 - OC4REFC rising or OC6REFC falling edges generate pulses on 

TRGO2

1110:

Compare Pulse

 - OC5REFC or OC6REFC rising edges generate pulses on TRGO2

1111:

Compare Pulse

 - OC5REFC rising or OC6REFC falling edges generate pulses on 

TRGO2

Note: The clock of the slave timer or ADC must be enabled prior to receive events from the 

master timer, and must not be changed on-the-fly while triggers are received from the 
master timer.

Bit 19 Reserved, must be kept at reset value.

Bit 18

OIS6

: Output Idle state 6 (OC6 output)

Refer to OIS1 bit

Bit 17 Reserved, must be kept at reset value.

Bit 16

OIS5

: Output Idle state 5 (OC5 output)

Refer to OIS1 bit

Bit 15 Reserved, must be kept at reset value.

Bit 14

OIS4

: Output Idle state 4 (OC4 output)

Refer to OIS1 bit

Bit 13

OIS3N

: Output Idle state 3 (OC3N output)

Refer to OIS1N bit

Summary of Contents for STM32WL5 Series

Page 1: ...icrocontrollers with different memory sizes packages and peripherals For ordering information mechanical and electrical device characteristics refer to the corresponding datasheets For information on...

Page 2: ...ot configuration 62 2 3 CPU2 boot 64 2 4 SRAM erase 65 2 5 Memory protection 65 2 6 Memory organization 70 2 6 1 Introduction 70 2 6 2 Memory map and register boundary addresses 71 2 6 3 CPU1 bit band...

Page 3: ...1 3 6 GTZC TZIC registers 92 3 6 1 GTZC TZIC interrupt enable register 1 GTZC_TZIC_IER1 92 3 6 2 GTZC TZIC status register 1 GTZC_TZIC_MISR1 93 3 6 3 GTZC TZIC interrupt status clear register 1 GTZC_T...

Page 4: ...2 FLASH_ACR2 129 4 10 3 FLASH key register FLASH_KEYR 130 4 10 4 FLASH option key register FLASH_OPTKEYR 130 4 10 5 FLASH status register FLASH_SR 131 4 10 6 FLASH control register FLASH_CR 133 4 10...

Page 5: ...3 3 Transmitter 156 5 3 4 Receiver 157 5 3 5 RF PLL 158 5 3 6 Intermediate frequencies 158 5 4 Sub GHz radio clocks 159 5 4 1 Internal oscillators 159 5 4 2 HSE32 reference clock 159 5 5 Sub GHz radi...

Page 6: ...6 5 10 Sub GHz radio registers 206 5 10 1 Sub GHz radio generic bit synchronization register SUBGHZ_GBSYNCR 206 5 10 2 Sub GHz radio generic packet control 1A register SUBGHZ_GPKTCTL1AR 207 5 10 3 Sub...

Page 7: ...ster 0 SUBGHZ_RNGR0 212 5 10 22 Sub GHz radio receiver gain control register SUBGHZ_RXGAINCR 213 5 10 23 Sub GHz radio PA over current protection register SUBGHZ_PAOCPR 213 5 10 24 Sub GHz radio HSE32...

Page 8: ...6 Power status register 2 PWR_SR2 260 6 6 7 PWR status clear register PWR_SCR 262 6 6 8 PWR control register 5 PWR_CR5 263 6 6 9 PWR port A pull up control register PWR_PUCRA 264 6 6 10 PWR port A pul...

Page 9: ...clock SYSCLK selection 287 7 2 9 Clock source frequency versus voltage scaling 288 7 2 10 Clock security system on HSE32 CSS 288 7 2 11 Clock security system on LSE LSECSS 289 7 2 12 SPI2S2 clock 289...

Page 10: ...1 RCC_APB1ENR1 320 7 4 19 RCC APB1 peripheral clock enable register 2 RCC_APB1ENR2 321 7 4 20 RCC APB2 peripheral clock enable register RCC_APB2ENR 322 7 4 21 RCC APB3 peripheral clock enable registe...

Page 11: ...42 RCC CPU2 AHB3 peripheral clock enable in Sleep mode register RCC_C2AHB3SMENR 350 7 4 43 RCC CPU2 APB1 peripheral clock enable in Sleep mode register 1 RCC_C2APB1SMENR1 351 7 4 44 RCC CPU2 APB1 per...

Page 12: ...9 3 1 IPCC block diagram 379 9 3 2 IPCC Simplex channel mode 379 9 3 3 IPCC Half duplex channel mode 382 9 3 4 IPCC interrupts 385 9 4 IPCC registers 385 9 4 1 IPCC processor 1 control register IPCC_C...

Page 13: ...ister GPIOx_PUPDR x A to B 403 10 4 5 GPIOx input data register GPIOx_IDR x A to B 404 10 4 6 GPIOx output data register GPIOx_ODR x A to B 405 10 4 7 GPIOx bit set reset register GPIOx_BSRR x A to B...

Page 14: ...2 1 SYSCFG memory remap register SYSCFG_MEMRMP 427 11 2 2 SYSCFG configuration register 1 SYSCFG_CFGR1 428 11 2 3 SYSCFG external interrupt configuration register 1 SYSCFG_EXTICR1 429 11 2 4 SYSCFG ex...

Page 15: ...COMP2 449 12 3 9 From internal analog to ADC 450 12 3 10 From comparators COMP1 COMP2 to timers TIM1 TIM2 TIM16 TIM17 450 12 3 11 From system errors to timers TIM1 TIM16 TIM17 451 12 3 12 From timers...

Page 16: ...DMAMUX functional description 483 14 4 1 DMAMUX block diagram 483 14 4 2 DMAMUX signals 484 14 4 3 DMAMUX channels 484 14 4 4 DMAMUX secure non secure channels 485 14 4 5 DMAMUX privileged unprivileg...

Page 17: ...gger selection register EXTI_RTSR1 512 16 6 2 EXTI falling trigger selection register EXTI_FTSR1 513 16 6 3 EXTI software interrupt event register EXTI_SWIER1 514 16 6 4 EXTI pending register EXTI_PR1...

Page 18: ...3 5 ADC clock CKMODE PRESC 3 0 538 18 3 6 ADC connectivity 540 18 3 7 Configuring the ADC 541 18 3 8 Channel selection CHSEL SCANDIR CHSELRMOD 541 18 3 9 Programmable sampling time SMPx 2 0 542 18 3...

Page 19: ...8 8 2 Analog watchdog 563 18 8 3 Triggered mode 563 18 9 Temperature sensor and internal reference voltage 564 18 10 Battery voltage monitoring 566 18 11 ADC interrupts 567 18 12 ADC registers 569 18...

Page 20: ...requests 597 19 4 9 Noise generation 597 19 4 10 Triangle wave generation 599 19 4 11 DAC channel modes 600 19 4 12 DAC channel buffer calibration 603 19 4 13 DAC channel conversion modes 604 19 5 DA...

Page 21: ...EFBUF functional description 618 20 3 VREFBUF registers 619 20 3 1 VREFBUF control and status register VREFBUF_CSR 619 20 3 2 VREFBUF calibration control register VREFBUF_CCR 620 20 3 3 VREFBUF regist...

Page 22: ...processing time 642 22 6 RNG entropy source validation 642 22 6 1 Introduction 642 22 6 2 Validation conditions 642 22 6 3 Data collection 643 22 7 RNG registers 643 22 7 1 RNG control register RNG_CR...

Page 23: ...684 23 7 1 AES control register AES_CR 684 23 7 2 AES status register AES_SR 687 23 7 3 AES data input register AES_DINR 688 23 7 4 AES data output register AES_DOUTR 688 23 7 5 AES key register 0 AE...

Page 24: ...ry multiplication 704 24 4 6 Modular exponentiation 705 24 4 7 Modular inversion 706 24 4 8 Modular reduction 707 24 4 9 Arithmetic addition 707 24 4 10 Arithmetic subtraction 707 24 4 11 Arithmetic m...

Page 25: ...2 Asymmetric PWM mode 754 25 3 13 Combined PWM mode 755 25 3 14 Combined 3 phase PWM mode 756 25 3 15 Complementary outputs and dead time insertion 757 25 3 16 Using the break function 759 25 3 17 Bid...

Page 26: ...oad register TIM1_ARR 804 25 4 15 TIM1 repetition counter register TIM1_RCR 805 25 4 16 TIM1 capture compare register 1 TIM1_CCR1 805 25 4 17 TIM1 capture compare register 2 TIM1_CCR2 806 25 4 18 TIM1...

Page 27: ...g 857 26 3 17 Timer input XOR function 857 26 3 18 Timers and external trigger synchronization 858 26 3 19 Timer synchronization 861 26 3 20 DMA burst mode 865 26 3 21 Debug mode 866 26 4 TIM2 registe...

Page 28: ...timer input selection register TIM2_TISEL 890 26 4 25 TIMx register map 891 27 General purpose timers TIM16 TIM17 894 27 1 TIM16 TIM17 introduction 894 27 2 TIM16 TIM17 main features 894 27 3 TIM16 TI...

Page 29: ...unter register TIMx_RCR x 16 to 17 934 27 4 13 TIMx capture compare register 1 TIMx_CCR1 x 16 to 17 934 27 4 14 TIMx break and dead time register TIMx_BDTR x 16 to 17 935 27 4 15 TIMx DMA control regi...

Page 30: ...ear register LPTIM_ICR 962 28 7 3 LPTIM interrupt enable register LPTIM_IER 963 28 7 4 LPTIM configuration register LPTIM_CFGR 964 28 7 5 LPTIM control register LPTIM_CR 967 28 7 6 LPTIM compare regis...

Page 31: ...tures 984 31 3 WWDG functional description 984 31 3 1 WWDG block diagram 985 31 3 2 WWDG internal signals 985 31 3 3 Enabling the watchdog 985 31 3 4 Controlling the down counter 985 31 3 5 How to pro...

Page 32: ...011 32 6 3 RTC sub second register RTC_SSR 1012 32 6 4 RTC initialization control and status register RTC_ICSR 1012 32 6 5 RTC prescaler register RTC_PRER 1014 32 6 6 RTC wakeup timer register RTC_WUT...

Page 33: ...CR1 1039 33 6 2 TAMP control register 2 TAMP_CR2 1040 33 6 3 TAMP control register 3 TAMP_CR3 1041 33 6 4 TAMP filter control register TAMP_FLTCR 1042 33 6 5 TAMP interrupt enable register TAMP_IER 10...

Page 34: ...rupts 1101 34 7 I2C registers 1102 34 7 1 I2C control register 1 I2C_CR1 1102 34 7 2 I2C control register 2 I2C_CR2 1105 34 7 3 I2C own address 1 register I2C_OAR1 1107 34 7 4 I2C own address 2 regist...

Page 35: ...52 35 5 18 USART IrDA SIR ENDEC block 1156 35 5 19 Continuous communication using USART and DMA 1159 35 5 20 RS232 Hardware flow control and RS485 Driver Enable 1161 35 5 21 USART low power management...

Page 36: ...ltiprocessor communication 1220 36 4 10 LPUART parity control 1222 36 4 11 LPUART single wire Half duplex communication 1223 36 4 12 Continuous communication using DMA and LPUART 1223 36 4 13 RS232 Ha...

Page 37: ...andard multi slave communication 1263 37 5 4 Multi master communication 1264 37 5 5 Slave select NSS pin management 1265 37 5 6 Communication formats 1266 37 5 7 Configuration of SPI 1268 37 5 8 Proce...

Page 38: ...3 DBG functional description 1317 38 3 1 DBG block diagram 1317 38 3 2 DBG pins and internal signals 1318 38 3 3 DBG interface control 1318 38 3 4 DBG reset and clocks 1319 38 3 5 DBG power domains 1...

Page 39: ...WT program counter sample register DWT_PCSR 1347 38 6 9 DWT comparator register x DWT_COMPxR 1347 38 6 10 DWT mask register x DWT_MASKxR 1348 38 6 11 DWT function register x DWT_FUNCTxR 1348 38 6 12 D...

Page 40: ...tity register 2 FPB_PIDR2 1388 38 9 8 FPB CoreSight peripheral identity register 3 FPB_PIDR3 1388 38 9 9 FPB CoreSight component identity register 0 FPB_CIDR0 1389 38 9 10 FPB CoreSight peripheral ide...

Page 41: ...t peripheral identity register 1 TPIU_PIDR1 1407 38 11 15 TPIU CoreSight peripheral identity register 2 TPIU_PIDR2 1408 38 11 16 TPIU CoreSight peripheral identity register 3 TPIU_PIDR3 1408 38 11 17...

Page 42: ...oreSight component identity register 3 C2ROM1_CIDR3 1427 38 13 11 CPU2 ROM1 registers and reset values 1427 38 13 12 CPU2 ROM2 memory type register C2ROM2_MEMTYPER 1428 38 13 13 CPU2 ROM2 CoreSight pe...

Page 43: ...ral identity register 3 BPU_PIDR3 1437 38 14 9 BPU CoreSight component identity register 0 BPU_CIDR0 1438 38 14 10 BPU CoreSight peripheral identity register 1 BPU_CIDR1 1438 38 14 11 BPU CoreSight co...

Page 44: ...3 Flash interrupt requests 126 Table 25 Flash interface register map and reset values 152 Table 26 Sub GHz internal input output signals 155 Table 27 Sub GHz radio transmit high output power 157 Table...

Page 45: ...able 76 STM32WL5x peripherals interconnect matrix 445 Table 77 DMA1 and DMA2 implementation 454 Table 78 DMA internal input output signals 456 Table 79 Programmable data width and endian behavior when...

Page 46: ...128 COMP register map and reset values 632 Table 129 RNG internal input output signals 634 Table 130 RNG interrupt requests 642 Table 131 RNG configurations 642 Table 132 RNG register map and reset ma...

Page 47: ...IM1 internal trigger connection 789 Table 180 Output control bits for complementary OCx and OCxN channels with break feature 803 Table 181 TIM1 register map and reset values 820 Table 182 Counting dir...

Page 48: ...ration 1088 Table 233 Examples of TIMEOUTA settings for various I2CCLK frequencies max tTIMEOUT 25 ms 1089 Table 234 Examples of TIMEOUTB settings for various I2CCLK frequencies 1089 Table 235 Example...

Page 49: ...ter map and reset values 1353 Table 272 CPU2 CTI inputs 1356 Table 273 CPU2 CTI outputs 1357 Table 274 CPU1 CTI inputs 1357 Table 275 CPU1 CTI outputs 1357 Table 276 CTI register map and reset values...

Page 50: ...230 Figure 25 CPUs low power modes possible transitions 234 Figure 26 Simplified diagram of the reset circuit 277 Figure 27 Clock tree 281 Figure 28 HSE32 clock sources 282 Figure 29 HSE32 TCXO contr...

Page 51: ...t mode conversion continuous mode software trigger 555 Figure 74 Behavior with WAIT 0 AUTOFF 1 556 Figure 75 Behavior with WAIT 1 AUTOFF 1 556 Figure 76 Analog watchdog guarded area 557 Figure 77 ADC_...

Page 52: ...6 Figure 130 Counter timing diagram with prescaler division change from 1 to 4 726 Figure 131 Counter timing diagram internal clock divided by 1 728 Figure 132 Counter timing diagram internal clock di...

Page 53: ...177 6 step generation COM example OSSR 1 768 Figure 178 Example of one pulse mode 769 Figure 179 Retriggerable one pulse mode 771 Figure 180 Example of counter operation in encoder interface mode 772...

Page 54: ...in reset mode 858 Figure 228 Control circuit in gated mode 859 Figure 229 Control circuit in trigger mode 860 Figure 230 Control circuit in external clock mode 2 trigger mode 861 Figure 231 Master Sl...

Page 55: ...Figure 276 I2C bus protocol 1054 Figure 277 Setup and hold timings 1056 Figure 278 I2C initialization flowchart 1059 Figure 279 Data reception 1060 Figure 280 Data transmission 1061 Figure 281 Slave i...

Page 56: ...9 Figure 320 USART data clock timing diagram in synchronous slave mode M bits 00 1150 Figure 321 ISO 7816 3 asynchronous protocol 1152 Figure 322 Parity error detection using the 1 5 stop bits 1154 Fi...

Page 57: ...andard 16 bit extended to 32 bit packet frame 1288 Figure 368 Example of 16 bit data frame extended to 32 bit channel frame 1288 Figure 369 MSB Justified 16 bit or 32 bit full accuracy length 1289 Fig...

Page 58: ...lue read clear write1 rc_w1 Software can read as well as clear this bit by writing 1 Writing 0 has no effect on the bit value read clear write rc_w Software can read as well as clear this bit by writi...

Page 59: ...this document Word data of 32 bit length Half word data of 16 bit length Byte data of 8 bit length Option bytes product configuration bits stored in the Flash memory AHB advanced high performance bus...

Page 60: ...core I bus CPU1 core D bus CPU1 core S bus CPU2 core S bus DMA1 DMA2 Eight slaves Internal Flash memory on the CPU1 Code bus Internal Flash memory on CPU1 DCode bus Internal Flash memory on CPU2 S bus...

Page 61: ...This bus connects the system bus of the CPU1 core to the bus matrix This bus is used by the core to access data located in a peripheral or SRAM area The targets of this bus are the SRAM1 SRAM2 the AH...

Page 62: ...efer to Section 2 6 2 Memory map and register boundary addresses for the address mapping of the peripherals connected to this bridge After each device reset all peripheral clocks are disabled except f...

Page 63: ...oot 1 System Flash boot SBRV boot 0 0 0 0 x Hold SFI RSS boot 1 2 3 1 Hold SBRV boot 2 1 1 0 x System Flash boot SBRV boot 0 0 SRAM1 boot SBRV boot x x 1 User Flash boot SBRV boot 1 1 x 0 0 x Yes 0 Us...

Page 64: ...uction It is used to program the Flash memory using one of the following device interfaces USART1 on pins PA9 and PA10 USART2 on pins PA2 and PA3 SPI1 on pins PA4 PA5 PA6 and PA7 SPI2S2 on pins PB12 P...

Page 65: ...Flash memory user options and privilege is defined in GTZC_TZSC registers The security and privilege definition protects the memory areas from being accessed by any non authorized bus master Table 2 S...

Page 66: ...rotection area with the HDPADIS bit in Flash memory access control register 2 FLASF_ACR2 Memory protection is controlled by the parameters as listed below Flash memory security address offset is defin...

Page 67: ...non secure unprivileged areas are accessible read write by the secure and non secure privileged and unprivileged bus masters and are only accessible execute by the non secure privileged and unprivile...

Page 68: ...non secure DMA channels have no execute read nor write access to these areas The non secure area of the memories grants full read write execute access to CPU1 and all DMA channels CPU2 has only read a...

Page 69: ...bit 2 Read access returns a zero value write access is ignored and in both cases an illegal access event is generated 3 The secure privileged and unprivileged read and execute protected pages cannot b...

Page 70: ...y data memory registers and I O ports are organized within the same linear 4 Gbyte address space The bytes are coded in memory in Little Endian format The lowest numbered byte in a word is considered...

Page 71: ...FFFF AHB3 2 0x5800 0000 APB3 2 CODE 0x4000 0000 0xE000 0000 0x2000 0000 0x0000 0000 SRAM2 1 3 Reserved Flash 1 Reserved Reserved Reserved CPU1 Flash system memory or SRAM1 depending on BOOT configurat...

Page 72: ...ster map 0x5800 2400 0x5800 33FF PKA RAM 0x5800 2000 0x5800 23FF PKA 0x5800 1C00 0x5800 1FFF Reserved 0x5800 1800 0x5800 1BFF 1 K AES Section 23 7 18 AES register map 0x5800 1400 0x5800 17FF 1 K HSEM...

Page 73: ...001 4400 0x4001 47FF 1 K TIM16 Section 27 4 23 TIM16 TIM17 register map 0x4001 3C00 0x4001 43FF Reserved 0x4001 3800 0x4001 3BFF 1 K USART1 Section 35 8 15 USART register map 0x4001 3400 0x4001 37FF R...

Page 74: ...I2C register map 0x4000 4800 0x4000 53FF Reserved 0x4000 4400 0x4000 47FF 1 K USART2 Section 35 8 15 USART register map 0x4000 3C00 0x4000 43FF Reserved 0x4000 3800 0x4000 3BFF 1 K SPI2S2 Section 37...

Page 75: ...te_offset 32 bit_number 4 where bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit bit_band_base is the starting address of the alias region byte_offset...

Page 76: ...s then 0x2200 6008 0x2200 0000 0x0300 32 2 4 Writing to address 0x2200 6008 has the same effect as a read modify write operation on bit 2 of the byte at SRAM1 address 0x2000 0300 Reading address 0x220...

Page 77: ...leged part of TZSC Set of registers to define product security settings Privileged watermark for internal memories Secure and privileged access mode for securable peripherals Note Security and privile...

Page 78: ...4 GTZC functional description 3 4 1 GTZC block diagram Figure 5 describes the combined feature of TZSC and TZIC Each sub block is controlled by its own AHB configuration port TZSC defines which perip...

Page 79: ..._ sec tzsc_mpcwm n _ sec tzsc_mpcwm n _priv tzsc_ila_event tzic_ila_it from option byte Table 5 GTZC internal signals Internal signal name Signal type Description AHB Input output AHB slaves TZSC and...

Page 80: ...rates an illegal access event and a bus error Illegal non secure memory fetch access Any non secure memory fetch access transaction trying to access a secure memory resource is considered as illegal T...

Page 81: ...rant No No Grant No No Write Unprivileged Fetch P 3 Yes Illegal P Yes Illegal S and P Yes Illegal S Yes Read No No P No Grant No No Write Non secure Privileged Fetch S 4 Yes S Yes Illegal S Yes Grant...

Page 82: ...table area starting from the internal Flash memory base Table 7 Peripheral access error generation Peripheral access type 1 Secure privileged peripheral Secure unprivileged peripheral Non secure privi...

Page 83: ...n interrupt to the secure CPU2 NVIC TZIC_ILA For each illegal event source a status flag and a clear bit exist respectively within TZIC_MISR and TZIC_ICR registers The reset value of the enable regist...

Page 84: ...m is non secure ESE 0 this register cannot be written and is read zero Table 8 TZSC privileged MPCWMn register memory allocation MPCWM index Memory Description 1 Flash Unprivileged and unprivileged wr...

Page 85: ...n GTZC_TZSC_PRIVCFGR1 are configured as privileged When TZSC configuration is locked in GTZC_TZSC_CR LCK this register can no longer be modified Note When the system is non secure ESE 0 this register...

Page 86: ...ter bits in GTZC_TZSC_SECCFGR1 are configured as secure When TZSC configuration is locked in GTZC_TZSC_CR LCK this register cannot be modified 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res R...

Page 87: ...7 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res LGTH 11 0 rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res B...

Page 88: ...s Res Res Res Res Res Res Res Res Res Res Bits 31 28 Reserved must be kept at reset value Bits 27 16 LGTH 11 0 Define the length of Flash unprivileged writable area in 2 Kbyte resolution starting from...

Page 89: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res LGTH 11 0 rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 90: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res LGTH 11 0 rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res R...

Page 91: ...erved Reserved 0x020 GTZC_TZSC_ PRIVCFGR1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PKAPRIV Res Res Res Res Res Res Res Res SUBGHZSPIPRIV RNGPRIV AESPRIV Res Res Reset va...

Page 92: ...Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res PKAIE SRAM2 IE SRAM1 IE FLASH IE DMAM UX1IE DMA2 IE DMA1 IE FLASH IFIE PWRIE SUBG HZSP IIE RNGIE...

Page 93: ...0 Disabled masked 1 Enabled unmasked Bit 4 SUBGHZSPIIE Illegal access event interrupt enable bit for sub GHz SPI 0 Disabled masked 1 Enabled unmasked Bit 3 RNGIE Illegal access event interrupt enable...

Page 94: ...rupt status flag before masking for DMA1 0 No illegal access event interrupt pending 1 Illegal access event interrupt pending Bit 6 FLASHIFMF Illegal access event interrupt status flag before masking...

Page 95: ...erved must be kept at reset value Bit 13 PKACF Illegal access event interrupt status flag clear bit for PKA 0 No action 1 Clear status flag Bit 12 SRAM2CF Illegal access event interrupt status flag cl...

Page 96: ...ter map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 GTZC_TZIC_IER1 Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 97: ...ts plus 8 ECC bits Page erase 2 Kbytes and mass erase Flash memory interface features Flash memory read operations Flash memory program erase operations Readout protection activated by option RDP 2 wr...

Page 98: ...rotected against spurious write erase operations 1 Kbyte 128 double word OTP one time programmable for user data The OTP data cannot be erased and can be written only once If only one bit is at 0 the...

Page 99: ...ear this flag after programming of a virgin device to execute user code after a system reset The EMPTY bit can also directly be written by software 4 3 3 Error code correction ECC Data in Flash memory...

Page 100: ...the SHDHPRE 3 0 bits in RCC_EXTCFGR 5 Optionally check that the new system clock source or and the new Flash memory clock prescaler value is are taken into account by reading the clock source status...

Page 101: ...n prefetch The CPU1 fetches the instruction over the ICode bus and the literal pool constant data over the DCode bus The prefetch block aims at increasing the efficiency of ICode bus accesses The CPU2...

Page 102: ...7 D 7 7 F 8 8 Read ins 1 2 3 4 Gives ins 1 2 3 4 ins 1 fetch ins 2 fetch ins 3 fetch ins 4 fetch Read ins 5 6 7 8 Gives ins 5 6 7 8 ins 5 fetch ins 6 fetch ins 7 fetch ins 8 fetch WITH PREFETCH 1 F 1...

Page 103: ...pipeline is consequently stalled until the requested literal pool is provided To limit the time lost due to literal pools accesses through the AHB data bus DCode have priority over accesses through t...

Page 104: ...ogram erase operation to the Flash memory any attempt to read the Flash memory stalls the bus The read operation proceeds correctly once the program erase operation is completed Note In a multi CPU sy...

Page 105: ...area disable provide no protection for erase A hide protection area when not protected by PCROP or WRP can be erased To erase a 2 Kbyte page follow the steps detailed below 1 Check that no Flash memo...

Page 106: ...memory mass erase by the CPU1 is ignored and an illegal access event is generated When PCROP or WRP is enabled any Flash memory mass erase is aborted and no erase started Hide protection area and hide...

Page 107: ...ASH_C2SR Any attempt to write a double word that is not aligned with a double word address sets the PGAERR flag in FLASH_SR or FLASH_C2SR When the system is secure ESE 1 only the secure CPU2 is able t...

Page 108: ...LASH_SR or FLASH_C2SR meaning the programming operation succeeded and clear it by software 8 Clear PG in FLASH_SR or FLASH_C2SR if there no more programming request Fast programming This mode allows a...

Page 109: ...6 is previously enabled with HSION in the RCC_CR register The 32 double word must be written successively The high voltage is kept on the Flash memory for all the programming Maximum time between two...

Page 110: ...s event is generated instead In the page erase sequence PG FSTPG and MER are not cleared when PER is set when the security of the page allows access When the security of this page does not allow acces...

Page 111: ...request PGSERR and PGAERR in a page based row programming In case of fast programming the table below describes how PGAERR and PGSERR are handled After a system reset no MER or PER is performed Any p...

Page 112: ...WRP area A address register FLASH_WRP1AR FLASH WRP area B address register FLASH_WRP1BR FLASH IPCC mailbox data buffer address register FLASH_IPCCBR FLASH CPU2 access control register FLASH_C2ACR FLAS...

Page 113: ...multi CPU system it is good practice to use semaphores to manage option programming and prevent simultaneous option programming by the CPUs Modify user options The option bytes are programmed differe...

Page 114: ...estart the device and reload the options Secure user options When the system is secure ESE 1 the secure option bytes Flash in FLASH_C2ACR and FLASH_SRRVR can only be written by the secure CPU2 Option...

Page 115: ...of mismatch is sub GHz radio SPI secure For OPTVAL option the value of mismatch is not valid OPTVAL is a check word programmed at the last user option address It is used to check if all user options...

Page 116: ...2 bit for sub GHz radio SPI in GTZC TZSC privileged configuration register GTZC_TZSC_PRIVCFGR1 4 5 Secure system memory 4 5 1 Introduction The secure system memory stores RSS root secure services firm...

Page 117: ...due to loss of program counter context The write protection WRP granularity is 2 Kbytes Apart from the RDP and WRP the Flash memory can also be protected against read and write from third parties PCR...

Page 118: ...be placed in a page containing a PCROP area Level 2 no debug In this level the protection level 1 is guaranteed In addition the CPU1 and CPU2 debug port the boot from RAM boot RAM mode and the boot f...

Page 119: ...memory erase ESE PCROP PCROP_RDP Comment 0 None x Flash SRAM1 SRAM2 PKA SRAM and backup registers mass erase Partial 1 0 Flash multiple page erase of all non PCROP pages SRAM1 SRAM2 PKA SRAM and backu...

Page 120: ...s erase to not erase secure and or PCROP pages Backup registers and SRAM2 erase Options page erase New options program Options write RDP level identical includes Options page erase New options program...

Page 121: ...PCROP1x_END 0x74 PCROP area last address 0x0801 D3FF Any data read access performed through a PCROP protected area triggers the RDERR flag error Any PCROP protected address is also write protected an...

Page 122: ...1x_END WRP1x_STRT For example to protect by WRP from the address 0x0801 2000 included to the address 0x0801 9FFF included if boot in Flash is selected FLASH_WRP1AR register must be programmed with WRP...

Page 123: ...becomes non secure Non secure CPU1 and secure CPU2 can both remove security by setting the ESE bit to 0 in FLASH_OPTR and regressing the RDP level from level 1 to level 0 In this case the main Flash m...

Page 124: ...cluded to the address 0x2000 7FFF included FLASH_SRRVR must be programmed with SNBRSA 0x1B Any CPU1 read access returns zero data A write access to a CPU2 security SRAM1 area is discarded and generate...

Page 125: ...boot from the user Flash memory regardless of what is selected by BOOT0 and BOOT1 When BOOT_LOCK is enabled and BOOT0 BOOT1 select anything different than the user Flash memory boot the system boots...

Page 126: ...s an illegal access event This event is connected to the GTZC_TZIC Non secure access to secure registers generates an illegal access event This event is connected to the GTZC_TZIC For more information...

Page 127: ...in the Flash memory are also protected by privileged FLASH_PRIVMODER PRIV 1 the other non secure user option bits are privileged They can be written only by a privileged CPU1 or CPU2 and read by CPU1...

Page 128: ...PES CPU1 program erase suspend request 0 Flash program and erase operations granted 1 Any new Flash program and erase operation is suspended until this bit and the same bit in FLASH_C2ACR are cleared...

Page 129: ...ister value is returned There are no read restrictions Note When the system is non secure ESE 0 this register cannot be written Bit 8 PRFTEN CPU1 prefetch enable 0 CPU1 prefetch disabled 1 CPU1 prefet...

Page 130: ...isable This bit is set by software and is only reset by hardware on a system reset 0 User Flash hide protection area access enabled 1 User Flash hide protection area access disabled Bit 0 PRIVMODE FLA...

Page 131: ...new program or erase operations are not started Bit 18 CFGBSY Program or erase configuration busy This bit is set and reset by hardware set when first word is sent and reset when program operation co...

Page 132: ...new data is not present in time and cleared by writing 1 Bit 7 PGSERR Programming sequence error This bit is set by hardware when a write access to the Flash memory is performed by the code while PG...

Page 133: ...ains 1 until suspend is deactivated by clearing the PES bits in FALSH_ACR and FLASH_C2ACR Consequently PESD goes back to 0 and the suspended operation completes Bit 2 Reserved must be kept at reset va...

Page 134: ...n FLASH_SR is set to 1 0 PCROP read error interrupt disabled 1 PCROP read error interrupt enabled Bit 25 ERRIE error interrupt enable This bit enables the interrupt generation when the OPERR bit in FL...

Page 135: ...CIE Res Res Res SYSF_ECC Res Res Res ADDR_ECC 16 rc_w1 rc_w1 r r r rw r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR_ECC 15 0 r r r r r r r r r r r r r r r r Bit 31 ECCD ECC detection Set by hardware...

Page 136: ...ed access Unprivileged write access is ignored and an illegal access event is generated Unprivileged read access is still allowed Bits 23 21 Reserved must be kept at reset value Bit 20 SYSF_ECC system...

Page 137: ...ogether with option nBOOT1 selects the boot modes from the user Flash memory SRAM1 or system Flash memory Refer to Section 2 2 Boot configuration 0 nBOOT0 0 1 nBOOT0 1 Bit 26 nSWBOOT0 software BOOT0 s...

Page 138: ...eset generated when entering the Stop mode Bits 11 9 BOR_LEV 2 0 BOR reset Level These bits contain the VDD supply level threshold that activates releases the reset 000 BOR level 0 Reset level thresho...

Page 139: ...dress register FLASH_PCROP1AER Address offset 0x028 Reset value 0xFFFF FF00 Default reset value from ST production is given Subsequently 0bX111 1111 1111 1111 1111 1111 XXXX XXXX the option bits are l...

Page 140: ...ess is ignored and an illegal access event is generated Unprivileged read access is still allowed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCROP_RDP Res Res Res Res Res Res Res Res Res Res Res...

Page 141: ...leged write access is ignored and an illegal access event is generated Unprivileged read access is still allowed Bits 31 23 Reserved must be kept at reset value Bits 22 16 WRP1A_END 6 0 WRP area A end...

Page 142: ...OP1BER Address offset 0x038 Reset value 0xFFFF FF00 Default reset value from ST production is given Subsequently 0b1111 1111 1111 1111 1111 1111 XXXX XXXX the option bits are loaded with user values f...

Page 143: ...illegal access event is generated Unprivileged read access is still allowed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12...

Page 144: ...bit in FLASH_ACR are cleared The PESD bit in FLASH_SR and FLASH_C2SR are set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set Bits 14 12 Reserved must be kept at reset value Bit 11 ICRST...

Page 145: ...d protected area of the Flash memory PCROP protection An interrupt is generated if RDERRIE is set in FLASH_CR This bit is cleared by writing 1 Bits 13 10 Reserved must be kept at reset value Bit 9 FAS...

Page 146: ...same double word 64 bit Flash memory in case of standard programming or if there is a change of page during fast programming This bit is cleared by writing 1 Bit 4 WRPERR write protection error This b...

Page 147: ...le This bit enables the interrupt generation when EOP in FLASH_SR is set to 1 0 EOP Interrupt disabled 1 EOP Interrupt enabled Bits 23 19 Reserved must be kept at reset value Bit 18 FSTPG fast program...

Page 148: ...is generated Unprivileged read access is still allowed This register except for the DDS bit is further write protected by HDPADIS when HDPAD 0 The write protected bits can only be written when HDPADI...

Page 149: ...memory hide protection area disabled Bits 22 16 HDPSA 6 0 user Flash memory hide protection area start address This bit is write protected when HDPAD 0 and HDPADIS 1 When FSD HDPAD 0 the user Flash m...

Page 150: ...V offset addresses SRAM1 or SRAM2 from start address 0x2000 0000 SBRV Note SBRV offset value must be kept within the SRAM area 1 SBRV offset addresses the Flash memory from start address 0x0800 0000 S...

Page 151: ...000 0x01 backup SRAM2 start address offset 0x0000 0400 0x1F backup SRAM2 start address offset 0x0000 7C00 Bits 17 16 Reserved must be kept at reset value Bits 15 0 SBRV 15 0 CPU2 boot reset vector Thi...

Page 152: ...PROGERR Res OPERR EOP Reset value X X X 0 0 0 0 0 0 0 0 0 0 0 0 0x014 FLASH_CR LOCK OPTLOCK Res Res OBL_LAUNCH RDERRIE ERRIE EOPIE Res Res Res Res Res FSTPG OPTSTRT STRT Res Res Res Res Res Res PNB 6...

Page 153: ...Res Res Res Res Res Res Res Res Res PES Res Res Res ICRST Res ICEN PRFTEN Res Res Res Res Res Res Res Res Reset value 0 0 1 0 0x060 FLASH_C2SR Res Res Res Res Res Res Res Res Res Res Res Res PESD CFGB...

Page 154: ...pin a digital modem bank providing the following modulation schemes LoRa Rx Tx with bandwidth BW from 7 8 500 kHz spreading factor SF 5 12 bit rate BR from 0 013 to 17 4 Kbit s real bitrate FSK and G...

Page 155: ...4V1 Sub GHz radio Sub GHz RF frontend Radio control SUBGHZSPI hse32 Interrups RFO_LP RFO_HP RFI_P RFI_N FSK modem LoRa modem note Data and control HSE32 OSC_IN OSC_OUT BUSY HSERDY HSEON HSEBYPPWR Note...

Page 156: ...G PA must be supplied directly from VDD on VDDSMPS pin as shown in the figure below Figure 10 High output power PA HSEBYPPWR Digital input Enable VDDTCXO regulator control HSERDY Digital output HSE32...

Page 157: ...Q signals are low pass filtered and a ADC converts them into the digital domain In the digital modem the signals are decimated further down converted and channel filtered The demodulation is done acco...

Page 158: ...ive chains The RF PLL uses auto calibration and uses the 32 MHz HSE32 reference The sub GHz radio covers all continuous frequencies in the range between 150 to 960 MHz 5 3 6 Intermediate frequencies T...

Page 159: ...also be used by the MCU The use of an external crystal XTAL or a temperature compensated crystal oscillator TCXO are supported The used clock source is configured in the RCC see Section 7 2 1 HSE32 cl...

Page 160: ...a modems support both transmission and reception The G MSK and BPSK modems only supports transmission The framing determines how the bit stream is translated in packets and how data is stored in the d...

Page 161: ...ows the use of a higher effective data rate and reduces the transmission time at the expense of a reduced sensitivity less link budget and shorter range The LoRa modem operates at a programmable bandw...

Page 162: ...th the low data rate optimization is usually recommended when the LoRa symbol time is equal or above 16 38 ms When using LoRa modulation the total frequency drift over the packet time must be kept low...

Page 163: ...header with CRC then followed by the payload and payload CRC In the implicit packet format the preamble is directly followed by the payload and payload CRC The payload is a variable length field that...

Page 164: ...r of payload fractional symbols in Implicit mode can be calculated as follows NbSymbolPayloadFrac PL x 8 CRC x 16 4 x SF 2 x 4 CR 4 x SF where CRC 0 no CRC or 1 16 bit CRC CR 0 to 4 PL 1 to 255 user d...

Page 165: ...nd transmit The received signal is demodulated like FSK in the frequency domain non coherent 5 5 4 MSK modem The MSK modem provides a 2 MSK modulation over a range of data rates from 0 1 Kbit s up to...

Page 166: ...is optional and can be used for a unicast when several devices share the same syncword In the variable length generic packet format the syncword is followed by the length of the payload If the Addres...

Page 167: ...payload and when present the header and CRC Whitening limits a sequence of consecutive 1 or 0 bit to nine The whitening polynomial is x9 x5 1 and can be initialized with the whitening initial value i...

Page 168: ...used TxBaseAddr 0x80 and RxBaseAddr 0x00 or RxPayloadLength and RxStartBufferPointer must be stored in the CPU memory On die revision Y and later the PayloadLength can be updated during transmission T...

Page 169: ...ion at which it was left by the previous received packet In this mode subsequent received packets are stored continuous in the RAM data buffer Caution If the amount of received data exceeds the define...

Page 170: ...Active mode FS TX RX Frequency synthesis FS mode RF PLL switched on Transmit TX mode the power amplifier PA ramped and data transmitted from the data buffer according the selected modulation scheme R...

Page 171: ...Exit Sleep mode can be done on a firmware request via the sub GHz radio SPI NSS signal keeping sub GHz radio SPI NSS low for at least 20 s on a request from the sub GHz radio RTC timer generating an...

Page 172: ...d the SMPS is enabled automatically when entering the Standby with HSE32 mode If the SMPS has been enabled by the CPU with PWR_CR5 SMPSEN the SMPS remains enabled in all sub GHz radio operating modes...

Page 173: ...edly switches between RX single with timeout mode and Sleep mode until an IRQ is triggered RX mode entry is requested by Set_Rx command When entering RX mode BUSY is set In RX mode BUSY is cleared whe...

Page 174: ...ing time Mode transition SPI command sub GHz radio event tSWMODE typical s Sleep to Standby no data retention SPI NSS low 20 s 3500 Sleep to Standby with data retention SPI NSS low 20 s RTC end of cou...

Page 175: ...adio and consists of a status when reading data In case of a write command that does not require any parameters the CPU sent only an opcode over the sub GHz radio SPI interface In case of a write comm...

Page 176: ...d from a contiguous data memory area starting from the specified byte 0 bits 7 0 Opcode 0x0D bytes 2 1 bits 15 0 Addr 15 0 first write address byte 3 bits 7 0 Data0 7 0 data to write to first address...

Page 177: ...7 0 see Get_Status command byte 3 bits 7 0 Data0 7 0 data read from offset address byte n 3 bits 7 0 Datan 7 0 data read from offset address n n number of bytes to read 0 1 Opcode SleepCfg w w byte 0...

Page 178: ...out x 15 625 s maximum time out duration 262 14 s When Set_Tx Timeout is sent in Standby or Receive mode the sub GHz radio passes through the FS mode no need to send Set_Fs In this case the RF PLL fre...

Page 179: ...e detection may cause the sub GHz radio to remain in Receive mode for an unexpected long period until stopped by a mode configuration command Set_RxDutyCycle command Set_RxDutyCycle RxPeriod SleepPeri...

Page 180: ...ved during the listening period the sub GHz radio issues a RxDone interrupt and enters Standby mode if SetStandby is sent during the listening period or after the sub GHz has been requested to exit Sl...

Page 181: ...sending Set_Cad Set_TxContinuousWave command Set_TxContinuousWave is a test command to generate a continuous transmit tone at the RF PLL frequency The sub GHz radio remains in continuous transmit ton...

Page 182: ...Changing from one sub GHz radio configuration to another is done using Set_PacketType The parameters from the previous sub GHz radio configuration are lost The switch from one configuration mode to a...

Page 183: ...eq 31 0 RF frequency RF PLL frequency 32e6 x RFfreq 225 0 1 2 Opcode Power 7 0 RampTime 7 0 w w w byte 0 bits 7 0 Opcode 0x8E byte 1 bits 7 0 Power 7 0 Output power setting LP PA selected in Set_PaCon...

Page 184: ...0 2 0 04 x PaDutyCycle 2 0 see Table 35 for settings Caution The following restrictions must be observed to avoid over stress on the PA LP PA mode with synthesis frequency 400 MHz PaDutyCycle must be...

Page 185: ...cket transmission or packet reception 0x20 Standby mode entry default 0x30 Standby with HSE32 enabled mode entry 0x40 FS mode entry Others reserved 0 1 2 3 4 5 6 7 Opcode NbCadSymbol 2 0 CadDetPeak 7...

Page 186: ...l is detected during the CAD scan if a LoRa symbol is detected the sub GHz radio stays in Receive mode until a packet is received or until the CAD timeout is reached bytes 7 5 bits 23 0 Timeout 23 0 C...

Page 187: ...are used for the transmission and reception Bw is used only for reception PulseShape represents the Gaussian filter that can be used to filter the modulation stream at the transmitter 0 1 2 3 4 5 6 7...

Page 188: ...0 kHz DSB 0x14 BW46 46 9 kHz DSB 0x0C BW58 58 6 kHz DSB 0x1B BW78 78 2 kHz DSB 0x13 BW93 93 8 kHz DSB 0x0B BW117 117 3 kHz DSB 0x1A BW156 156 2 kHz DSB 0x12 BW187 187 2 kHz DSB 0x0A BW234 234 3 kHz D...

Page 189: ...62 62 50 kHz 0x04 bandwidth 125 125 kHz 0x05 bandwidth 250 250 kHz 0x06 bandwidth 500 500 kHz Others reserved byte 3 bits 7 3 Reserved must be kept at reset value bits 2 0 Cr 2 0 Forward error correct...

Page 190: ...of bit symbols 0x0 preamble detection disabled 0x4 8 bit preamble detection 0x5 16 bit preamble detection 0x6 24 bit preamble detection 0x7 32 bit preamble detection Others reserved byte 4 bit 7 Rese...

Page 191: ...RC 0x1 no CRC 0x2 2 byte CRC 0x4 1 byte inverted CRC 0x6 2 byte inverted CRC Others reserved byte 9 bits 7 1 Reserved must be kept at reset value bit 0 Whitening Whitening enable The whitening initial...

Page 192: ...yte 5 bits 7 1 Reserved must be kept at reset value bit 0 CrcType CRC enable 0 CRC disabled 1 CRC enabled byte 6 bits 7 1 Reserved must be kept at reset value bit 0 InvertIQ IQ setup 0 standard IQ set...

Page 193: ...RC 13 MHz 0x3 Standby mode with HSE32 0x4 FS mode 0x5 RX mode 0x6 TX mode Others reserved bits 3 1 Status_CmdStatus 2 0 Command status 0x2 data available to host packet received successfully and data...

Page 194: ...fset in the RAM data buffer where the first byte of the last received packet is stored 0 1 2 3 4 Opcode Status 7 0 RxStatus 7 0 RssiSync 7 0 RssiAvg 7 0 w r r r r byte 0 bits 7 0 Opcode 0x14 byte 1 bi...

Page 195: ...I level over the received packet Signal power RssiPkt 2 in dBm byte 3 bits 7 0 SnrPkt 7 0 Estimation of SNR over the received packet SNR SnrPkt 4 in dB byte 4 bits 7 0 SignalRssiPkt 7 0 Estimation of...

Page 196: ...and operating mode Each of these interrupt sources can be enabled or masked and mapped on any of the IRQ interrupts A set of commands is used to configure and control the IRQ sources and interrupt gen...

Page 197: ...Channel activity detection finished LoRa Cad 8 CadDetected Channel activity detected LoRa Cad 9 Timeout RX or TX timeout LoRa and GFSK Rx and Tx 15 10 Not applicable Reserved Not applicable 0 1 2 3 4...

Page 198: ...BUSY is set A falling edge on BUSY indicates the end of all enabled calibrations 0 1 2 3 Opcode Status 7 0 IrqStatus 15 0 w r r r byte 0 bits 7 0 Opcode 0x12 byte 1 bits 7 0 Status 7 0 see Get_Status...

Page 199: ...Image calibration disabled 1 Image calibration enabled bit 5 CalibCfg_AdcBulkP RF ADC bulk P calibration 0 RF ADC bulk P calibration disabled 1 RF ADC bulk P calibration enabled bit 4 CalibCfg_AdcBulk...

Page 200: ...selection between LDO mode default and SMPS mode when in Standby with HSE32 and Active modes Note For the different CPU operating modes the LDO or SMPS mode is controlled by the SMPSEN bit inPWR cont...

Page 201: ...at reset value bit 8 OpError_PaRampError PA ramping failed bit 7 Reserved must be kept at reset value bit 6 OpError_PllLockError RF PLL locking failed bit 5 OpError_XoscStartError HSE32 clock startup...

Page 202: ...imeout disabled 0x1 1 7 Other timeout enabled 2 2 Maximum time the system waits for the HSE32 clock to be ready before HSEStartErr is set 0x2 1 8 0x3 2 2 0x4 2 4 0x5 2 7 0x6 3 0 0x7 3 3 Table 41 Sub G...

Page 203: ...0x8C PbLength PdDetLength SyncWordLength AddrComp PktType PayloadLength CrcType Whitening LoRa PbLength HeaderType PayloadLength CrcType InvertIQ BPSK PayloadLength Set_PacketType 0x8A PktType Set_Reg...

Page 204: ...ayload data to the transmit data buffer with Write_Buffer 3 Select the packet type generic or LoRa with Set_PacketType 4 Define the frame format with Set_PacketParams 5 Define synchronization word in...

Page 205: ...in RX mode with Set_Rx When in continuous receiver mode the sub GHz radio remains in RX mode to look for packets until stopped with Set_Standby In single mode with or without timeout when the recepti...

Page 206: ...rupts by configuring IRQ with Cfg_DioIrq 10 Start the transmission by setting the sub GHz radio in TX mode with Set_Tx After the transmission is finished the sub GHz radio enters automatically the Sta...

Page 207: ...inverted 1 receive data inverted Bit 4 BITSYNCDIS LoRa normal bit synchronization enable This bit must be cleared to 0 when using generic packet and BPSK type 0 normal bit synchronization enabled 1 n...

Page 208: ...ue 0x10 Bits 7 0 WHITEINI 7 0 Generic packet whitening initial value LSB bits 7 0 7 6 5 4 3 2 1 0 CRCINI 15 8 rw rw rw rw rw rw rw rw Bits 7 0 CRCINI 15 8 Generic packet CRC initial polynomial MSB bit...

Page 209: ...x23 5 10 10 Sub GHz radio generic synchronization word control register 5 SUBGHZ_GSYNCR5 Address offset 0x06C2 Reset value 0x52 7 6 5 4 3 2 1 0 CRCPOLI 7 0 rw rw rw rw rw rw rw rw Bits 7 0 CRCPOLI 7 0...

Page 210: ...ub GHz radio generic synchronization word control register 1 SUBGHZ_GSYNCR1 Address offset 0x06C6 Reset value 0x65 Bits 7 0 SYNCWORD 47 40 Sixth byte of generic packet synchronization word 7 6 5 4 3 2...

Page 211: ...0741 Reset value 0x24 Bits 7 0 SYNCWORD 15 8 Second byte of generic packet synchronization word 7 6 5 4 3 2 1 0 SYNCWORD 7 0 rw rw rw rw rw rw rw rw Bits 7 0 SYNCWORD 7 0 First byte of generic packet...

Page 212: ...ess offset 0x081B Reset value 0x00 5 10 21 Sub GHz radio random number register 0 SUBGHZ_RNGR0 Address offset 0x081C Reset value 0x00 7 6 5 4 3 2 1 0 RNDATA 31 24 r r r r r r r r Bits 7 0 RNDATA 31 24...

Page 213: ..._ADJUST 5 0 Sensitivity Floor of AGC This bitfield must be kept at 0x25 Bits 1 0 PMODE 1 0 Receiver power mode selection between normal mode and power saving mode 00 power saving mode reduced sensitiv...

Page 214: ...11 3 pF 0x12 value 20 3 pF default 0x2F maximum capacitor value 33 4 pF Others reserved 7 6 5 4 3 2 1 0 Res Res TRIM 5 0 rw rw rw rw rw rw Bits 7 6 Reserved must be kept at reset value Bits 5 0 TRIM...

Page 215: ...limiter disabled unlimited current 1 power supply current limiter enabled current limited according to CLV 1 0 Bits 5 4 CLV 1 0 Power supply current limiter value When the power supply current limite...

Page 216: ...BE SUBGHZ_GCRCPOLRH CRCPOL 15 8 Reset value 0 0 0 1 0 0 0 0 0x06BF SUBGHZ_GCRCPOLRL CRCPOL 7 0 Reset value 0 0 1 0 0 0 0 1 0x06C0 SUBGHZ_GSYNCR7 SYNCWORD 63 56 Reset value 1 0 0 1 0 1 1 1 0x06C1 SUBGH...

Page 217: ...0 0 1 0 1 0 0 0x08B0 to 0x08E6 Reserved Reserved 0x08E7 SUBGHZ_PAOCPR Res Res OCP 5 0 Reset value 0 1 1 0 0 0 0x08E8 to 0x0910 Reserved Reserved 0x0911 SUBGHZ_HSEINTRIMR Res Res TRIM 5 0 Reset value...

Page 218: ...wer supply for A D converters D A converters voltage reference buffer and comparators The VDDA voltage level is independent from the VDD voltage see power up and power down limitations below and must...

Page 219: ...y become lower then other supplies only if the energy provided to the device remains below 1 mJ This allows external decoupling capacitors to be discharged with different time constants during this tr...

Page 220: ...be checked with the SMPSRDY flag in Power status register 2 PWR_SR2 Note When the radio is active the supply mode is not changed until after the radio activity is finished During Stop 1 Stop 2 and Sta...

Page 221: ...pheral voltage monitoring and compared with a threshold 1 65 V for PVM3 See Section 6 2 3 Peripheral voltage monitoring PVM for more details When a single supply is used VDDA can be externally connect...

Page 222: ...up registers TAMP PA0 TAMP_IN2 and PB3 TAMP_IN3 when they are configured by the TAMP as tamper pins Note Due to the fact that the analog switch can transfer only a limited amount of current 3 mA the u...

Page 223: ...VCORE domain preserving the contents of all or part of the registers and of internal SRAM1 and SRAM2 In Standby modes with SRAM2 content preserved RRS bit set in the PWR control register 3 PWR_CR3 the...

Page 224: ...PWR control register 1 PWR_CR1 2 Wait until the VOSF flag is cleared in the Power status register 2 PWR_SR2 3 Adjust number of wait states according new frequency target in range 1 LATENCY bits in the...

Page 225: ...This event is internally connected to the EXTI line 16 and can generate an interrupt if enabled through the EXTI registers The PVD output interrupt can be generated when VDD or voltage level on PVD_I...

Page 226: ...ly voltage is above the PVMx threshold and is set when the supply voltage is below the PVMx threshold Each PVM output is connected to an EXTI line and can generate an interrupt if enabled through the...

Page 227: ...it for the PVM3 wakeup time c Wait until PVMO3 is cleared in the Power status register 2 PWR_SR2 d Disable the PVM3 for consumption saving optional 2 Enable the analog peripheral This automatically re...

Page 228: ...ins high When transferring a command with an expected radio busy indication the RFBUSYMS status must be used to detect the radio busy state When transferring a command without any expected radio busy...

Page 229: ...de CPU2 boots when it is woken up via a wakeup source C2BOOT 0 When exiting a system low power mode CPU2 is prevented from booting except when the system is secure and an illegal access wakeup event i...

Page 230: ...ly goes back to CStop After C2BOOT is set CPU2 is woken up by its wakeup source MSv50976V1 RUN LP RUN ILAC handling STANDBY Enter STANDBY STOP0 STOP1 STOP2 LP_STOP CPU2 CSTOP CPU1 CSTOP CPU2 CSTOP BOO...

Page 231: ...r is in Run mode after a system or a power reset and at least one of the CPUs is in CRun mode executing code Low power modes are available to save power when the CPU does not need to be kept running f...

Page 232: ...her MSI up to 48 MHz or HSI16 depending on the software configuration Standby mode VCORE domain is powered off However it is possible to preserve the SRAM2 content as detailed below Standby mode with...

Page 233: ...modes on its own When CPU2 has boot CPU1 CPU2 and radio sub systems can enter and wak eup from system low power modes on their own The system low power mode to enter depends on the allowed mode selec...

Page 234: ...et CPU1 CRUN or CSLEEP CPU2 CRUN or CSLEEP CPU2 CRUN or CSLEEP CPU1 CSTOP CPU1 CRUN or CSLEEP CPU2 CSTOP CPU2 CRUN or CSLEEP CPU1 CSTOP STANDBY CPU2 CSTOP CPU1 CSTOP C1STOP C1_wakeup C2STOP C1STOP HCL...

Page 235: ...the EXTI registers Specific peripherals events HSI16 when STOPWUCK 1 in RCC_CFGR MSI with the frequency before entering the Stop mode when STOPWUCK 0 All clocks OFF except HSI16 LSI and LSE ON ON Sto...

Page 236: ...Programmable voltage detector PVD O O O O O O O O O O O 5 O 5 Peripheral voltage monitor PVM3 O O O O O O O O O O DMAx x 1 2 O O O O R R DMAMUX1 O O O O R R High speed internal HSI16 O O O O O 6 O 6...

Page 237: ...O R O R R R R HSEM O R O R R R GTZC TZSC O R O R R R R GTZC TZIC O R O R R R R EXTI O O O O R O R O R O GPIOs O O O O O O O O O O R 11 3 pin s 12 13 3 pin s 1 2 1 Legend Y Yes enable O Optional disab...

Page 238: ...e 46 MCU and sub GHz radio operating modes CPU operating mode Sub GHz radio operating mode 1 Description Run Sleep Sleep Calibration Standby Active FS TX RX 2 LDO or SMPS regulator active MCU running...

Page 239: ...and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption In Sleep mode to further reduce the power consumption the peripheral clocks can be disabled...

Page 240: ...rce the regulator in main mode by clearing the LPR bit in the PWR control register 1 PWR_CR1 2 Wait until REGLPF bit is cleared in the Power status register 2 PWR_SR2 3 Increase the HCLK clock frequen...

Page 241: ...heral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit in the NVIC interrupt clear pending register must be cleared All NVIC interrupts wake up the CPU even the disab...

Page 242: ...to CPU1 1 0 0 0 Wakeup from Standby but system is already in Run due to CPU2 Wakeup from Run 0 0 1 0 Wakeup from Run Wakeup from Standby but system is already in Run due to CPU1 1 1 0 0 Wakeup from St...

Page 243: ...leep mode by issuing an interrupt or an event the MCU is in LPRun mode Table 49 Sleep mode Sleep mode Description Mode entry WFI wait for interrupt or WFE wait for event while SLEEPDEEP 0 No interrupt...

Page 244: ...t consumption in this mode but any drop of the voltage below the operating conditions between two active periods of the supply detector results in a non generation of PDR reset I O states in Stop 0 mo...

Page 245: ...eripherals can be used in Stop 0 mode and can add consumption if they are enabled and clocked by LSI or LSE LPTIMx x 1 2 3 I2Cx x 1 2 3 USARTx x 1 2 LPUART1 In Stop 0 mode when HSIKERON is enabled the...

Page 246: ...de all EXTI line pending bits in EXTI pending register EXTI_PR1 and EXTI pending register EXTI_PR2 and the peripheral flags generating wakeup interrupts must be cleared Otherwise the Stop 0 mode entry...

Page 247: ...while SLEEPDEEP bit is set in Cortex system control register SLEEPONEXIT 1 No interrupt is pending LPMS 0b001 in PWR_CR1 and or PWR_C2CR1 or higher Note To enter Stop 1 mode all EXTI line pending bits...

Page 248: ...e Stop 2 mode entry is delayed until the memory access is finished If an access to the APB domain is ongoing The Stop 2 mode entry is delayed until the APB access is finished Several peripherals can b...

Page 249: ...led by setting the ULPEN bit of the PWR_CR3 register allows the current consumption to be decreased in this mode but any drop of the voltage below the operating conditions between two active periods o...

Page 250: ...dent watchdog IWDG the IWDG is started by writing to its key register or by hardware option Once started it cannot be stopped except by a reset See Section 30 3 IWDG functional description Real time c...

Page 251: ...r LSE are also functional Three wakeup pins WKUPx x 1 2 3 and the three TAMP tampers are available Enter Shutdown mode The Shutdown mode is entered according Section 6 5 3 when the SLEEPDEEP bit in th...

Page 252: ...external interrupt Auto wakeup mode The RTC provides a programmable time base for waking up from Stop 0 1 or 2 or Standby mode at regular intervals For this purpose the Table 55 Shutdown mode Shutdown...

Page 253: ...to configure the EXTI line 18 To wakeup from Stop mode with an RTC wakeup event it is necessary to Configure the EXTI line 20 to be sensitive to rising edge Configure the RTC to generate the RTC alarm...

Page 254: ...dden by hardware Bit 8 DBP Disable Backup domain write protection In reset state the RTC and backup registers are protected against parasitic write access This bit must be set to enable write access t...

Page 255: ...R NSS RFBUSYMS functionality enabled 1 sub GHz SPI NSS signal driven from LPTIM3_OUT RFBUSYMS functionality disabled Bits 2 0 LPMS 2 0 Low power mode selection for CPU1 These bits are not reset when e...

Page 256: ...ck is set in the SYSCFG_CBR register These bits are reset only by a system reset Bit 0 PVDE Programmable voltage detector enable 0 Programmable voltage detector disabled 1 Programmable voltage detecto...

Page 257: ...power regulator in Standby mode SRAM2 content kept Bit 8 EWPVD PVD and wakeup for CPU1 enable when sub GHz radio in active state This bit is set and reset by software When this bit is set the PVD is...

Page 258: ...r 4 PWR_CR4 Bit 0 EWUP1 wakeup pin WKUP1 for CPU1 enable When this bit is set the external wakeup pin WKUP1 is enabled and triggers an interrupt and wakeup from Stop Standby or Shutdown event when a r...

Page 259: ...he polarity used for an event detection on external wake up pin WKUP2 0 Detection on high level rising edge 1 Detection on low level falling edge Bit 0 WP1 Wakeup pin WKUP1 polarity This bit defines t...

Page 260: ...by writing 1 in the CWUF2 bit of the PWR status clear register PWR_SCR Bit 0 WUF1 Wakeup flag 1 This bit is set when a wakeup event is detected on wakeup pin WKUP1 It is cleared by writing 1 in the C...

Page 261: ...SRAM2 disabled the wakeup time from Standby mode may be increased 0 LPR not ready 1 LPR ready Bit 7 FLASHRDY Flash memory ready This bit is set by hardware when the Flash memory can be accessed by sof...

Page 262: ...rce 0 CPU2 booted from an illegal access event 1 CPU2 booted from a C2BOOT request 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14...

Page 263: ...SR1 register This bit is always read as 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMPSEN R...

Page 264: ...7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 0 PU 15 0...

Page 265: ...0 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 0 PU...

Page 266: ...es Res Res Res Res Res PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 13 PU 15 13 Port PC y pull up y 13 to 15 When set each bit acti...

Page 267: ...egister 3 PWR_CR3 and in PWR CPU2 control register 3 PWR_C2CR3 Bits 12 7 Reserved must be kept at reset value Bits 6 0 PD 6 0 Port PC y pull down bit y y 0 to 6 When set each bit activates the pull do...

Page 268: ...ry power down mode during LPSleep for CPU2 This bit selects whether the Flash memory is in power down mode or Idle mode when both CPUs are in Sleep mode Flash memory is only set in power down mode whe...

Page 269: ...top 2 In Standby mode SRAM2 is preserved depending on RRS bit configuration in PWR control register 3 PWR_CR3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Re...

Page 270: ...3 Reserved must be kept at reset value Bit 2 EWUP3 Enable wakeup pin WKUP3 for CPU2 When this bit is set the external wakeup pin WKUP3 is enabled and triggers an interrupt and wakeup from Stop Standb...

Page 271: ...by flag for CPU2 no core states retained This bit is set by hardware and cleared only by a POR reset or by setting C2CSSF bit 0 System has not been in Standby mode 1 System has been in Standby mode Bi...

Page 272: ...s offset 0x090 Reset value 0x0000 8000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2EWILA Res...

Page 273: ...y software and is used to control the sub GHz SPI NSS level from software 0 sub GHz SPI NSS signal at level low 1 sub GHz SPI NSS signal is at level high Bits 14 0 Reserved must be kept at reset value...

Page 274: ...WRFBUSYF Res Res WPVDF Res Res Res Res Res WUF3 WUF2 WUF1 Reset value 0 0 0 0 0 0 0 0x014 PWR_SR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PVMO3 Res Res PVDO VOSF REGLPF REG...

Page 275: ...CR1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res FPDS FPDR Res LPMS 2 0 Reset value 0 0 1 1 1 0x084 PWR_C2CR3 Res Res Res Res Res Res Res Res...

Page 276: ...cified in the register description A system reset is generated when one of the following events occurs a low level on the NRST pin external reset window watchdog event WWDG reset independent watchdog...

Page 277: ...entry sequence is successfully executed the device is reset instead of entering Standby mode Entering Stop mode this type of reset is enabled by resetting nRST_STOP bit in user option bytes In this c...

Page 278: ...can be monitored in SYSCFG_SCSR PKASRAMBSY flag register bit 7 2 Clocks The following different clock sources can be used to drive the system clock SYSCLK HSI16 high speed internal 16 MHz RC oscillato...

Page 279: ...HSI16 or LSE The I2Cs clocks are derived selected by software from one of the following sources system clock SYSCLK only available in Run mode HSI16 clock available in Run and Stop modes APB clock PCL...

Page 280: ...work either with this clock or directly with the CPU1 clock HCLK1 configurable in the SysTick control and status register FCLK1 acts as CPU1 free running clock For more details refer to the programmi...

Page 281: ...close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time MSv62604V2 LSI RCC 32 kHz LSE OSC 32 768 kHz LSCO to IWDG HSE32 OSC 32 MHz HSE CSS OSC_IN...

Page 282: ...r the HSE32 frequency drift requirements related to the sub GHz radio see Section 5 5 1 LoRa modem The HSERDY flag in the RCC clock control register RCC_CR indicates if the HSE32 oscillator is stable...

Page 283: ...ly can be provided by the device on PB0 VDDTCXO The VDDTCXO supply is also enabled with the HSEBYPPWR bit in RCC clock control register RCC_CR before enabling the HSE32 oscillator VDDTCXO supply level...

Page 284: ...ation using the HSITRIM 6 0 bits in the RCC internal clock sources calibration register RCC_ICSCR For more details on how to measure the HSI16 frequency variation refer to Section 7 2 20 Internal exte...

Page 285: ...re TA 25 C After reset the factory calibration value is loaded in the MSICAL 7 0 bits in the RCC internal clock sources calibration register RCC_ICSCR If the application is subject to voltage or tempe...

Page 286: ...between robustness and short start up time on one side and low power consumption on the other side The LSE drive can be decreased to the lower drive capability LSEDRV 0 when the LSE is on However onc...

Page 287: ...C control status register RCC_CSR indicates if the LSI oscillator is stable or not At startup the clock is not released until this bit is set by hardware An interrupt can be generated if enabled in th...

Page 288: ...nerated to inform the software about the failure allowing the MCU to perform rescue operations The HSE32 CSS interrupt is linked to the CPU1 and CPU2 NMI non maskable interrupt exception vector Note O...

Page 289: ...terrupt flag register RCC_CIFR RCC clock interrupt clear register RCC_CICR The software must then disable the LSECSSON bit stop the defective 32 kHz oscillator disabling LSEON and change the RTC clock...

Page 290: ...he LSE clock is in the Backup domain whereas the HSE32 and LSI clocks are not with the following consequences If LSE is selected as RTC clock the RTC continues to work even if the VDD supply is switch...

Page 291: ...be output onto the external MCO pin One of the following clock signals can be selected as the MCO clock SYSCLK MSI HSI16 only available when enabled by HSION HSE32 PLLRCLK LSI LSE PLLPCLK PLLQCLK The...

Page 292: ...of the MCU This selection is performed through the TI1_RMP 1 0 bits in the TIM16_OR register The possibilities are listed below TIM16 channel1 is connected to the GPIO refer to the alternate function...

Page 293: ...d HSI16 oscillator both have dedicated user accessible calibration bits for this purpose The basic concept consists in providing a relative measurement the HSI16 LSE ratio the precision is therefore c...

Page 294: ...The enable bits have a synchronization mechanism to create a glitch free clock for the peripheral After the enable bit is set there is a two clock cycles delay before the clock is active in the periph...

Page 295: ...TIMs can also be driven by the LSE oscillator when the system is in Stop mode if LSE is selected as clock source for that peripheral and the LSE oscillator is enabled LSEON In that case LSE remains al...

Page 296: ...zation time must be waited for after wakeup even if LSE was kept on during the Stop mode When exiting Standby mode the system clock is MSI at 4 MHz When exiting Shutdown modes the system clock is MSI...

Page 297: ...is bit cannot be reset if the main PLL clock is used as the system clock 0 Main PLL off 1 Main PLL on Bits 23 22 Reserved must be kept at reset value Bit 21 HSEBYPPWR HSE32 VDDTCXO output on package p...

Page 298: ...y Note Once HSIKERON is cleared HSIKERDY goes low after six HSI16 clock cycles Bit 11 HSIASFS HSI16 automatic start from Stop modes This bit is set and cleared by software When the system wakeup clock...

Page 299: ...1 around 48 MHz Others not allowed hardware write protection Caution This field can be modified only when MSI is off MSION 0 or when MSI is ready MSIRDY 1 This filed must not be modified when MSI is o...

Page 300: ...r r r r r r r r Bit 31 Reserved must be kept at reset value Bits 30 24 HSITRIM 6 0 HSI16 clock trimming These bits provide an additional user programmable trimming value that is added to the HSICAL 7...

Page 301: ...ept at reset value Bits 30 28 MCOPRE 2 0 Microcontroller clock output prescaler These bits are set and cleared by software It is highly recommended to change this prescaler before MCO output is enable...

Page 302: ...tion This bit is set and cleared by software to select the system clock used when exiting Stop mode The selected clock is also used as emergency clock for the CSS on HSE32 0 MSI oscillator selected as...

Page 303: ...please refer to Section 6 1 4 Dynamic voltage scaling management After a write operation to these bits and before decreasing the voltage range the HPREF bit must be read to be sure that the new value...

Page 304: ...31 29 PLLR 2 0 Main PLL division factor for PLLRCLK These bits are set and cleared by software to control the frequency of the main PLL output clock PLLRCLK This output can be selected as system clock...

Page 305: ...not used the value of PLLQEN must be 0 0 PLLQCLK output disabled 1 PLLQCLK output enabled Bits 23 22 Reserved must be kept at reset value Bits 21 17 PLLP 4 0 Main PLL division factor for PLLPCLK Thes...

Page 306: ...he main PLL input clock These bits are set and cleared by software to divide the PLL input clock before the VCO They can be written only when the PLL is disabled VCO input frequency PLL input clock fr...

Page 307: ...able interrupt caused by the CSS on LSE 0 Clock security interrupt caused by LSE clock failure disabled 1 Clock security interrupt caused by LSE clock failure enabled Bits 8 6 Reserved must be kept at...

Page 308: ...Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res LSE CSSF CSSF Res Res PLL RDYF HSE RDYF HSI RDYF MSI RDYF LSE RDYF LSI RDYF r r r r r r r...

Page 309: ...eady interrupt caused by the HSI16 oscillator Bit 2 MSIRDYF MSI ready interrupt flag This bit is set by hardware when the MSI clock becomes stable and MSIRDYDIE is set It is cleared by software settin...

Page 310: ...F flag 0 No effect 1 PLLRDYF flag cleared Bit 4 HSERDYC HSE32 ready interrupt clear This bit is set by software to clear the HSERDYF flag 0 No effect 1 HSERDYF flag cleared Bit 3 HSIRDYC HSI16 ready i...

Page 311: ...es Res DMA MUX1 RST DMA2 RST DMA1 RST rw rw rw rw Bits 31 13 Reserved must be kept at reset value Bit 12 CRCRST CRC reset This bit is set and cleared by software 0 No effect 1 CRC reset Bits 11 3 Rese...

Page 312: ...are 0 No effect 1 IO port B reset Bit 0 GPIOARST IO port A reset This bit is set and cleared by software 0 No effect 1 IO port A reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res R...

Page 313: ...reset This bit is set and cleared by software PKA reset is disabled when a hardware PKA SRAM erase is ongoing 0 No effect 1 PKA reset Bits 15 0 Reserved must be kept at reset value 31 30 29 28 27 26...

Page 314: ...eset Bits 20 18 Reserved must be kept at reset value Bit 17 USART2RST USART2 reset This bit is set and cleared by software 0 No effect 1 USART2 reset Bits 16 15 Reserved must be kept at reset value Bi...

Page 315: ...is bit is set and cleared by software 0 No effect 1 LPUART1 reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res TIM17 RST TIM16 RST Res rw rw 15 1...

Page 316: ...TIM1 reset Bit 10 Reserved must be kept at reset value Bit 9 ADCRST ADC reset This bit is set and cleared by software 0 No effect 1 ADC reset Bits 8 0 Reserved must be kept at reset value 31 30 29 28...

Page 317: ...Res Res Res Res Res Res DMA MUX1 EN DMA2 EN DMA1 EN rw rw rw rw Bits 31 13 Reserved must be kept at reset value Bit 12 CRCEN CPU1 CRC clock enable This bit is set and cleared by software 0 CRC clock...

Page 318: ...IOC EN GPIOB EN GPIOA EN rw rw rw rw Bits 31 8 Reserved must be kept at reset value Bit 7 GPIOHEN CPU1 IO port H clock enable This bit is set and cleared by software 0 IO port H clock disabled for CPU...

Page 319: ...sh interface clock disabled for CPU1 1 Flash interface clock enabled for CPU1 Bits 24 21 Reserved must be kept at reset value Bit 20 IPCCEN CPU1 IPCC interface clock enable This bit is set and cleared...

Page 320: ...1 Bit 30 Reserved must be kept at reset value Bit 29 DACEN CPU1 DAC clock enable This bit is set and cleared by software 0 DAC clock disabled for CPU1 1 DAC clock enabled for CPU1 Bits 28 24 Reserved...

Page 321: ...is reset by hardware system reset This bit is forced to 1 by hardware when the hardware WWDG_SW option is reset 0 Window watchdog clock disabled for CPU1 1 Window watchdog clock enabled for CPU1 Bit...

Page 322: ...1EN CPU1 Low power UART 1 clocks enable Set and cleared by software 0 LPUART1 bus and kernel clocks disable for CPU1 1 LPUART1 bus and kernel clocks enable for CPU1 31 30 29 28 27 26 25 24 23 22 21 20...

Page 323: ...software 0 TIM1 timer clock disabled for CPU1 1 TIM1P timer clock enabled for CPU1 Bit 10 Reserved must be kept at reset value Bit 9 ADCEN CPU1 ADC clocks enable This bit is set and cleared by softwa...

Page 324: ...ating during CPU1 CSleep mode disabled during CPU1 CStop mode Bits 11 3 Reserved must be kept at reset value Bit 2 DMAMUX1SMEN DMAMUX1 clock enable during CPU1 CSleep mode This bit is set and cleared...

Page 325: ...g during CPU1 CSleep mode disabled during CPU1 CStop mode Bits 6 3 Reserved must be kept at reset value Bit 2 GPIOCSMEN IO port C clock enable during CPU1 CSleep mode This bit is set and cleared by so...

Page 326: ...ock gating during CPU1 CSleep mode disabled during CPU1 CStop mode Bit 24 SRAM2SMEN SRAM2 memory interface clock enable during CPU1 CSleep mode This bit is set and cleared by software 0 SRAM2 clock di...

Page 327: ...MEN Res Res Res USART2 SMEN Res rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res SPI2S2 SMEN Res Res WWDG SMEN RTC APB SMEN Res Res Res Res Res Res Res Res Res TIM2 SMEN rw rw rw rw Bit 31...

Page 328: ...are 0 SPI2S2 clock disabled by the clock gating during CPU1 CSleep and CStop modes 1 SPI2S2 clock enabled by the clock gating during CPU1 CSleep mode disabled during CPU1 CStop mode Bits 13 12 Reserve...

Page 329: ...0 LPTIM3 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes 1 LPTIM3 bus clock enabled by the clock gating during CPU1 CSleep mode disabled during CPU1 CStop mode Bit 5 LPTIM2S...

Page 330: ...e 0 TIM16 clock disabled by the clock gating during CPU1 CSleep and CStop modes 1 TIM16 clock enabled by the clock gating during CPU1 CSleep mode disabled during CPU1 CStop mode Bits 16 15 Reserved mu...

Page 331: ...ing CPU1 CSleep mode disabled during CPU1 CStop mode Bits 8 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res R...

Page 332: ...lock selected Bits 29 28 ADCSEL 1 0 ADC clock source selection These bits are set and cleared by software to select the clock source used by the ADC interface 00 No clock selected 01 HSI16 clock selec...

Page 333: ...k source selection These bits are set and cleared by software to select the LPUART1 clock source 00 PCLK selected 01 System clock SYSCLK selected 10 HSI16 clock selected 11 LSE clock selected Bits 9 8...

Page 334: ...6 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res LSCO SEL LSCO EN Res Res Res Res Res Res Res BDRST rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCEN Res Res Res LSESY SRDY Res RTCSEL 1 0 LS...

Page 335: ...bled to USARTx LPUARTx LPTIMx TIMx RNG system LSCO MCO MSI PLL mode 1 LSE system clock enabled to USARTx LPUARTx LPTIMx TIMx RNG system LSCO MCO MSI PLL mode Note The LSE clock for the RTC is not impa...

Page 336: ...t and cleared by hardware to indicate when the external 32 kHz oscillator is stable 0 LSE oscillator not ready 1 LSE oscillator ready Note Once the LSEON bit is cleared this bit goes low after six LSE...

Page 337: ...et occurred 1 Software reset occurred Bit 27 BORRSTF BOR flag This bit is set by hardware when a BOR occurs It is cleared by writing to the RMVF bit 0 No BOR occurred 1 BOR occurred Bit 26 PINRSTF Pin...

Page 338: ...nge 7 around 8 MHz Others Not allowed hardware write protection Bits 7 5 Reserved must be kept at reset value Bit 4 LSIPRE LSI frequency prescaler This bit is set and cleared by software It can be wri...

Page 339: ...value Bit 17 C2HPREF HCLK2 prescaler flag CPU2 This bit is set and cleared by hardware to acknowledge HCLK2 prescaler programming It is reset when a new prescaler value is programmed in C2HPRE 3 0 Th...

Page 340: ...mic voltage scaling management After a write operation to these bits and before decreasing the voltage range the C2HPREF bit must be read to be sure that the new value is taken into account Bits 3 0 S...

Page 341: ...Res Res Res Res Res Res Res DMA MUX1 EN DMA2 EN DMA1 EN rw rw rw rw Bits 31 13 Reserved must be kept at reset value Bit 12 CRCEN CPU2 CRC clock enable This bit is set and cleared by software 0 CRC cl...

Page 342: ...s GPIOC EN GPIOB EN GPIOA EN rw rw rw rw Bits 31 8 Reserved must be kept at reset value Bit 7 GPIOHEN CPU2 IO port H clock enable This bit is set and cleared by software 0 IO port H clock disabled for...

Page 343: ...sh memory interface clock disabled for CPU2 1 Flash memory interface clock enabled for CPU2 Bits 24 21 Reserved must be kept at reset value Bit 20 IPCCEN CPU2 IPCC interface clock enable This bit is s...

Page 344: ...el clocks enabled for CPU2 Bit 30 Reserved must be kept at reset value Bit 29 DACEN CPU2 DAC clock enable This bit is set and cleared by software 0 DAC clock disabled for CPU2 1 DAC clock enabled for...

Page 345: ...s set and cleared by software RTC kernel clock is controlled by the RTCEN bit in the RCC_BDCR register 0 RTC APB bus clock disabled for CPU2 1 RTC APB bus clock enabled for CPU2 Bits 9 1 Reserved must...

Page 346: ...RT1 bus and kernel clocks enabled for CPU2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res TIM17 EN TIM16 EN Res rw rw 15 14 13 12 11 10 9 8 7 6 5 4...

Page 347: ...TIM1 clock disabled for CPU2 1 TIM1 clock enabled for CPU2 Bit 10 Reserved must be kept at reset value Bit 9 ADCEN ADC clocks enable This bit is set and cleared by software 0 ADC bus and kernel clocks...

Page 348: ...during CPU2 CSleep mode disabled during CPU2 CStop mode Bits 11 3 Reserved must be kept at reset value Bit 2 DMAMUX1SMEN DMAMUX1 clock enable during CPU2 CSleep and CStop modes This bit is set and cl...

Page 349: ...CPU2 CSleep mode disabled during CPU2 CStop mode Bits 6 3 Reserved must be kept at reset value Bit 2 GPIOCSMEN IO port C clock enable during CPU2 CSleep and CStop modes This bit is set and cleared by...

Page 350: ...ng during CPU2 CSleep mode disabled during CPU2 CStop mode Bit 24 SRAM2SMEN SRAM2 interface clock enable during CPU2 CSleep and CStop modes This bit is set and cleared by software 0 SRAM2 clock disabl...

Page 351: ...EN I2C2 SMEN I2C1 SMEN Res Res Res USART2 SMEN Res rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res SPI2S2 SMEN Res Res Res RTC APB SMEN Res Res Res Res Res Res Res Res Res TIM2 SMEN rw rw...

Page 352: ...ep mode disabled during CPU2 CStop mode Bits 16 15 Reserved must be kept at reset value Bit 14 SPI2S2SMEN SPI2S2 clock enable during CPU2 CSleep and CStop modes This bit is set and cleared by software...

Page 353: ...M3 bus and kernel clocks disabled by the clock gating during CPU2 CSleep and CStop modes 1 LPTIM3 bus clock enabled by the clock gating during CPU2 CSleep mode disabled during CPU2 CStop mode Bit 5 LP...

Page 354: ...e 0 TIM16 timer clock disabled by the clock gating during CPU2 CSleep and CStop modes 1 TIM16 timer clock enabled by the clock gating during CPU2 CSleep mode disabled during CPU2 CStop mode Bits 16 15...

Page 355: ...during CPU2 CSleep mode disabled during CPU2 CStop mode Bits 8 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Re...

Page 356: ...TOPWUCK Res PPRE2 2 0 PPRE1 2 0 HPRE 3 0 SWS 1 0 SW 1 0 Reset value 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00C RCC_ PLLCFGR PLLR 2 0 PLLREN PLLQ 2 0 PLLQEN Res Res PLLP 4 0 PLLPEN Res PLL...

Page 357: ...ACRST Res Res Res Res Res I2C3RST I2C2RST I2C1RST Res Res Res USART2RST Res Res SPI2S2RST Res Res Res Res Res Res Res Res Res Res Res Res Res TIM2RST Reset value 0 0 0 0 0 0 0 0 0x03C RCC_ APB1RSTR2 R...

Page 358: ...Res Res Res Res I2C3EN I2C2EN I2C1EN Res Res Res USART2EN Res Res SPI2S2EN Res Res WWDGEN RTCAPBEN Res Res Res Res Res Res Res Res Res TIM2EN Reset value 0 0 0 0 0 0 0 0 0 0 0x05C RCC_ APB1ENR2 Res R...

Page 359: ...alue 1 1 1 1 1 1 0x074 Reserved Reserved 0x078 RCC_APB1 SMENR1 LPTIM1SMEN Res DACSMEN Res Res Res Res Res I2C3SMEN I2C2SMEN I2C1SMEN Res Res Res USART2SMEN Res Res SPI2S2SMEN Res Res WWDGSMEN RTCAPBSM...

Page 360: ...es Res BDRST RTCEN Res Res Res LSESYSRDY Res RTCSEL 1 0 LSESYSEN LSECSSD LSECSSON LSEDRV 1 0 LSEBYP LSERDY LSEON Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x094 RCC_CSR LPWRRSTF WWDGRSTF IWDGRSTF SFTR...

Page 361: ...EN Res Res Res Res Res I2C3EN I2C2EN I2C1EN Res Res Res USART2EN Res Res SPI2S2EN Res Res Res RTCAPBEN Res Res Res Res Res Res Res Res Res TIM2EN Reset value 0 0 0 0 0 0 0 0 0 0x15C RCC_C2 APB1ENR2 Re...

Page 362: ...alue 1 1 1 1 1 1 0x174 Reserved Reserved 0x178 RCC_C2 APB1 SMENR1 LPTIM1SMEN Res DACSMEN Res Res Res Res Res I2C3SMEN I2C2SMEN I2C1SMEN Res Res Res USART2SMEN Res Res SPI2S2SMEN Res Res Res RTCAPBSMEN...

Page 363: ...RCC_C2 APB3SMENR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res SUBGHZSPISMEN Reset value 1 Table 63 RCC register map and r...

Page 364: ...are provided Locking a semaphore can be done in two ways 2 step lock by writing COREID and PROCID to the semaphore followed by a read check 1 step lock by reading the COREID from the semaphore Interru...

Page 365: ...signals 8 3 3 HSEM lock procedures There are two lock procedures namely 2 step write lock and 1 step read lock The two procedures 1 step and 2 step can be used concurrently MS40530V5 HSEM Interrupt i...

Page 366: ...lock procedure consists in a write to lock the semaphore followed by a read to check if the lock has been successful carried out from the HSEM_Rx register Write semaphore with PROCID and COREID and L...

Page 367: ...0x80 address offset In the first register address bank the semaphore can be written locked unlocked and read through the HSEM_Rx registers In the second register address bank the semaphore can be read...

Page 368: ...isters 8 3 7 HSEM interrupts An interrupt line hsem_intn_it per processor allows each semaphore to generate an interrupt An interrupt line provides the following features per semaphore interrupt enabl...

Page 369: ...x interrupt status for the interrupt line in HSEM_CnICR Re try to lock the semaphore x again If the semaphore lock is obtained no interrupt is needed semaphore has been freed between first try to lock...

Page 370: ...react locks the semaphore 8 3 8 AHB bus master ID verification The HSEM allows only authorized AHB bus master IDs to lock and unlock semaphores The AHB bus master 2 step lock write access to the sema...

Page 371: ...cked Bits 30 13 Reserved must be kept at reset value Bit 12 Reserved must be kept at reset value Bits 11 8 COREID 3 0 Semaphore COREID Written by software When the semaphore is free and the LOCK bit i...

Page 372: ...turns 1 When the semaphore is locked A read with a valid AHB bus master ID returns 1 the COREID and PROCID reflect the already locked semaphore information Bits 30 13 Reserved must be kept at reset va...

Page 373: ...his bit is read and written by software 0 Interrupt n generation for semaphore x disabled masked 1 Interrupt n generation for semaphore x enabled not masked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 374: ...Interrupt semaphore x status interrupt pending 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MI...

Page 375: ...12 Reserved must be kept at reset value Bits 11 8 COREID 3 0 COREID of semaphores to be cleared This field can be written by software and is always read 0 This field indicates the COREID for which the...

Page 376: ...3 0 PROCID 7 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0BC HSEM_RLR15 LOCK Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res COREID 3 0 PROCID 7 0 Reset value 0 0 0 0 0 0 0 0...

Page 377: ...0 0 0 0 0 0 0 0 0x140 HSEM_CR KEY 15 0 Res Res Res Res COREID 3 0 Res Res Res Res Res Res Res Res Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x144 HSEM_KEYR KEY 15 0 Res Res Res Res Res Res...

Page 378: ...rocessor One for TX channel free communication data retrieved by receiving processor Interrupt masking per channel Channel occupied mask Channel free mask Two channel operation modes Simplex each chan...

Page 379: ...channel mode a dedicated memory location used to transfer data in a single direction is assigned to the communication data The associated channel N control bits see Table 68 are used to manage the tra...

Page 380: ...mplex channel mode transfer timing Table 68 Bits used for the communication Processor A B SEND A 1 RECEIVE B 2 IPCC_C1CR TXFIE IPCC_C1MR CHnFM IPCC_C1SCR CHnS IPCC_C1TOC2SR CHnF IPCC_C2CR RXOIE IPCC_C...

Page 381: ...rrupt CHnFM 0 On a TX free interrupt the sending processor checks which channel became free and masks the channel free interrupt CHnFM 1 Then the new communication can take place Once the complete com...

Page 382: ...ping pong In Half duplex channel mode a single dedicated memory location is assigned to communication data and response and is used to transfer data in both directions The sending processor channel st...

Page 383: ...a Communication data Read Communication data Write Response Write Communication data Read Response Response Read Communication data Write Response Communication data Response MS42433V1 UNMASK Channel...

Page 384: ...ry access and generates the TX free interrupt to the sending processor Once the channel status flag CHnF is cleared the channel occupied interrupt is unmasked CHnOM 0 Figure 42 IPCC Half duplex Receiv...

Page 385: ...RX occupied interrupt is used by the receiving processor and indicates when an unmasked channel status indicates occupied CHnF 1 The TX free interrupt is used by the sending processor and indicates wh...

Page 386: ...ate an RX occupied interrupt 0 Processor 1 RX occupied interrupt disabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res CH6 FM CH5 FM CH4 FM CH3 FM CH2 FM CH1...

Page 387: ...h IPCC_C1TOC2SR CHnF 1 Processor 1 transmit channel n status bit set 0 No action Bits 15 6 Reserved must be kept at reset value Bits 5 0 CHnC Processor 1 receive channel n status clear n 6 to 1 Associ...

Page 388: ...rupt enable Associated with IPCC_C2TOC1SR 1 Enable an unmasked processor 2 transmit channel free to generate a TX free interrupt 0 Processor 2 TX free interrupt disabled Bits 15 1 Reserved must be kep...

Page 389: ...2SR CHnF 1 Receive channel n occupied interrupt masked 0 Receive channel n occupied interrupt not masked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res CH6S CH...

Page 390: ...9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res CH6F CH5F CH4F CH3F CH2F CH1F r r r r r r Bits 31 6 Reserved must be kept at reset value Bits 5 0 CHnF Processor 2 transmit to processor 1 r...

Page 391: ...s Res Res Res Res Res CH6C CH5C CH4C CH3C CH2C CH1C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x000C IPCC_C1TOC2SR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 392: ...ister GPIOx_ BSRR for bitwise write access to GPIOx_ODR Locking mechanism GPIOx_LCKR provided to freeze the I O port configurations Analog function Alternate function selection registers Fast toggle c...

Page 393: ...O port bit Table 70 gives the possible port bit configurations Figure 43 Basic structure of a standard I O port bit Alternate function output Alternate function input Push pull open drain or disabled...

Page 394: ...diode Protection diode on off Input driver Output driver down up P MOS N MOS Read Bit set reset registers Write Input data register ai15939e 1 VDD_FT is specific to 5V tolerant I Os and different fro...

Page 395: ...at every AHB clock cycle All GPIO pins have weak internal pull up and pull down resistors which can be activated or not depending on the value in the GPIOx_PUPDR register 10 3 2 I O pin alternate fun...

Page 396: ...registers For the additional functions like RTC WKUPx and oscillators configure the required function in the related RTC PWR and RCC registers These functions have priority over the configuration in...

Page 397: ...configuration during the write sequence LCKR 15 0 value must be the same When the LOCK sequence is applied to a port bit the value of the port bit can no longer be modified until the next MCU reset or...

Page 398: ...put buffer is enabled Open drain mode A 0 in the Output register activates the N MOS whereas a 1 in the Output register leaves the port in Hi Z the P MOS is never activated Push pull mode A 0 in the O...

Page 399: ...read access to the input data register gets the I O state The figure below shows the alternate function configuration of the I O port bit Figure 47 Alternate function configuration Push pull or Open...

Page 400: ...the LSEON bit in the RCC_CSR register the oscillator takes the control of its associated pins and the GPIO configuration of these pins has no effect When the oscillator is configured in a user externa...

Page 401: ...Reset value Block B 0xFFFF FEBF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MODE15 1 0 MODE14 1 0 MODE13 1 0 MODE12 1 0 MODE11 1 0 MODE10 1 0 MODE9 1 0 MODE8 1 0 rw rw rw rw rw rw rw rw rw rw rw r...

Page 402: ...ode 10 Alternate function mode 11 Analog mode reset state 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4...

Page 403: ...guration Bits 9 8 OSPEED4 1 0 Port Px4 output speed configuration Bits 7 6 OSPEED3 1 0 Port Px3 output speed configuration Bits 5 4 OSPEED2 1 0 Port Px2 output speed configuration Bits 3 2 OSPEED1 1 0...

Page 404: ...configuration Bits 7 6 PUPD3 1 0 Port Px3 pull configuration Bits 5 4 PUPD2 1 0 Port Px2 pull configuration Bits 3 2 PUPD1 1 0 Port Px1 pull configuration Bits 1 0 PUPD0 1 0 Port Px0 pull configurati...

Page 405: ...PIOx_BSRR and GPIOx_BRR registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...

Page 406: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 17 Reserved must be...

Page 407: ...SEL5 3 0 Port Px5 alternate function selection Bits 19 16 AFSEL4 3 0 Port Px4 alternate function selection Bits 15 12 AFSEL3 3 0 Port Px3 alternate function selection Bits 11 8 AFSEL2 3 0 Port Px2 alt...

Page 408: ...ted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6...

Page 409: ...1 0 MODE0 1 0 Port PC0 IO type configuration These bits are written by software to configure the I O mode 00 Input mode 01 General purpose output mode 10 Alternate function mode 11 Analog mode reset...

Page 410: ...rw rw rw rw rw rw Bits 31 30 OSPEED15 1 0 Port PC15 output speed configuration Bits 29 28 OSPEED14 1 0 Port PC14 output speed configuration Bits 27 26 OSPEED13 1 0 Port PC13 output speed configuratio...

Page 411: ...figuration Bits 25 14 Reserved must be kept at reset value Bits 13 12 PUPD6 1 0 Port PC6 pull configuration Bits 11 10 PUPD5 1 0 Port PC5 pull configuration Bits 9 8 PUPD4 1 0 Port PC4 pull configurat...

Page 412: ...s Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OD15 OD14 OD13 Res Res Res Res Res Res OD6 OD5 OD4 OD3 OD2 OD1 OD0 rw rw rw rw rw rw rw rw rw rw Bits 31 16 Rese...

Page 413: ...DR Bit 18 BR2 Port PC2 reset output data bit 2 in GPIOC_ODR Bit 17 BR1 Port PC1 reset output data bit 1 in GPIOC_ODR Bit 16 BR0 Port PC0 reset output data bit 0 in GPIOC_ODR These bits are read clear...

Page 414: ...es Res Res Res Res Res LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw Bits 31 17 Reserved must be kept at reset value Bit 16 LCKK Lock key This bit can be read any time It can only b...

Page 415: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AFSEL3 3 0 AFSEL2 3 0 AFSEL1 3 0 AFSEL0 3 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 28 Reserved must be kept at reset value Bits 27 24 AFSEL6 3 0 P...

Page 416: ...te function I Os 0x0 AF0 selected 0x1 AF1 selected 0x2 AF2 selected 0xE AF14 selected 0xF AF15 selected Bits 19 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R...

Page 417: ...GPIOC_ODR OD0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res MODE...

Page 418: ...es Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res OSPEED3 1 0 Res Res Res Res Res Res rw rw Bits 31 8 Reserved must be kept at reset valu...

Page 419: ...s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res ID3 Res Res Res r Bits 31 4 Reserved must be kept at reset value Bit 3 ID3 Port PH3 input data bit This bit is r...

Page 420: ...nction registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res BR3 Res Res Res rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res...

Page 421: ...e aborts the lock After the first lock sequence on any bit of the port any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset Bits 15 4 Reserved must be kept at reset v...

Page 422: ...MODE3 1 0 MODE2 1 0 MODE1 1 0 MODE0 1 0 Reset value 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x0004 GPIOA_OTYPER Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 423: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0400 GPIOB_MODER MODE15 1 0 MODE14 1 0 MODE13 1 0 MODE12 1 0 MODE11 1 0 MODE10 1 0 MODE9 1 0 MODE8 1 0 MODE7 1 0 MODE6 1 0 MODE5 1 0 MODE4...

Page 424: ...Res Res Res Res Res Res Res Res Res Res Res MODE6 1 0 MODE5 1 0 MODE4 1 0 MODE3 1 0 MODE2 1 0 MODE1 1 0 MODE0 1 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x0804 GPIOC_OTYPER Res Res Res R...

Page 425: ...s Res MODE3 1 0 Res Res Res Res Res Res Reset value 1 1 0x1C04 GPIOH_OTYPER Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res OT3 Res Res...

Page 426: ...28 GPIOH_BRR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res BR3 Res Res Res Reset value 0 Table 74 GPIOH register map and reset values...

Page 427: ...emory remap Address offset 0x000 Reset value 0x0000 000X MEM_MODE 2 0 is the memory mode selected by the BOOT0 pin and BOOT1 option bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res...

Page 428: ...de is enabled on I2C2 pins selected through AF selection bits Bit 20 I2C1_FMP I2C1 Fast mode Plus driving capability activation This bit enables the Fm driving mode on I2C1 pins selected through AF se...

Page 429: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI3 2 0 Res EXTI2 2 0 Res EXTI1 2 0 Res EXTI0 2 0...

Page 430: ...figuration bits These bits are written by software to select the source input for the EXTI0 external interrupt 000 PA0 pin 001 PB0 pin 010 PC0 pin 011 Reserved 100 Reserved 101 Reserved 110 Reserved 1...

Page 431: ...Bits 6 4 EXTI5 2 0 EXTI5 configuration bits These bits are written by software to select the source input for the EXTI5 external interrupt 000 PA5 pin 001 PB5 pin 010 PC5 pin 011 Reserved 100 Reserved...

Page 432: ...are written by software to select the source input for the EXTI10 external interrupt 000 PA10 pin 001 PB10 pin 010 Reserved 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved Bit 7 Rese...

Page 433: ...rw Bits 31 15 Reserved must be kept at reset value Bits 14 12 EXTI15 2 0 EXTI15 configuration bits These bits are written by software to select the source input for the EXTI15 external interrupt 000 P...

Page 434: ...eset value Bits 2 0 EXTI12 2 0 EXTI12 configuration bits These bits are written by software to select the source input for the EXTI12 external interrupt 000 PA12 pin 001 PB12 pin 010 Reserved 011 Rese...

Page 435: ...correct key sequence is written in the SYSCFG_SKR register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5...

Page 436: ...t output to TIM1 16 17 break inputs 0 CPU1 LOCKUP output disconnected from TIM1 16 17 break inputs 1 CPU1 LOCKUP output connected to TIM1 16 17 break inputs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 437: ...yte page 8 write protection Bit 7 P7WP SRAM2 1 Kbyte page 7 write protection Bit 6 P6WP SRAM2 1 Kbyte page 6 write protection Bit 5 P5WP SRAM2 1 Kbyte page 5 write protection Bit 4 P4WP SRAM2 1 Kbyte...

Page 438: ...EXTI14IM EXTI14 interrupt mask to CPU1 Bit 29 EXTI13IM EXTI13 interrupt mask to CPU1 Bit 28 EXTI12IM EXTI12 interrupt mask to CPU1 Bit 27 EXTI11IM EXTI11 interrupt mask to CPU1 Bit 26 EXTI10IM EXTI10...

Page 439: ...at reset value Bit 20 PVDIM PVD interrupt mask to CPU1 0 PVD interrupt forwarded to CPU1 1 PVD interrupt to CPU1 masked Bit 19 Reserved must be kept at reset value Bit 18 PVM3IM PVM3 interrupt mask to...

Page 440: ...to CPU2 Bit 18 EXTI2IM EXTI2 interrupt mask to CPU2 Bit 17 EXTI1IM EXTI1 interrupt mask to CPU2 Bit 16 EXTI0IM EXTI0 interrupt mask to CPU2 Bits 15 12 Reserved must be kept at reset value Bit 13 DACI...

Page 441: ...t mask to CPU2 0 RTCSTAMPTAMPLSECSS interrupt forwarded to CPU2 1 RTCSTAMPTAMPLSECSS interrupt to CPU2 masked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Re...

Page 442: ...set value Bit 6 DMA1CH7IM DMA1CH7 interrupt mask to CPU2 0 DMA1CH7 interrupt forwarded to CPU2 1 DMA1CH7 interrupt to CPU2 masked Bit 5 DMA1CH6IM DMA1CH6 interrupt mask to CPU2 Bit 4 DMA1CH5IM DMA1CH5...

Page 443: ...0 Res EXTI4 2 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x010 SYSCFG_EXTICR3 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res EXTI11 2 0 Res EXTI10 2 0 Res EXTI9 2 0 Res EXTI8 2 0 Reset...

Page 444: ...TI4IM EXTI3IM EXTI2IM EXTI1IM EXTI0IM Res Res DACIM ADCIM COMPIM AESIM Res PKAIM Res FLASHIM RCCIM Res RTCWKUPIM RTCSSRUIM RTCALARMIM RTCSTAMPTAMPLSECSSIM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 445: ...latency and result in more predictable system design Depending on peripherals these interconnections can operate in Run Sleep LPRun LPSleep Stop 0 Stop 1 and Stop 2 modes 12 2 Connection summary Table...

Page 446: ...ing signals The output from master is on signal TIMx_TRGO and TIMx_TRGO2 for TIM1 following a configurable timer event The input to slave is on signals TIMx_ITR0 ITR1 ITR2 ITR3 The input and output si...

Page 447: ...M1 TIM2 and GPIO pin EXTI to ADC DAC Purpose Advanced control timer TIM1 general purpose timer TIM2 and GPIO pin EXTI can be used to generate an ADC DAC trigger event TIMx synchronization is described...

Page 448: ...s on the timer are provided in Section 25 3 4 External trigger input Triggering signals The output from ADC is on signals ADC_AWDx_OUT x 1 2 3 3 watchdogs on ADC and the input to timer on signal TIMx_...

Page 449: ...Table 192 LPTIM1 external trigger connection and Table 193 LPTIM2 external trigger connection Active power modes Run Sleep LPRun LPSleep Stop 0 Stop 1 Stop 2 LPTIM1 only 12 3 8 From timer TIM1 TIM2 t...

Page 450: ...imers TIM1 TIM2 TIM16 TIM17 Purpose Comparators COMP1 COMP2 output values can be connected to timers TIM1 TIM2 TIM16 TIM17 input captures or TIMx_ETR signals Comparators COMP1 COMP2 output values can...

Page 451: ...ls TIMx_OC1 are used to generate the waveform of infrared signal output The functionality is described in Section 29 Infrared interface IRTIM Active power modes Run Sleep LPRun LPSleep 12 3 13 From ti...

Page 452: ...Low power timer LPTIM3 can be used to generate a sub GHz radio SPI NSS event Triggering signals The output from low power timer is on signal LPTIM3_OUT event The connection between timers and sub GHz...

Page 453: ...h a software trigger in memory to memory transfers This configuration is done by software Priority between the requests is programmable by software 4 levels per channel very high high medium low and b...

Page 454: ...ion parameters shown in Table 77 13 3 2 DMA request mapping The DMA controller is connected to DMA requests from the AHB APB peripherals through the DMAMUX peripheral For the mapping of the different...

Page 455: ...533V1 DMA2 DMA1 AHB master interface Arbiter Ch 1 AHB slave interface Ch 2 Ch 7 32 bit AHB bus 32 bit AHB bus dma1_req 1 7 dma1_ack 1 7 Interrupt interface dma1_it 1 7 dma1_secm 1 7 dma1_priv 1 7 DMAM...

Page 456: ...s The secure software configures the DMA controller at channel level in order to perform a block transfer composed of a sequence of AHB secure or non secure privileged or unprivileged bus transfers A...

Page 457: ...t decrementing of the programmed DMA_CNDTRx register This register contains the remaining number of data items to transfer number of AHB read followed by write transfers This sequence is repeated unti...

Page 458: ...ers these registers keep the initially programmed value The current transfer addresses in the current internal peripheral memory address register are not accessible by software If the channel x is con...

Page 459: ...A_CM0ARx and DMA_CM1ARx a non secure read access to a dedicated register of this channel x except the DMA_CxCR register DMA_CNDTRx DMA_CPARx DMA_CM0ARx and DMA_CM1ARx If the channel x is in non secure...

Page 460: ...after the channel is enabled in memory to memory mode 3 Set the memory address in the DMA_CMARx register The data is written to read from the memory after the peripheral event or after the channel is...

Page 461: ...o pending hardware DMA request from this peripheral The software must operate separated write accesses to the same DMA_CCRx register First disable the channel Second reconfigure the channel for a next...

Page 462: ...e of the DIR bit of the DMA_CCRx register sets the direction of the transfer and consequently it identifies the source and the destination regardless the source destination type peripheral or memory D...

Page 463: ...B3B2 15 0 0x2 then write B2 7 0 0x1 3 read B5B4 15 0 0x4 then write B4 7 0 0x2 4 read B7B6 15 0 0x6 then write B6 7 0 0x3 0x0 B0 0x1 B2 0x2 B4 0x3 B6 16 16 4 0x0 B1B0 0x2 B3B2 0x4 B5B4 0x6 B7B6 1 rea...

Page 464: ...B0B0B0 to the 0x0 address An AHB half word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses is converted to an APB word write transfer of 0xB1B0B1B0 to the 0x0 address 13 4 7 DMA error management...

Page 465: ...tware can read the full interrupt status An unprivileged software is restricted to read the status of unprivileged channel s other privileged bit fields returning zero Every status flag bit is set by...

Page 466: ...er HT flag for channel 6 0 no HT event 1 a HT event occurred Bit 21 TCIF6 transfer complete TC flag for channel 6 0 no TC event 1 a TC event occurred Bit 20 GIF6 global interrupt flag for channel 6 0...

Page 467: ...no TE HT or TC event 1 a TE HT or TC event occurred Bit 7 TEIF2 transfer error TE flag for channel 2 0 no TE event 1 a TE event occurred Bit 6 HTIF2 half transfer HT flag for channel 2 0 no HT event 1...

Page 468: ...R register Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register causes the DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx HTIFx TCIFx in...

Page 469: ...t 16 CGIF5 global interrupt flag clear for channel 5 Bit 15 CTEIF4 transfer error flag clear for channel 4 Bit 14 CHTIF4 half transfer flag clear for channel 4 Bit 13 CTCIF4 transfer complete flag cle...

Page 470: ...ept at reset value Bit 20 PRIV privileged mode This bit can only be set and cleared by a privileged software 0 disabled 1 enabled This bit must not be written when the channel is enabled EN 1 It is re...

Page 471: ...e source This bit must not be written when the channel is enabled EN 1 It is read only when the channel is enabled EN 1 Bit 17 SECM secure mode This bit can only be set or cleared by a secure software...

Page 472: ...y destination if DIR 1 and the memory source if DIR 0 In peripheral to peripheral mode this field identifies the peripheral destination if DIR 1 and the peripheral source if DIR 0 00 8 bits 01 16 bits...

Page 473: ...ction This bit must be set only in memory to peripheral and peripheral to memory modes 0 read from peripheral Source attributes are defined by PSIZE and PINC plus the DMA_CPARx register This is still...

Page 474: ...led 1 enabled Note This bit is set and cleared by software privileged secure software if the channel is in privileged secure mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Re...

Page 475: ...PA 31 0 is ignored Access is automatically aligned to a half word address When PSIZE 10 32 bits bits 1 and 0 of PA 31 0 are ignored Access is automatically aligned to a word address In memory to memor...

Page 476: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x004 DMA_IFCR Res Res Res Res CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF...

Page 477: ...Res Res Res PRIV DSEC SSEC SECM Res Res MEM2MEM PL 1 0 MSIZE 1 0 PSIZE 1 0 MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x05C DMA_CNDTR5 Res Res Res Res Res R...

Page 478: ...Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x088 DMA_CPAR7 PA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08C DMA_CMAR7 MA 31 0 Reset value 0 0 0 0 0 0 0 0...

Page 479: ...ntrollers of the product The routing function is ensured by a programmable multi channel DMA request line multiplexer Each channel selects a unique DMA request line unconditionally or synchronously wi...

Page 480: ...y at a channel level Security aware AHB slave port protecting any secure resource register register field from a non secure software access with configurable interrupt event Two secure and non secure...

Page 481: ...equest MUX input Resource 1 dmamux_req_gen0 22 LPUART1_TX 43 Reserved 2 dmamux_req_gen1 23 TIM1_CH1 44 Reserved 3 dmamux_req_gen2 24 TIM1_CH2 45 Reserved 4 dmamux_req_gen3 25 TIM1_CH3 46 Reserved 5 AD...

Page 482: ...I LINE11 27 Reserved 12 EXTI LINE12 28 Reserved 13 EXTI LINE13 29 Reserved 14 EXTI LINE14 30 Reserved 15 EXTI LINE15 31 Reserved Table 85 DMAMUX1 assignment of synchronization inputs to resources Sync...

Page 483: ..._trgx Internal or external signals to synchronization inputs dmamux_syncx MS51703V2 DMAMUX_C0CR Channel 0 0 Channel select Ctrl Channel 1 Channel m DMAMUX Request multiplexer p n 3 n 2 n p 2 1 0 n 2 1...

Page 484: ...ctivate the DMA channel y by setting the EN bit in the DMA y channel register 1 Set and configure completely the DMA channel y except enabling the channel y 2 Set and configure completely the related...

Page 485: ...has no impact Additionally an illegal access signal is generated as a pulse to the secure interrupt controller when a non secure software attempts to access a secure DMAMUX register DMAMUX_CxCR if the...

Page 486: ...dge on the selected input synchronization signal via the SPOL 1 0 field of the DMAMUX_CxCR register Additionally there is a programmable DMA request counter internally to the DMAMUX request multiplexe...

Page 487: ...x dmamux_req_outx dmamux_syncx Selected dmamux_reqx Synchronization event Input DMA request line connected to output 3 2 1 0 4 4 DMA request counter underrun DMA request counter auto reload to NBREQ I...

Page 488: ...bit SOIE is set in the DMAMUX_CxCR register 14 4 7 DMAMUX request generator The DMAMUX request generator produces DMA requests following trigger events on its DMA request trigger inputs The DMAMUX req...

Page 489: ...is no served request received from the DMA The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the DMAMUX_RGCFR register Setting the DMAMUX request trigger overrun f...

Page 490: ...ation event overrun on a secure channel x of the DMAMUX request line multiplexer SOFx CSOFx SOIE Trigger event overrun on a secure channel x of the DMAMUX request generator OFx COFx OIE Table 87 DMAMU...

Page 491: ...onnected of the connected DMA controller channel y This assumes that the DMAMUX x channel output is connected to the y channel of the DMA refer to the DMAMUX mapping implementation section 31 30 29 28...

Page 492: ...d to the y channel of the DMA refer to the DMAMXUX mapping implementation section This register must be written at bit level by an unprivileged or privileged write according to the privileged mode of...

Page 493: ...MUX request generator x channel output is selected by the y channel of the DMAMUX request line channel refer to DMAMUX_CyCR DMAREQ_ID 7 0 and to the DMAMXUX mapping implementation section 31 30 29 28...

Page 494: ...igger input 00 No event i e no trigger detection nor generation 01 Rising edge 10 Falling edge 11 Rising and falling edges Bit 16 GE DMA request generator channel x enable 0 DMA request generator chan...

Page 495: ...e written at bit level by an unprivileged or privileged write according to the privileged mode of the considered DMAMUX request line multiplexer channel y it is assigned to and considering that the DM...

Page 496: ...0 0 0 0x01C DMAMUX_C7CR Res Res Res SYNC_ID 4 0 NBREQ 4 0 SPOL 1 0 SE Res Res Res Res Res Res EGE SOIE Res DMAREQ_ID 6 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x020 DMAMUX_C8CR Res R...

Page 497: ...0 0 0 0 0 0 0x10C DMAMUX_RG3CR Res Res Res Res Res Res Res Res GNBREQ 4 0 GPOL 1 0 GE Res Res Res Res Res Res Res OIE Res Res Res SIG_ID 4 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x110 0x13C Reserv...

Page 498: ...upt handling Power management control The NVICs and the processor cores interfaces are closely coupled resulting in low latency interrupt processing and efficient processing of late arriving interrupt...

Page 499: ...al interrupt AIECinterrupt interrupt Table 89 CPU1 vector table Position Priority Type of priority Acronym Description 1 2 Address Reserved 0x0000 0000 3 Fixed Reset Reset 0x0000 0004 2 Fixed NMI Non...

Page 500: ...068 11 18 Settable DMA1_CH1 DMA1 channel 1 non secure interrupt 0x0000 006C 12 19 Settable DMA1_CH2 DMA1 channel 2 non secure interrupt 0x0000 0070 13 20 Settable DMA1_CH3 DMA1 channel 3 non secure in...

Page 501: ...RTC alarms A and B interrupt 0x0000 00E8 43 50 Settable LPTIM3 LP timer 3 global interrupt 0x0000 00EC 44 51 Settable Reserved Reserved 0x0000 00F0 45 52 Settable IPCC_C1_RX_IT IPCC CPU1 RX occupied i...

Page 502: ...x0000 0034 2 1 Settable PendSV Pendable request for system service 0x0000 0038 1 2 Settable Systick System tick timer 0x0000 003C 0 3 Settable TZIC_ILA Security Interrupt controller illegal access int...

Page 503: ...1 trigger and communication Timer 1 capture compare interrupt 0x0000 0078 15 18 Settable TIM2 Timer 2 global interrupt 0x0000 007C 16 19 Settable TIM16 Timer 16 global interrupt 0x0000 0080 17 20 Sett...

Page 504: ...0B4 30 33 Settable SUBGHZSPI Sub GHz radio SPI global interrupt 0x0000 00B8 31 34 Settable Radio IRQ Busy Radio IRQs RFBUSY interrupt through EXTI 45 0x0000 00BC 1 C2IMRx n refer to the pre mask bit n...

Page 505: ...flag in the EXTI and generate an interrupt to the CPU from the EXTI The asynchronous event inputs are classified in the following two groups Configurable events signals from I Os or peripherals able...

Page 506: ...B bus clock and EXTI system clock Configurable event y I Asynchronous wakeup events from peripherals which do not have an associated interrupt and flag in the peripheral Direct event x I Synchronous a...

Page 507: ...system and CPU sub system bus clocks 16 3 1 EXTI wakeup interrupt list The wakeup sources are listed in Table 93 Wakeup interrupts Some wakeup sources are able to generate an event to the CPU see Even...

Page 508: ...PU2 27 USART2 USART2 wakeup Direct No CPU1 and CPU2 28 LPUART1 LPUART1 wakeup Direct No CPU1 and CPU2 29 LPTIM1 wakeup LPtimer 1 wakeup Direct No CPU1 and CPU2 30 LPTIM2 wakeup LPtimer 2 wakeup Direct...

Page 509: ...XTI event mask register EXTI_CnEMR1 EXTI event mask register EXTI_CnEMR2 45 Radio Busy RFBUSY wakeup Configurable No CPU1 and CPU2 46 CDBGPWRUPREQ Debug power up request wakeup Direct No CPU1 and CPU2...

Page 510: ...pt or CPU event is enabled the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator This guarantees that the EXTI hclk clock is woken up before the...

Page 511: ...s unmasked the corresponding pending bit in EXTI_PR is set the CPU sub system wakes up and the CPU MSv60762V1 Peripheral interface EVG EXTI Direct event input x Asynchronous rising edge detect circuit...

Page 512: ...vent register EXTI_SWIER This allows the generation of a rising edge on the event The edge event pending bit must be set in EXTI_PR irrespective of the setting in EXTI_RTSR 16 6 EXTI registers The EXT...

Page 513: ...input 14 Bit 13 RT13 rising trigger event configuration bit of configurable event input 13 Bit 12 RT12 rising trigger event configuration bit of configurable event input 12 Bit 11 RT11 rising trigger...

Page 514: ...3 FT13 falling trigger event configuration bit of configurable event input 13 Bit 12 FT12 falling trigger event configuration bit of configurable event input 12 Bit 11 FT11 falling trigger event confi...

Page 515: ...on line 15 Bit 14 SWI14 Software interrupt on line 14 Bit 13 SWI13 Software interrupt on line 13 Bit 12 SWI12 Software interrupt on line 12 Bit 11 SWI11 Software interrupt on line 11 Bit 10 SWI10 Soft...

Page 516: ...IF15 pending bit on event input 15 Bit 14 PIF14 pending bit on event input 14 Bit 13 PIF13 pending bit on event input 13 Bit 12 PIF12 pending bit on event input 12 Bit 11 PIF11 pending bit on event in...

Page 517: ...ent configuration bit of configurable event input 34 Bits 1 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res R...

Page 518: ...be kept at reset value Bit 13 SWI45 software interrupt on event 45 A software interrupt is generated independently from the setting in EXTI_RTSR and EXTI_FTSR This bit always returns 0 when read 0 Wr...

Page 519: ...ending bit on event input 41 Bit 8 PIF40 pending bit on event input 40 Bits 7 3 Reserved must be kept at reset value Bit 2 PIF34 pending bit on event input 34 Bits 1 0 Reserved must be kept at reset v...

Page 520: ...with event generation mask on event input 13 Bit 12 EM12 wakeup with event generation mask on event input 12 Bit 11 EM11 wakeup with event generation mask on event input 11 Bit 10 EM10 wakeup with eve...

Page 521: ...th interrupt mask on event input 40 Bit 7 IM39 wakeup with interrupt mask on event input 39 Bit 6 IM38 wakeup with interrupt mask on event input 38 Bit 5 IM37 wakeup with interrupt mask on event input...

Page 522: ...0 0 0 0x028 EXTI_SWIER2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res SWI45 Res Res Res SWI41 SWI40 Res Res Res Res Res SWI34 Res Res Reset value 0 0 0 0 0x02C EXTI_PR2 Res R...

Page 523: ...IM45 IM44 IM46 IM42 IM41 IM40 IM39 IM38 IM37 IM36 Res IM34 Res Res Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x0D4 EXTI_C2EMR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 524: ...a reference signature generated at link time and stored at a given memory location 17 2 CRC main features Uses CRC 32 Ethernet polynomial 0x4C11DB7 X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X 1 A...

Page 525: ...data word or byte by byte depending on the format of the data being written The CRC_DR register can be accessed by word right aligned half word and right aligned byte For the other registers only 32...

Page 526: ...RC_CR register the default value is 0xFFFFFFFF The initial CRC value can be programmed with the CRC_INIT register The CRC_DR register is automatically initialized upon CRC_INIT register write access T...

Page 527: ...1 0 DR 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 DR 31 0 Data register bits This register is used to write new data to the CRC calculator It holds the previous CRC calculation res...

Page 528: ...of the output data 0 Bit order not affected 1 Bit reversed output format Bits 6 5 REV_IN 1 0 Reverse input data These bits control the reversal of the bit order of the input data 00 Bit order not affe...

Page 529: ...w rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 CRC_INIT 31 0 Programmable initial CRC value This register is used to write the CRC initial value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POL 31...

Page 530: ...ue 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x04 CRC_IDR IDR 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08 CRC_CR Res Res Res Res Res Res...

Page 531: ...channels can be performed in single continuous scan or discontinuous mode The result of the ADC is stored in a left aligned or right aligned 16 bit data register The analog watchdog feature allows the...

Page 532: ...ower consumption of the ADC Analog input channels 12 external analog inputs 1 channel for internal temperature sensor VTS 1 channel for internal reference voltage VREFINT 1 channel for monitoring exte...

Page 533: ...rupt IRQ DMA request AHB DMAEN DMACFG OVRMODE overrun mode ALIGN left right RES 1 0 12 10 8 bits AWDxEN AWDxSGL AWDCHx 4 0 LTx 11 0 HTx 11 0 ADC_AWDx_OUT To analog watchdog ADSTART SW trigger AUTDLY A...

Page 534: ...ge regulator is disabled the internal analog calibration is kept Analog reference from the power control unit The internal ADC voltage regulator internally uses an analog reference delivered by the po...

Page 535: ...regulator is enabled ADVREGEN 1 and tADCVREG_SETUP has elapsed and the ADC is disabled when ADEN 0 ADCAL bit stays at 1 during all the calibration sequence It is then cleared by hardware as soon the c...

Page 536: ..._CALFACT with the saved calibration factor 3 The calibration factor is used as soon as a new conversion is launched Figure 60 Calibration factor forcing 18 3 4 ADC on off control ADEN ADDIS ADRDY At p...

Page 537: ...in the ADC_ISR register ADRDY is set after the ADC startup time This can be handled by interrupt if the interrupt is enabled by setting the ADRDYIE bit in the ADC_IER register Follow this procedure to...

Page 538: ...ed from the APB clock of the ADC bus interface divided by a programmable factor 1 2 or 4 according to bits CKMODE 1 0 To select this scheme bits CKMODE 1 0 of the ADC_CFGR2 register must be different...

Page 539: ...vide the clock Table 103 Latency between trigger and start of conversion 1 1 Refer to the device datasheet for the maximum ADC_CLK frequency ADC clock source CKMODE 1 0 Latency between the trigger eve...

Page 540: ...ribed in Figure 63 Figure 63 ADC connectivity MSv61354V1 SAR ADC ADC ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 VIN 1 VIN 2 STM32WLxx VIN 0 VIN 3 VIN 4 VIN 5 VIN 6 VIN 8 VIN 9 VIN 7 VIN 10 VIN 11...

Page 541: ...e To recover correct operation in this case the ADC must be disabled clear ADEN 0 and all the bits in the ADC_CR register 18 3 8 Channel selection CHSEL SCANDIR CHSELRMOD There are up to 18 multiplexe...

Page 542: ...The temperature sensor is connected to channel ADC VIN 12 The internal voltage reference VREFINT is connected to channel ADC VIN 13 VBAT channel is connected to ADC VIN 14 channel The internal dac_out...

Page 543: ...Continuous conversion mode CONT 1 In continuous conversion mode when a software or hardware trigger event occurs the ADC performs a sequence of conversions converting all the channels once and then a...

Page 544: ...on EOC 1 In all cases CONT x EXTEN XX After execution of the ADSTP procedure invoked by software see Section 18 3 14 Stopping an ongoing conversion ADSTP on page 546 Note In continuous mode CONT 1 the...

Page 545: ...y refer to datasheet for more details tCONV tSMPL tSAR 1 5 min 12 5 12bit x tADC_CLK tCONV tSMPL tSAR 42 9 ns min 357 1 ns 12bit 0 400 s min for fADC_CLK 35 MHz Analog channel Internal S H t t depends...

Page 546: ...ion can be triggered either by software or by an external event for example timer capture If the EXTEN 1 0 control bits are not equal to 0b00 then external events are able to trigger a conversion with...

Page 547: ...er channel 10 is converted and both EOC and EOS events are generated 5th trigger channel 0 is converted an EOC event is generated 6th trigger channel 3 is converted and an EOC event is generated DISCE...

Page 548: ...alog multiplexer can be accessed in hidden time during the conversion phase so that the multiplexer is positioned when the next sampling starts Note As there is only a very short time left between the...

Page 549: ...x20601 WAIT 0 AUTOFF 0 Figure 68 Continuous conversion of a sequence software trigger 1 EXTEN 00 CONT 1 2 CHSEL 0x20601 WAIT 0 AUTOFF 0 MSv30338V3 RDY EOC SCANDIR CH9 CH17 CH9 ADC_DR D0 D10 D17 D10 D9...

Page 550: ...ersions of a sequence hardware trigger 1 EXTSEL TRGx EXTEN 10 falling edge CONT 1 2 CHSEL 0xF SCANDIR 0 WAIT 0 AUTOFF 0 MSv30340V2 CH1 CH1 CH3 CH0 CH2 D0 D1 D2 D1 D2 D3 D3 CH2 EOC ADC_DR ADC state 2 A...

Page 551: ...rigger generates an internal rearm command 18 5 Data management 18 5 1 Data register and data alignment ADC_DR ALIGN At the end of each conversion when an EOC event occurs the result of the converted...

Page 552: ...erves the data register from being overwritten the old data is maintained and the new conversion is discarded If OVR remains at 1 further conversions can be performed but the resulting data is discard...

Page 553: ...s generated after the conversion of each channel This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software Note The DMAEN bit in the...

Page 554: ...en if the DMA has reached the last DMA transfer This allows the DMA to be configured in circular mode to handle a continuous analog input data stream 18 6 Low power features 18 6 1 Wait mode conversio...

Page 555: ...e power consumption of applications which need relatively few conversions or when conversion requests are timed far enough apart for example with a low frequency hardware trigger to justify the extra...

Page 556: ...1 AUTOFF 1 1 EXTSEL TRGx EXTEN 01 rising edge CONT x ADSTART 1 CHSEL 0xF SCANDIR 0 WAIT 1 AUTOFF 1 MSv30345V2 TRGx EOC EOS ADC_DR Read access ADC state ADC_DR by H W by S W triggered D1 D3 D2 D4 RDY C...

Page 557: ...ith a resolution of less than 12 bit according to bits DRES 1 0 the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12 bit raw con...

Page 558: ...dware signal ADC_AWDx_OUT x being the watchdog number that is directly connected to the ETR input external trigger of some on chip timers refer to the timers section for details on how to select the A...

Page 559: ...generation AWDx flag not cleared by software MSv45362V1 EOC FLAG ADC STATE RDY AWDx FLAG Conversion1 outside ADC_AWDx_OUT inside Cleared by SW Conversion2 Conversion3 Conversion4 Conversion5 Conversi...

Page 560: ...h end of conversion If the current ADC data are out of the new threshold interval this does not generated any interrupt or an ADC_AWDx_OUT signal The Interrupt and the ADC_AWDx_OUT generation only occ...

Page 561: ...it shift up to 8 bits It is configured through the OVSS 3 0 bits in the ADC_CFGR2 register The summation unit can yield a result up to 20 bits 256 x 12 bit which is first shifted right The upper bits...

Page 562: ...nversions total 0 3 7 11 15 19 Raw 20 bit data B F 15 B 7 3 7 D 1 D MS31929V1 Final result after 5 bits shift and rounding to nearest Table 108 Maximum output results vs N and M Grayed values indicate...

Page 563: ...n using the full 12 bits values HTx 11 0 and LTx 11 0 the comparison is performed on the most significant 12 bits of the 16 bits oversampled results ADC_DR 15 4 Note Care must be taken when using high...

Page 564: ...he conversion of ADC VIN 12 temperature sensor and the VREFEN bit must be set to enable the conversion of ADC VIN 13 VREFINT The temperature sensor output voltage changes linearly with temperature The...

Page 565: ...ing formula Where TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP refer to the datasheet for TS_CAL2 value TS_CAL1 is the temperature sensor calibration value acquired at...

Page 566: ...you can use the following formula to get this absolute value For applications where VREF value is not known you must use the internal voltage reference and VREF can be replaced by the expression prov...

Page 567: ...any of the following events End Of Calibration EOCAL flag ADC power up when the ADC is ready ADRDY flag End of any conversion EOC flag End of a sequence of conversions EOS flag When an analog watchdog...

Page 568: ...watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set AWD3 AWD3IE Channel Configuration Ready CCRDY CCRDYIE End of sampling phase EOSMP EOSMPIE Overrun OVR OVRIE Table 109 ADC...

Page 569: ...l the CCRDY flag rises before configuring again or starting conversions otherwise the new configuration or the START bit is ignored Once the flag is asserted if the software needs to configure again t...

Page 570: ...sequence not complete or the flag event was already acknowledged and cleared by software 1 Conversion sequence complete Bit 2 EOC End of conversion flag This bit is set by hardware at the end of each...

Page 571: ...rupt disabled 1 End of calibration interrupt enabled Note The software is allowed to write this bit only when ADSTART bit is cleared to 0 this ensures that no conversion is ongoing Bit 10 Reserved mus...

Page 572: ...bit is set and cleared by software to enable disable the end of conversion interrupt 0 EOC interrupt disabled 1 EOC interrupt enabled An interrupt is generated when the EOC bit is set Note The softwar...

Page 573: ...erved must be kept at reset value Bit 28 ADVREGEN ADC Voltage Regulator Enable This bit is set by software to enable the ADC internal voltage regulator The voltage regulator output is available after...

Page 574: ...ADDIS 0 ADC is enabled and there is no pending request to disable the ADC After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW it is mandatory to wait until CCRDY flag is asserted be...

Page 575: ...24 Reserved must be kept at reset value Bit 23 AWD1EN Analog watchdog enable This bit is set and cleared by software 0 Analog watchdog 1 disabled 1 Analog watchdog 1 enabled Note The software is allo...

Page 576: ...f it is set conversion takes place continuously until it is cleared 0 Single conversion mode 1 Continuous conversion mode Note It is not possible to have both discontinuous mode and continuous mode en...

Page 577: ...es that no conversion is ongoing Bit 5 ALIGN Data alignment This bit is set and cleared by software to select right or left alignment Refer to Figure 71 Data alignment and resolution oversampling disa...

Page 578: ...onfiguration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN 1 0 DMA one shot mode selected 1 DMA circular mode selected For more...

Page 579: ...configured inside the RCC must be bypassed and the system clock must by 50 duty cycle In all synchronous clock modes there is no jitter in the delay from a timer trigger to the start of a conversion...

Page 580: ...001 4x 010 8x 011 16x 100 32x 101 64x 110 128x 111 256x Note The software is allowed to write this bit only when ADSTART 0 which ensures that no conversion is ongoing Bit 1 Reserved must be kept at re...

Page 581: ...DC clock cycles 010 7 5 ADC clock cycles 011 12 5 ADC clock cycles 100 19 5 ADC clock cycles 101 39 5 ADC clock cycles 110 79 5 ADC clock cycles 111 160 5 ADC clock cycles Note The software is allowed...

Page 582: ...g window watchdog AWD1EN AWD1SGL AWD1CH ADC_AWDxCR ADC_AWDxTR on page 557 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res HT2 11 0 rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10...

Page 583: ...CHSEL 12 CHSEL 11 CHSEL 10 CHSEL 9 CHSEL 8 CHSEL 7 CHSEL 6 CHSEL 5 CHSEL 4 CHSEL 3 CHSEL 2 CHSEL 1 CHSEL 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 18 Reserved must be kept at reset va...

Page 584: ...annels these bits are ignored 0000 CH0 0001 CH1 1100 CH12 1101 CH13 1110 CH14 1111 No channel selected End of sequence Note The software is allowed to write this bit only when ADSTART 0 which ensures...

Page 585: ...channel number 0 14 assigned to the 8th conversion of the sequence 0b1111 indicates end of the sequence When 0b1111 end of sequence is programmed to the lower sequence channels these bits are ignored...

Page 586: ...CH ADC_AWDxCR ADC_AWDxTR on page 557 Bits 15 12 Reserved must be kept at reset value Bits 11 0 LT3 11 0 Analog watchdog 3lower threshold These bits are written by software to define the lower threshol...

Page 587: ...elected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers Refer to SQ8 3 0 for a definition of channel selection The software is allowed to write this bit only when ADSTART 0 wh...

Page 588: ...ware Once a calibration is complete they are updated by hardware with the calibration factors Software can write these bits with a new calibration factor If the new calibration factor is different fro...

Page 589: ...it only when ADSTART 0 which ensures that no conversion is ongoing Bits 21 18 PRESC 3 0 ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC 0000 input ADC clock n...

Page 590: ...es Res HT1 11 0 Res Res Res Res LT1 11 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0x24 ADC_AWD2TR Res Res Res Res HT2 11 0 Res Res Res Res LT2 11 0 Reset value 1 1 1 1 1 1 1 1 1 1 1...

Page 591: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Reserved 0xB4 ADC_CALFACT Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CALFACT 6 0 Reset value 0 0 0...

Page 592: ...he DAC output buffer can be optionally enabled to obtain a high drive output current An individual calibration can be applied on each DAC output channel The DAC output channels support a low power mod...

Page 593: ...ation and the Sample and hold mode Table 111 DAC features DAC features DAC Dual channel Output buffer X I O connection DAC_OUT1 to PA10 Maximum sampling time 1 Msps Autonomous mode MSv61355V5 V REF da...

Page 594: ...e Sample and hold block and its associated registers can run in Stop mode using the LSI clock source dac_hold_ck Table 112 DAC input output pins Pin name Signal type Remarks VREF Input analog referenc...

Page 595: ...11 0 bits 12 bit right alignment the software has to load data into the DAC_DHR12R1 11 0 bits stored into the DHR1 11 0 bits Depending on the loaded DAC_DHRyyyx register the data written by the user i...

Page 596: ...for conversion with trigger disabled TEN 0 19 4 6 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and VREF The analog output voltage on the DAC cha...

Page 597: ...est is not queued so that if a second external trigger arrives before the acknowledgment for the first external trigger is received first request then no new request is issued and the DMA channel1 und...

Page 598: ...value is then transferred into the DAC_DOR1 register If LFSR is 0x0000 a 1 is injected into it antilock up mechanism It is possible to reset LFSR wave generation by resetting the WAVE1 1 0 bits Figur...

Page 599: ...incremented as long as it is less than the maximum amplitude defined by the MAMP1 3 0 bits Once the configured amplitude is reached the counter is decremented down to 0 then incremented again and so o...

Page 600: ...output is tri stated therefore reducing the overall power consumption A stabilization period which value depends on the buffer state is required before each new conversion In this mode the DAC core a...

Page 601: ...for product data CSH 100 nF VDD 3 0 V Sampling phase tSAMP 7 s 10 2000 100 10 9 2 007 ms where RBON 2 k Refresh phase tREFRESH 7 s 2000 100 10 9 ln 2 10 606 1 s where NLSB 10 10 LSB drop during the ho...

Page 602: ...DAC is connected to on chip peripherals When MODE1 2 0 bits are equal to 111 an internal capacitor CLint holds the voltage output of the DAC core and then drive it to on chip peripherals All Sample an...

Page 603: ...ut signal to 0 or 1 depending on the comparison result CAL_FLAG1 bit Two calibration techniques are provided Factory trimming default setting The DAC buffer offset is factory trimmed The default value...

Page 604: ...DAC_CCR register Note A tTRIM delay must be respected between the write to the OTRIM1 4 0 bits and the read of the CAL_FLAG1 bit in DAC_SR register in order to get a correct value This parameter is s...

Page 605: ...SEL1 3 0 bits 3 Configure the DAC channel WAVE1 1 0 bits as 1x and the same maximum amplitude value in the MAMP1 3 0 bits 4 Load the DAC channel data into the desired DHR register DAC_DHR12RD DAC_DHR1...

Page 606: ...iting Stop 2 The DAC must be disabled before entering Stop 2 Standby The DAC peripheral is powered down and must be reinitialized after exiting Standby or Shutdown mode Shutdown Table 117 Effect of lo...

Page 607: ...kept at reset value Bits 30 16 Reserved must be kept at reset value Bit 15 Reserved must be kept at reset value Bit 14 CEN1 DAC channel1 calibration enable This bit is set and cleared by software to...

Page 608: ...and cleared by software 00 wave generation disabled 01 Noise wave generation enabled 1x Triangle wave generation enabled Only used if bit TEN1 1 DAC channel1 trigger enabled Bits 5 2 TSEL1 3 0 DAC cha...

Page 609: ...value Bit 1 Reserved must be kept at reset value Bit 0 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode 0 No trigger 1 Trigger Note This b...

Page 610: ...Res rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 4 DACC1DHR 11 0 DAC channel1 12 bit left aligned data These bits are written by software They specify 12...

Page 611: ...27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC1DHR 11 0 Res Res Res Res rw rw rw rw rw rw rw rw rw rw r...

Page 612: ...MAU DR1 Res Res Res Res Res Res Res Res Res Res Res Res Res r r rc_w1 Bits 31 29 Reserved must be kept at reset value Bit 28 Reserved must be kept at reset value Bit 27 Reserved must be kept at reset...

Page 613: ...reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Re...

Page 614: ...ected to external pin with Buffer disabled 011 DAC channel1 is connected to on chip peripherals with Buffer disabled DAC channel1 in sample hold mode 100 DAC channel1 is connected to external pin with...

Page 615: ...s Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res THOLD1 9 0 rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at res...

Page 616: ...Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DACC1DHR 11 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x24 DAC_ DHR12LD Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DAC...

Page 617: ...addresses 0x4C DAC_ SHRR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TREFRESH1 7 0 Reset value 0 0 0 0 0 0 0 1 Table 119 DAC register map and reset...

Page 618: ...rnal voltage reference can be configured in four different modes depending on ENVR and HIZ bits configuration These modes are provided in the table below After enabling the VREFBUF by setting ENVR bit...

Page 619: ...eached the requested level Bit 2 VRS Voltage reference scale This bit selects the value generated by the voltage reference buffer 0 Voltage reference set to VREF_OUT1 around 2 048 V 1 Voltage referenc...

Page 620: ...ng code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test Writing into these bits allows the tuning of the internal ref...

Page 621: ...d with a PWM output from a timer 21 2 COMP main features Configurable plus and minus inputs used for flexible voltage Multiplexed I O pins DAC channel1 Internal reference voltage and three sub multipl...

Page 622: ...internally redirected to a variety of timer inputs for the following purposes emergency shut down of PWM signals using BKIN and BKIN2 inputs cycle by cycle current control using OCREF_CLR inputs inpu...

Page 623: ...t affected PB3 110 Not affected PA10 111 00 PA11 111 01 PA15 111 10 Reserved 111 11 Table 124 COMP2 input plus assignment COMP2_INP COMP2_INPSEL PB4 00 PB1 01 PA15 10 Table 125 COMP2 input minus assig...

Page 624: ...example at program counter corruption For this purpose the comparator configuration registers can be write protected read only Once the programming is completed the COMPx LOCK bit can be set to 1 This...

Page 625: ...r instance when exiting from low power mode to be able to force the hysteresis value using external components Figure 96 Comparator hysteresis MSv37667V1 COMPy_INM I Os COMPy_INP I Os Internal sources...

Page 626: ...p_out from spurious pulses due to current spikes as depicted in the figure below Figure 97 Comparator output blanking 21 3 8 COMP power and speed modes COMP1 and COMP2 power consumption versus propaga...

Page 627: ...hannel mapped to the corresponding EXTI lines 3 Enable the COMPx Table 126 Comparator behavior in the low power modes Mode Description Sleep No effect on the comparators Comparator interrupts cause th...

Page 628: ...SEL 1 0 COMP1 input minus extended selection These bits are set and cleared by software They select which extended GPIO input is connected to the input minus of COMP1 if INMSEL 2 0 111 00 PA10 01 PA11...

Page 629: ...output value inverted Bits 14 9 Reserved must be kept at reset value Bits 8 7 INPSEL 1 0 COMP1 input plus selection These bits are set and cleared by software 00 PB4 01 PB2 10 reserved 11 reserved Bi...

Page 630: ...0 COMP2 input minus extended selection These bits are set and cleared by software They select which extended GPIO input is connected to the input minus of COMP2 if INMSEL 2 0 111 00 PB2 01 PA10 10 PA1...

Page 631: ...0 COMP2 output value not inverted 1 COMP2 output value inverted Bits 14 10 Reserved must be kept at reset value Bit 9 WINMODE window mode selection This bit is set and cleared by software It selects...

Page 632: ...leared by software It switches COMP2 on 0 COMP2 switched off 1 COMP2 switched on Table 128 COMP register map and reset values Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 633: ...8 22 2 RNG main features The RNG delivers 32 bit true random numbers produced by an analog entropy source conditioned by a NIST SP800 90B approved conditioning stage It can be used as entropy source t...

Page 634: ...status RNG_DR data Analog noise source 1 Banked Registers Sampling x N XOR DIV Analog noise source Fault detection Clock checker Health tests 1 bit CONDRST Alarms Analog noise source 2 Analog noise s...

Page 635: ...the bitstring output by the entropy source This noise source provides 1 bit samples It is composed of Multiple analog noise sources x6 each based on three XORed free running ring oscillator outputs I...

Page 636: ...le are described in Section 22 5 RNG processing time Output buffer A data output buffer can store up to four 32 bit words that have been output from the conditioning component When four words have bee...

Page 637: ...s running indefinitely on the outputs of the noise source Repetition count test similar to the one running in start up tests Adaptive proportion test running on 1024 consecutive samples like during st...

Page 638: ...wer tests 3 When start up health tests are completed During this time three 128 bit noise source samples are used 4 The conditioning stage internal input data buffer is filled again with 128 bit and a...

Page 639: ...error occurs Therefore at each interrupt check that No error occurred The SEIS and CEIS bits must be set to 0 in the RNG_SR register A random number is ready The DRDY bit must be set to 1 in the RNG_...

Page 640: ...cking The RNG runs on two different clocks the AHB bus clock and a dedicated RNG clock The AHB clock is used to clock the AHB banked registers and conditioning component The RNG clock coupled with a p...

Page 641: ...oning output internal register four additional random numbers can be still be read from the RNG_DR register If it is not the case RNG must be re enabled by the application until the expected new noise...

Page 642: ...der to assess the amount of entropy available from the RNG STMicroelectronics has tested the peripheral using German BSI AIS 31 statistical tests T0 to T8 and NIST SP800 90B test suite The results can...

Page 643: ...N Res Res rw rw rw rw rw rw rw rw rw rw rw Bit 31 CONFIGLOCK RNG Config lock 0 Writes to the RNG_CR configuration bits 29 4 are allowed 1 Writes to the RNG_CR configuration bits 29 4 are ignored until...

Page 644: ...bit is taken into account only if CONDRST bit is set to 1 in the same access while CONFIGLOCK remains at 0 Writing to this bit is ignored if CONFIGLOCK 1 Bits 11 8 RNG_CONFIG3 3 0 RNG configuration 3...

Page 645: ...SECS Seed error current status 0 No faulty sequence has currently been detected If the SEIS bit is set this means that a faulty sequence was detected and the situation has been recovered 1 At least o...

Page 646: ...r r Bits 31 0 RNDATA 31 0 Random data 32 bit random data which are valid when DRDY 1 When DRDY 0 RNDATA value is zero It is recommended to always verify that RNG_DR is different from zero Because whe...

Page 647: ...ONFIGLOCK CONDRST Res Res Res Res RNG_CONFIG1 5 0 CLKDIV 3 0 RNG_C ONFIG 2 2 0 NISTC RNG_CO NFIG3 3 0 Res Res CED Res IE RNGEN Res Res Reset value 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x004 R...

Page 648: ...ey lengths of 128 bit and 256 bit Encryption and decryption with multiple chaining modes Electronic codebook ECB mode Cipher block chaining CBC mode Counter CTR mode Galois counter mode GCM Galois mes...

Page 649: ...1 aes_hclk Banked registers DOUT KEY IVI DIN AES key control status IV counter data in data out aes_it 32 bit AHB bus aes_in_dma AES_CR AES_KEYRx AES_SR AES_IVRx AES_DINR AES_DOUTR AES Core AEA swap A...

Page 650: ...rs Now the AES peripheral is ready to switch to Mode 3 for executing data decryption Mode 3 Ciphertext decryption using a key stored in the AES_KEYRx registers When ECB and CBC chaining modes are sele...

Page 651: ...e simplest mode of operation There are no chaining operations and no special initialization stage The message is divided into blocks and each block is encrypted or decrypted separately Note For decryp...

Page 652: ...rocessing Note For decryption a special key scheduling is required before processing the first block MSv42141V1 Encryption Plaintext block 1 Plaintext block 2 Plaintext block 3 Ciphertext block 1 Ciph...

Page 653: ...s required for the CTR decryption since in this chaining scheme the AES core is always used in encryption mode for producing the key stream or counter blocks MSv42142V1 Encryption Plaintext block 1 Ci...

Page 654: ...articular 128 bit block at the end of the message Galois message authentication code GMAC principle Figure 106 GMAC authentication principle Galois message authentication code GMAC allows authenticati...

Page 655: ...CM mode is based on AES in counter mode for confidentiality and it uses CBC for computing the message authentication code It requires an initial value Like GCM the CCM chaining mode can be applied on...

Page 656: ...tion 23 4 6 AES ciphertext stealing and data padding The last block management in these cases is more complex than in the sequence described in this section Data append through polling This method use...

Page 657: ...or write operations which allows for example an interrupt from another peripheral to be served between two AES computations NPBLB bits are not used in header phase of GCM GMAC and CCM chaining modes D...

Page 658: ...bled by hardware when the derivation key is available To restart a derivation key computation repeat steps 4 5 6 and 7 Note The operation of the key preparation lasts 59 or 82 clock cycles depending o...

Page 659: ...in order to send a shorter and higher priority Message 2 Figure 108 Example of suspend mode management A detailed description of suspend resume operations is in the sections dedicated to each AES mod...

Page 660: ...by the AES core In ECB decrypt mode the 128 bit ciphertext input data block C1 in the AES_DINR register first goes through bit byte half word swapping The keying sequence is reversed compared to that...

Page 661: ...decryption In CBC decrypt mode like in ECB decrypt mode the secret key must be prepared to perform an AES decryption After the key preparation process the decryption goes as follows the first 128 bit...

Page 662: ...128 or 256 bits with encryption key Fill the AES_IVRx registers with the initialization vector data if CBC mode has been selected 5 Enable the AES peripheral by setting the EN bit of the AES_CR regis...

Page 663: ...ES_CR register 2 If DMA is not used read four times the AES_DOUTR register to save the last processed block If DMA is used wait until the CCF flag is set in the AES_SR register then stop the DMA trans...

Page 664: ...de Overview The counter mode CTR uses AES as a key stream generator The generated keys are then XOR ed with the plaintext to obtain the ciphertext CTR chaining is defined in NIST Special Publication 8...

Page 665: ...31 0 AES_IVR1 31 0 AES_IVR0 31 0 IVI 127 96 IVI 95 64 IVI 63 32 IVI 31 0 32 bit counter 0x0001 MSv19102V3 Encrypt AES_KEYRx KEY AES_DINR plaintext P1 AES_DOUTR ciphertext C1 DATATYPE 1 0 Swap managem...

Page 666: ...ock if needed 6 Append data in AES and read the result The three possible scenarios are described in Section 23 4 4 AES procedure to perform a cipher operation 7 Repeat the previous step till the seco...

Page 667: ...nly authenticated not encrypted Plaintext message P is both authenticated and encrypted as ciphertext C with a known length Len P that may be non multiple of 16 bytes and cannot exceed 232 2 128 bit b...

Page 668: ...e Table 136 MSv42149V1 4 Final 1 Init 2 Header AES_KEYRx KEY AES_DINR plaintext P1 AES_DOUTR ciphertext C1 DATATYPE 1 0 Swap management AES_IVRx ICB 32 bit counter 0x02 input output Legend XOR Swap ma...

Page 669: ...phase and keep it unchanged in all subsequent phases 5 Initialize the AES_KEYRx registers with a key and initialize AES_IVRx registers with the information as defined in Table 136 6 Start the calcula...

Page 670: ...t are not part of the payload when the last block size is less than 16 bytes Note The payload phase can be skipped if there is no payload data that is Len C 0 see GMAC mode GCM final phase In this las...

Page 671: ...y changed from their initial values In the header phase this step is not required 6 Disable the AES peripheral by clearing the EN bit of the AES_CR register 7 Save the current AES configuration in the...

Page 672: ...ings are the same as with the GCM except that the payload phase is omitted Suspend resume operations in GMAC In GMAC mode the sequence described for the GCM applies except that only the header phase c...

Page 673: ...sage is 16 byte first authentication block B0 composed of three distinct fields Q a bit string representation of the octet length of P Len P Nonce N a single use value that is a new nonce must be assi...

Page 674: ...Len T appended to the ciphertext C of overall length Len C When a part of the message A or P has a length that is a non multiple of 16 bytes a special padding scheme is required Note CCM chaining mod...

Page 675: ...length defined by the first block B0 Table 137 shows how the application must load the B0 data Note The AES peripheral in CCM mode supports counters up to 64 bits as specified by NIST MSv42152V2 2 Hea...

Page 676: ...the EN bit of the AES_CR register EN is automatically reset when the calculation finishes 7 Wait until the end of computation indicated by the CCF flag of the AES_SR transiting to 1 Alternatively use...

Page 677: ...ext C CCM final phase In this last phase the AES peripheral generates the GCM authentication tag and stores it in the AES_DOUTR register The sequence to execute is 1 Indicate the final phase by settin...

Page 678: ...nitialization vector register values previously saved in the memory back into their corresponding AES_IVRx registers 5 Restore the initial setting values in the AES_CR and AES_KEYRx registers 6 Enable...

Page 679: ...half word swapping Word 3 DATATYPE 1 0 10 8 bit byte swapping Word 2 Word 3 DATATYPE 1 0 11 bit swapping Word 3 LSB MSB LSB MSB LSB MSB LSB MSB MSB MSB MSB LSB LSB Word 0 Word 1 LSB Word 0 Word 0 Word...

Page 680: ...by DATATYPE 1 0 bitfield of the AES_CR register 23 4 15 AES initialization vector registers The four AES_IVRx registers keep the initialization vector input bitfield IVI 127 0 The data to write to or...

Page 681: ...Section 23 4 4 AES procedure to perform a cipher operation Figure 125 DMA transfer of a 128 bit data block during input phase Data output using DMA Setting the DMAOUTEN bit of the AES_CR register enab...

Page 682: ...gement AES configuration can be changed at any moment by clearing the EN bit of the AES_CR register Read error flag RDERR Unexpected read attempt of the AES_DOUTR register sets the RDERR flag of the A...

Page 683: ...dividual sources are combined into the common interrupt signal aes_it that connects to NVIC nested vectored interrupt controller Each can individually be enabled disabled by setting clearing the corre...

Page 684: ...CTR 75 Table 141 Processing latency for GCM and CCM in clock cycles Key size Mode of operation Algorithm Init Phase Header phase 1 Payload phase 1 Tag phase 1 128 bit Mode 1 Encryption Mode 3 Decrypti...

Page 685: ...d has no effect if other than GCM GMAC or CCM algorithms are selected through the ALGOMODE bitfield Bit 12 DMAOUTEN DMA output enable This bit enables disables data transferring with DMA in the output...

Page 686: ...g mode This bitfield selects the AES operating mode 00 Mode 1 encryption 01 Mode 2 key derivation or key preparation for ECB CBC decryption 10 Mode 3 decryption 11 Reserved Attempts to write the bitfi...

Page 687: ...cleared by software upon setting the ERRC bit of the AES_CR register Upon the flag setting an interrupt is generated if enabled through the ERRIE bit of the AES_CR register The flag setting has no imp...

Page 688: ...complete 128 bit block of input data to the AES peripheral From the first to the fourth write the corresponding data weights are 127 96 95 64 63 32 and 31 0 Upon each write the data from the 32 bit in...

Page 689: ...tion 23 4 13 AES data registers and data swapping on page 678 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 31 16 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w...

Page 690: ...w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 79 64 w w w w w w w w w w w w w w w w Bits 31 0 KEY 95 64 Cryptographic key bits 95 64 Refer to the AES_KEYR0 register for description of the KEY...

Page 691: ...ed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVI 63 48 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IVI 47 32 rw rw rw rw rw rw rw rw rw rw rw rw rw rw r...

Page 692: ...143 128 w w w w w w w w w w w w w w w w Bits 31 0 KEY 159 128 Cryptographic key bits 159 128 Refer to the AES_KEYR0 register for description of the KEY 255 0 bitfield 31 30 29 28 27 26 25 24 23 22 21...

Page 693: ...completion the software restores the saved contents back into the corresponding suspend registers before resuming the original task These registers can be read only when AES is enabled Reading these...

Page 694: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x018 AES_KEYR2 KEY 95 64 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x01C AES_KEYR3 KEY 127 96 Reset value 0 0 0 0 0 0...

Page 695: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x054 AES_SUSP5R SUSP 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x058 AES_SUSP6R SUSP 31 0 Reset...

Page 696: ...tions based on the Montgomery method for fast modular multiplications More specifically RSA modular exponentiation RSA Chinese Remainder Theorem CRT exponentiation ECC scalar multiplication point on c...

Page 697: ...o 3136 bits for RSA and DH and up to 640 bits for ECC The PKA supports all non singular elliptic curves defined over prime fields that can be described with a short Weierstrass equation y2 x3 ax b mod...

Page 698: ...omputation R2 mod n Section 24 4 2 0x0E 001110 Modular addition A B mod n Section 24 4 3 0x0F 001111 Modular subtraction A B mod n Section 24 4 4 0x10 010000 Montgomery multiplication AxB mod n Sectio...

Page 699: ...yptography for the Financial Services Industry The Elliptic Curve Digital Signature Algorithm ECDSA November 2005 The principles of the main functions are described in this section for a more detailed...

Page 700: ...as below Curve corresponds to the elliptic curve field agreed among actors Alice and Bob Supported curves parameters are summarized in Section 24 5 1 Supported elliptic curves G is the chosen ellipti...

Page 701: ...ling disabling PKA Setting the EN bit to 1 in PKA_CR register enables the PKA peripheral When EN 0 the PKA peripheral is kept under reset with PKA memory still accessible by the application through th...

Page 702: ...the Address Error flag ADDRERRF is set in the PKA_SR register An AHB access to the PKA RAM occurred while the PKA core was using it In this case the RAM Error Flag RAMERRF is set in the PKA_SR registe...

Page 703: ...t significant bit is to be placed in bit 0 at address offset 0x55C the most significant bit is to be placed in bit 31 of address offset 0x578 Then as mentioned above word 0x00000000 should also be wri...

Page 704: ...ation are Map a value from natural domain to Montgomery domain and vice versa Perform a modular multiplication A x B mod n The method to perform above operations are described below Note that x functi...

Page 705: ...d Compute ABR AR x BR mod n Output is in the Montgomery domain e Compute CR C x r2modn mod n Output is in the Montgomery domain f Compute ABCR ABR x CR mod n Output is in the Montgomery domain g optio...

Page 706: ...null RAM 0x404 IN OUT Operand A base of exponentiation 0 A n RAM 0xA44 ROS IN Exponent e 0 e n RAM 0xBD0 Modulus value n Odd integer only n 23136 RAM 0xD5C OUT Result Ae mod n 0 result n RAM 0x724 Ta...

Page 707: ...n Table 155 Table 153 Modular reduction Parameters with direction Value Note Storage Size IN MODE 0x0D PKA_CR 6 bits Operand length In bits not null RAM 0x400 32 bits Modulus length In bits 8 value 31...

Page 708: ...the following optimization for decryption and signing based on the Chinese remainder theorem CRT p and q are precomputed primes stored as part of the private key dP d mod p 1 dQ d mod q 1 and qinv q 1...

Page 709: ...atisfies or not the curves over prime fields equation y2 x3 ax b mod p where a and b are elements of the curve Operation instructions for point on elliptic curve Fp check are summarized in Table 159 T...

Page 710: ...ive RAM 0x408 Curve coefficient a Absolute value a p RAM 0x40C EOS Curve coefficient b b p RAM 0x7FC Curve modulus value p Odd integer prime 0 p 2640 RAM 0x460 Point P coordinate x x p RAM 0x55C Point...

Page 711: ...5 is summarized in Table 162 input parameters and in Table 163 output parameters The application should check if the output error is equal to zero if it is different from zero a new k should be genera...

Page 712: ...th in bits 8 value 640 RAM 0x404 Curve coefficient a sign 0x0 positive 0x1 negative RAM 0x408 Curve coefficient a Absolute value a p RAM 0x40C EOS Curve modulus value p Odd integer prime 0 p 2640 RAM...

Page 713: ...0x26 PKA_CR 6 bits Curve prime order n length In bits not null RAM 0x404 32 bits Curve modulus p length In bits not null 8 value 640 RAM 0x4B4 Curve coefficient a sign 0x0 positive 0x1 negative RAM 0x...

Page 714: ...rdinates Gx Gy the integers a and b coefficients of the short Weierstrass equation For the last bullet when standard bodies define a as negative PKA supports two representations 1 a defined as p a in...

Page 715: ...npoolP512t1 secp192k1 secp192r1 SEC Standards for Efficient Cryptography SEC 2 curves https www secg org secp224k1 secp224r1 secp256k1 secp256r1 secp384r1 secp521r1 Recommended curve parameters for pu...

Page 716: ...Fast 273522000 CRT 1 73378000 Table 169 ECC scalar multiplication computation times 1 1 These times depend on the number of 1 s included in the scalar parameter Mode Modulus length in bits 160 192 256...

Page 717: ...a summary of the available features Table 171 ECDSA verification average computation times Modulus length in bits 160 192 256 320 384 512 521 3500000 5350000 10498000 18126000 29118000 61346000 715880...

Page 718: ...must be kept at reset value Bit 17 PROCENDIE End of operation interrupt enable 0 No interrupt is generated when PROCENDF flag is set in PKA_SR 1 An interrupt is generated when PROCENDF flag is set in...

Page 719: ...is out of range unmapped address This bit is cleared using ADDRERRFC bit in PKA_CLRFR Bit 19 RAMERRF PKA RAM error flag 0 No PKA RAM access error 1 An AHB access to the PKA RAM occurred while the PKA...

Page 720: ...22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res ADDR ERRFC RAM ERRFC Res PROC ENDFC Res w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 721: ...s Res Res Res Res Res Res Res Res Res Res ADDRERRIE RAMERRIE Res PROCENDIE Res Res Res MODE 5 0 Res Res Res Res Res Res START EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0x004 PKA_SR Res Res Res Res Res Res...

Page 722: ...ler It may be used for a variety of purposes including measuring the pulse lengths of input signals input capture or generating output waveforms output compare PWM complementary PWM with dead time ins...

Page 723: ...ircuit to control the timer with external signals and to interconnect several timers together Repetition counter to update the timer registers only after a given number of cycles of the counter 2 brea...

Page 724: ...ompare 1 register Notes Reg Preload registers transferred to active registers on U event according to control bit Event Interrupt DMA output TIMx_BKIN Internal sources Auto reload register Capture Com...

Page 725: ...ad enable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow or underflow when downcounting and if the UDIS bit equals 0 in the TIMx_CR1 register It can also...

Page 726: ...N Timerclock CK_CNT Counter register Update event UEV 0 Prescaler control register 1 0 Write a new value in TIMx_PSC Prescaler buffer 1 0 Prescaler counter 0 1 0 1 0 1 0 1 01 02 03 FA FB F7 F8 F9 FC M...

Page 727: ...egisters Then no update event occurs until the UDIS bit has been written to 0 However the counter restarts from 0 as well as the counter of the prescaler but the prescale rate does not change In addit...

Page 728: ...gram internal clock divided by 2 00 02 03 04 05 06 07 32 33 34 35 36 31 MS31078V2 CK_PSC CNT_EN Timerclock CK_CNT Counter register Update event UEV Counter overflow Update interrupt flag UIF 01 MS3107...

Page 729: ...Figure 134 Counter timing diagram internal clock divided by N 0000 0001 0035 0036 MS31080V2 CK_PSC Timerclock CK_CNT Counter register Update event UEV Counter overflow Update interrupt flag UIF CNT_E...

Page 730: ...ck CK_CNT Counter register Update event UEV Counter overflow Update interrupt flag UIF 00 02 03 04 05 06 07 32 33 34 35 36 31 01 CEN Auto reload preload register Write a new value in TIMx_ARR MS31083V...

Page 731: ...ver the counter restarts from the current auto reload value whereas the counter of the prescaler restarts from 0 but the prescale rate doesn t change In addition if the URS bit update request selectio...

Page 732: ...internal clock divided by 2 36 34 33 32 31 30 2F 04 03 02 01 00 05 MS31184V1 CK_PSC CNT_EN Timerclock CK_CNT Counter register Update event UEV Counter underflow cnt_udf Update interrupt flag UIF 35 MS...

Page 733: ...gure 140 Counter timing diagram internal clock divided by N 0000 0001 0001 0000 MS31186V1 CK_PSC Timerclock CK_CNT Counter register Update event UEV Counter underflow Update interrupt flag UIF CNT_EN...

Page 734: ...rent direction of the counter The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register by software or by using the sla...

Page 735: ...tive register is updated with the preload value content of the TIMx_ARR register Note that if the update source is a counter overflow the auto reload is updated before the counter is reloaded so that...

Page 736: ...TIMx_ARR 0x36 MS31190V1 CK_PSC CNT_EN Timerclock CK_CNT Counter register Update event UEV Counter underflow Update interrupt flag UIF 0003 0002 0001 0000 0001 0002 0003 0034 0035 MS31191V1 CK_PSC Tim...

Page 737: ...nderflow 00 1F 20 MS31192V1 CK_PSC Timerclock CK_CNT Counter register Update event UEV Counter underflow Update interrupt flag UIF 01 FD 36 MS31193V1 CK_PSC Timerclock CK_CNT Counter register Update e...

Page 738: ...t each counter overflow and at each counter underflow in center aligned mode Although this limits the maximum number of repetition to 32768 PWM cycles it makes it possible to update the duty cycle twi...

Page 739: ...flow For example for RCR 3 the UEV is generated each 4th overflow or underflow event depending on when the RCR was written Figure 148 Update rate examples depending on mode and TIMx_RCR register setti...

Page 740: ...ammed by the ETPS 1 0 bitfield and digitally filtered with the ETF 3 0 bitfield Figure 149 External trigger input block The ETR input comes from multiple sources input pins default configuration compa...

Page 741: ...ts and can be changed only by software except UG which remains cleared automatically As soon as the CEN bit is written to 1 the prescaler is clocked by the internal clock CK_INT Figure 151 shows the b...

Page 742: ...5 Configure the timer in external clock mode 1 by writing SMS 111 in the TIMx_SMCR register 6 Select TI2 as the trigger input source by writing TS 00110 in the TIMx_SMCR register 7 Enable the counter...

Page 743: ...nal trigger input block 1 Refer to Figure 150 TIM1 ETR input circuitry For example to configure the upcounter to count each 2 rising edges on ETR use the following procedure Counter clock CK_CNT CK_PS...

Page 744: ...ing CEN 1 in the TIMx_CR1 register The counter counts once each 2 ETR rising edges The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit...

Page 745: ...56 Capture compare channel example channel 1 input stage The output stage generates an intermediate waveform which is then used for reference OCxRef active high The polarity acts at the end of the cha...

Page 746: ...R CC1NE 0 1 CC1P TIM1_CCER 0 1 CC1NP TIM1_CCER OC1 Output enable circuit OC1N CC1E TIM1_CCER CC1NE OSSI TIM1_BDTR MOE OSSR 0x 10 11 11 01 x0 Output selector OCxREF OC1REFC To the master mode controlle...

Page 747: ...in the TIMx_CCRx register CCxOF is cleared when written with 0 The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises To do this use the following procedure 1 S...

Page 748: ...pt flag CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared An interrupt is generated depending on the CC1IE bit A DMA request is generated depending on th...

Page 749: ..._SMCR register 8 Enable the captures write the CC1E and CC2E bits to 1 in the TIMx_CCER register Figure 161 PWM input mode timing 25 3 9 Forced output mode In output mode CCxS bits 00 in the TIMx_CCMR...

Page 750: ...bit is set CCxDE bit in the TIMx_DIER register CCDS bit in the TIMx_CR2 register for the DMA request selection The TIMx_CCRx registers can be programmed with or without preload registers using the OC...

Page 751: ...s are transferred to the shadow registers only when an update event occurs before starting the counter all registers must be initialized by setting the UG bit in the TIMx_EGR register OCx polarity is...

Page 752: ...ion Downcounting is active when DIR bit in TIMx_CR1 register is high Refer to the Downcounting mode on page 731 In PWM mode 1 the reference signal OCxRef is low as long as TIMx_CNT TIMx_CCRx else it b...

Page 753: ...enter aligned mode 1 selected for CMS 01 in TIMx_CR1 register Figure 164 Center aligned PWM waveforms ARR 8 Hints on using center aligned mode When starting in center aligned mode the current up down...

Page 754: ...shift are determined by a pair of TIMx_CCRx register One register controls the PWM during up counting the second during down counting so that PWM is adjusted every half PWM cycle OC1REFC or OC2REFC is...

Page 755: ...nnels one OCx output per pair of CCR registers by writing 1100 Combined PWM mode 1 or 1101 Combined PWM mode 2 in the OCxM bits in the TIMx_CCMRx register When a given channel is used as combined PWM...

Page 756: ...R5 allow selection on which reference signal the OC5REF is combined The resulting signals OCxREFC are made of an AND logical combination of two reference PWMs If GC5C1 is set OC1REFC is controlled by...

Page 757: ...ntrinsic delays of level shifters delays due to power switches The polarity of the outputs main output OCx or complementary OCxN can be selected independently for each output This is done by writing t...

Page 758: ...ge The OCxN output signal is the opposite of the reference signal except for the rising edge which is delayed relative to the reference falling edge If the delay is greater than the width of the activ...

Page 759: ...ecomes active as soon as OCxREF is high For example if CCxNP 0 then OCxN OCxRef On the other hand when both OCx and OCxN are enabled CCxE CCxNE 1 OCx becomes active when OCxREF is high whereas OCxN is...

Page 760: ...on Because MOE falling edge can be asynchronous a resynchronization circuit has been inserted between the actual signal acting on the outputs and the synchronous control bit accessed in the TIMx_BDTR...

Page 761: ...used to guarantee that break events are handled COMP2 output BK2CMP2E BK2CMP2P COMP1 output BK2CMP1E BK2CMP1P BKIN2 inputs from AF controller BK2INE BK2INP BK2F 3 0 Filter BK2P Application break requ...

Page 762: ...e otherwise the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high The break status flag SBIF BIF and B2IF bits in the TIMx_SR register is set An interrupt is genera...

Page 763: ...ISx 1 OCx OCxN not implemented CCxP 0 OISx 0 OCx OCxN not implemented CCxP 1 OISx 1 OCx OCxN not implemented CCxP 1 OISx 0 OCx OCxN CCxE 1 CCxP 0 OISx 0 CCxNE 1 CCxNP 0 OISxN 1 OCx OCxN CCxE 1 CCxP 0...

Page 764: ...behavior in case of active signals on BRK and BRK2 inputs In this case both outputs have active high polarities CCxP CCxNP 0 in TIMx_CCER register Figure 173 PWM output state following BRK and BRK2 pi...

Page 765: ...nal the fault event The bidirectional mode is inhibited if the polarity bits are not correctly set active high polarity for safety purposes The break software events BG and B2G also cause the break I...

Page 766: ...by hardware when the application break condition disappears From this point the break circuitry is armed and active and the MOE bit can be set to re enable the PWM outputs Figure 175 Output redirecti...

Page 767: ...CxCE In this example the timer TIMx is programmed in PWM mode Figure 176 Clearing TIMx OCxREF Note In case of a PWM with a 100 duty cycle if CCRx ARR then OCxREF is enabled again at the next counter o...

Page 768: ...on of all the channels at the same time COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware on TRGI rising edge A flag is set when the COM event occurs COMI...

Page 769: ...imer is waiting for the trigger the configuration must be In upcounting CNT CCRx ARR in particular 0 CCRx In downcounting CNT CCRx Figure 178 Example of one pulse mode For example one may want to gene...

Page 770: ...CEN bit which enables the counter Then the comparison between the counter and the compare value makes the output toggle But several clock cycles are needed for these operations and it limits the mini...

Page 771: ...pending on the sequence the counter counts up or down the DIR bit in the TIMx_CR1 register is modified by hardware accordingly The DIR bit is calculated at each transition on any input TI1 or TI2 what...

Page 772: ...configuration is the following CC1S 01 TIMx_CCMR1 register TI1FP1 mapped on TI1 CC2S 01 TIMx_CCMR2 register TI1FP2 mapped on TI2 CC1P 0 and CC1NP 0 TIMx_CCER register TI1FP1 non inverted TI1FP1 TI1 CC...

Page 773: ...e timer counter register s bit 31 TIMxCNT 31 This allows both the counter value and a potential roll over condition signaled by the UIFCPY flag to be read in an atomic way It eases the calculation of...

Page 774: ...bit in the TIMx_CR2 register The slave mode controller is configured in reset mode the slave input is TI1F_ED Thus each time one of the 3 inputs toggles the counter restarts counting from 0 This creat...

Page 775: ...e CC1S bits in the TIMx_CCMR1 register to 01 The digital filter can also be programmed if needed Program the channel 2 in PWM 2 mode with the desired delay write the OC2M bits to 111 and the CC2S bits...

Page 776: ...2 Figure 183 Example of Hall sensor interface Counter CNT TRGO OC2REF CCR2 OC1 OC1N COM Write CCxE CCxNE TIH1 TIH2 TIH3 CCR1 OC2 OC2N OC3 OC3N C796 and OCxM for next step Interfacing timer Advanced c...

Page 777: ...gured The CC1S bits select the input capture source only CC1S 01 in the TIMx_CCMR1 register Write CC1P 0 and CC1NP 0 in TIMx_CCER register to validate the polarity and detect rising edges only Configu...

Page 778: ...mode the counter doesn t start if CEN 0 whatever is the trigger input level The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high The TIF flag...

Page 779: ...Figure 186 Control circuit in trigger mode Slave mode Combined reset trigger mode In this case a rising edge of the selected trigger input TRGI reinitializes the counter generates an update of the re...

Page 780: ...ER register to validate the polarity and detect rising edge only 3 Configure the timer in trigger mode by writing SMS 110 in TIMx_SMCR register Select TI1 as the input source by writing TS 00101 in TI...

Page 781: ...from the timer 25 3 28 DMA burst mode The TIMx timers have the capability to generate multiple DMA requests upon a single event The main purpose is to be able to re program part of the timer multiple...

Page 782: ...fer should be 6 Let s take the example of a buffer in the RAM containing data1 data2 data3 data4 data5 and data6 The data is transferred to the CCRx registers as follows on the first update DMA reques...

Page 783: ...filters ETR TIx 00 tDTS tCK_INT 01 tDTS 2 tCK_INT 10 tDTS 4 tCK_INT 11 Reserved do not program this value Note tDTS 1 fDTS tCK_INT 1 fCK_INT Bit 7 ARPE Auto reload preload enable 0 TIMx_ARR register...

Page 784: ...his bit is set and cleared by software to enable disable UEV event generation 0 UEV enabled The Update UEV event is generated by one of the following events Counter overflow underflow Setting the UG b...

Page 785: ...was already high as soon as a capture or compare match occurs TRGO2 0100 Compare OC1REFC signal is used as trigger output TRGO2 0101 Compare OC2REFC signal is used as trigger output TRGO2 0110 Compare...

Page 786: ...reset mode then the signal on TRGO is delayed compared to the actual reset 001 Enable the Counter Enable signal CNT_EN is used as trigger output TRGO It is useful to start several timers at the same t...

Page 787: ...Res Res Res Res Res Res Res Res TS 4 3 Res Res Res SMS 3 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETP ECE ETPS 1 0 ETF 3 0 MSM TS 2 0 OCCS SMS 2 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw...

Page 788: ...MPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Bit 7 MSM Master slave mode 0 No action 1 The effect of an event on the t...

Page 789: ...low Both start and stop of the counter are controlled 0110 Trigger Mode The counter starts at a rising edge of the trigger TRGI but it is not reset Only the start of the counter is controlled 0111 Ex...

Page 790: ...2 DMA request enable 0 CC2 DMA request disabled 1 CC2 DMA request enabled Bit 9 CC1DE Capture Compare 1 DMA request enable 0 CC1 DMA request disabled 1 CC1 DMA request enabled Bit 8 UDE Update DMA re...

Page 791: ...rc_w0 rc_w0 Bits 31 18 Reserved must be kept at reset value Bit 17 CC6IF Compare 6 interrupt flag Refer to CC1IF description Note Channel 6 can only be configured as output Bit 16 CC5IF Compare 5 int...

Page 792: ...No trigger event occurred 1 Trigger interrupt pending Bit 5 COMIF COM interrupt flag This flag is set by hardware on COM event when Capture compare Control bits CCxE CCxNE OCxM have been updated It i...

Page 793: ...8 B2G Break 2 generation This bit is set by software in order to generate an event it is automatically cleared by hardware 0 No action 1 A break 2 event is generated MOE bit is cleared and B2IF flag...

Page 794: ...t or DMA request is sent if enabled If channel CC1 is configured as input The current value of the counter is captured in TIMx_CCR1 register The CC1IF flag is set the corresponding interrupt or DMA re...

Page 795: ...0000 No filter sampling is done at fDTS 0001 fSAMPLING fCK_INT N 2 0010 fSAMPLING fCK_INT N 4 0011 fSAMPLING fCK_INT N 8 0100 fSAMPLING fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0...

Page 796: ...1CE description Bits 24 14 12 OC2M 3 0 Output Compare 2 mode Refer to OC1M 3 0 description Bit 11 OC2PE Output Compare 2 preload enable Refer to OC1PE description Bit 10 OC2FE Output Compare 2 fast en...

Page 797: ...vent is detected on TRGI signal Then a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update 1001 Retrigerrable OPM mode 2 In up counting mode the channel...

Page 798: ...s the latency between a trigger event and a transition on the timer output It must be used in one pulse mode OPM bit set in TIMx_CR1 register to have the output pulse starting as soon as possible afte...

Page 799: ...channel is configured as input IC4 is mapped on TI3 11 CC4 channel is configured as input IC4 is mapped on TRC This mode is working only if an internal trigger input is selected through TS bit TIMx_S...

Page 800: ...This mode is working only if an internal trigger input is selected through TS bit TIMx_SMCR register Note CC4S bits are writable only when the channel is OFF CC4E 0 in TIMx_CCER Bit 7 OC3CE Output co...

Page 801: ...17 CC5P Capture Compare 5 output polarity Refer to CC1P description Bit 16 CC5E Capture Compare 5 output enable Refer to CC1E description Bit 15 CC4NP Capture Compare 4 complementary output polarity...

Page 802: ...Commutation event is generated Bit 1 CC1P Capture Compare 1 output polarity 0 OC1 active high output mode Edge sensitivity selection input mode see below 1 OC1 active low output mode Edge sensitivity...

Page 803: ...output state 1 X X 0 0 Output disabled not driven by the timer Hi Z OCx 0 OCxN 0 0 0 1 Output disabled not driven by the timer Hi Z OCx 0 OCxREF Polarity OCxN OCxREF xor CCxNP 0 1 0 OCxREF Polarity O...

Page 804: ...t 0 Bits 30 16 Reserved must be kept at reset value Bits 15 0 CNT 15 0 Counter value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 P...

Page 805: ...event U_RC any write to the TIMx_RCR register is not taken in account until the next repetition update event It means in PWM mode REP 1 corresponds to the number of PWM periods in edge aligned mode th...

Page 806: ...ounter TIMx_CNT and signaled on OC2 output If channel CC2 is configured as input CCR2 is the counter value transferred by the last input capture 2 event IC2 The TIMx_CCR2 register is read only and can...

Page 807: ...pture compare 4 register preload value It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register bit OC4PE Else the preload value is copied in the active capture compa...

Page 808: ...isarmed This bit is cleared by hardware when no break source is active The BKDSRM bit must be set by software to release the bidirectional output control open drain output in Hi Z state and then be po...

Page 809: ...N 6 1111 fSAMPLING fDTS 32 N 8 Note This bit cannot be modified when LOCK level 1 has been programmed LOCK bits in TIMx_BDTR register Bits 19 16 BKF 3 0 Break filter This bit field defines the frequen...

Page 810: ...t be modified as long as LOCK level 1 has been programmed LOCK bits in TIMx_BDTR register Note Any write operation to this bit takes a delay of 1 APB clock cycle to become effective Bit 12 BKE Break e...

Page 811: ...er be written 10 LOCK Level 2 LOCK Level 1 CC Polarity bits CCxP CCxNP bits in TIMx_CCER register as long as the related channel is configured in output through the CCxS bits as well as OSSR and OSSI...

Page 812: ...ed In this case the transfer is done to 7 registers starting from the following address TIMx_CR1 address DBA According to the configuration of the DMA Data Size several cases may occur If the DMA Data...

Page 813: ...28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res TI1_ RMP Res R...

Page 814: ...13 12 OC6M 3 0 Output compare 6 mode Refer to OC1M description Bit 11 OC6PE Output compare 6 preload enable Refer to OC1PE description Bit 10 OC6FE Output compare 6 fast enable Refer to OC1FE descrip...

Page 815: ...s bit can either have immediate effect or be preloaded and taken into account after an update event if preload feature is selected in TIMxCCMR1 Note it is also possible to apply this distortion on com...

Page 816: ...0 COMP2 input polarity is not inverted active low if BKP 0 active high if BKP 1 1 COMP2 input polarity is inverted active high if BKP 0 active low if BKP 1 Note This bit can not be modified as long as...

Page 817: ...it 0 BKINE BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input BKIN input is ORed with the other BRK sources 0 BKIN input disabled 1 BKIN input enabled N...

Page 818: ...ote This bit can not be modified as long as LOCK level 1 has been programmed LOCK bits in TIMx_BDTR register Bits 8 3 Reserved must be kept at reset value Bit 2 BK2CMP2E BRK2 COMP2 enable This bit ena...

Page 819: ...SEL 3 0 rw rw rw rw rw rw rw rw Bits 31 28 Reserved must be kept at reset value Bits 27 24 TI4SEL 3 0 selects TI4 0 to TI4 15 input 0000 TIM1_CH4 input Others Reserved Bits 23 20 Reserved must be kept...

Page 820: ...s Res SBIF CC4OF CC3OF CC2OF CC1OF B2IF BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 TIM1_EGR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 821: ...0 0 0 0 0 0 0 0 0 0 0x3C TIM1_CCR3 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CCR3 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x40 TIM1_CCR4 Res Res Res Res Res Res Res Res...

Page 822: ...R6 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x60 TIM1_AF1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res ETRSEL 3 0 Res Res BKCMP2P BKCMP1P BKINP Res Res Res Res Res Res BKCMP2E B...

Page 823: ...own auto reload counter 16 bit programmable prescaler used to divide also on the fly the counter clock frequency by any factor between 1 and 65535 Up to 4 independent channels for Input capture Output...

Page 824: ...red to active registers on U event according to control bit Event Interrupt DMA output Auto reload register Capture Compare 2 register Prescaler Prescaler Output control U U CC3I CC4I Output control O...

Page 825: ...enable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow or underflow when downcounting and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be...

Page 826: ...Timerclock CK_CNT Counter register Update event UEV 0 Prescaler control register 1 0 Write a new value in TIMx_PSC Prescaler buffer 1 0 Prescaler counter 0 1 0 1 0 1 0 1 01 02 03 FA FB F7 F8 F9 FC MS...

Page 827: ...not change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA r...

Page 828: ...timing diagram internal clock divided by 4 MS31079V2 CK_PSC CNT_EN Timerclock CK_CNT Counter register Update event UEV Counter overflow Update interrupt flag UIF 0034 0035 0036 0000 0001 0002 0003 00...

Page 829: ...ARPE 0 TIMx_ARR not preloaded 00 1F 20 MS31081V2 CK_PSC Timerclock CK_CNT Counter register Update event UEV Counter overflow Update interrupt flag UIF FF 36 MS31082V2 CK_PSC Timerclock CK_CNT Counter...

Page 830: ...rts from 0 but the prescale rate doesn t change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the...

Page 831: ...ternal clock divided by 1 Figure 198 Counter timing diagram internal clock divided by 2 36 34 33 32 31 30 2F 04 03 02 01 00 05 MS31184V1 CK_PSC CNT_EN Timerclock CK_CNT Counter register Update event U...

Page 832: ...re 200 Counter timing diagram internal clock divided by N 0000 0001 0001 0000 MS31186V1 CK_PSC Timerclock CK_CNT Counter register Update event UEV Counter underflow Update interrupt flag UIF CNT_EN 00...

Page 833: ...rent direction of the counter The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register by software or by using the sla...

Page 834: ...of the TIMx_ARR register Note that if the update source is a counter overflow the auto reload is updated before the counter is reloaded so that the next period is the expected one the counter is load...

Page 835: ...ed mode 2 or 3 is used with an UIF on overflow MS31190V1 CK_PSC CNT_EN Timerclock CK_CNT Counter register Update event UEV Counter underflow Update interrupt flag UIF 0003 0002 0001 0000 0001 0002 000...

Page 836: ...rflow 00 1F 20 MS31192V1 CK_PSC Timerclock CK_CNT Counter register Update event UEV Counter underflow Update interrupt flag UIF 01 FD 36 MS31193V1 CK_PSC Timerclock CK_CNT Counter register Update even...

Page 837: ...more details Internal clock source CK_INT If the slave mode controller is disabled SMS 000 in the TIMx_SMCR register then the CEN DIR in the TIMx_CR1 register and UG bits in the TIMx_EGR register are...

Page 838: ...0 bits in the TIMx_TISEL register 2 Configure channel 2 to detect rising edges on the TI2 input by writing CC2S 01 in the TIMx_CCMR1 register 3 Configure the input filter duration by writing the IC2F...

Page 839: ...by writing CEN 1 in the TIMx_CR1 register When a rising edge occurs on TI2 the counter counts once and the TIF flag is set The delay between the rising edge on TI2 and the actual clock of the counter...

Page 840: ...CE 1 in the TIMx_SMCR register 6 Enable the counter by writing CEN 1 in the TIMx_CR1 register The counter counts once each 2 ETR rising edges The delay between the rising edge on ETR and the actual cl...

Page 841: ...can be used as trigger input by the slave mode controller or as the capture command It is prescaled before the capture register ICxPS Figure 213 Capture Compare channel example channel 1 input stage...

Page 842: ...d register is copied into the shadow register which is compared to the counter MSv63030V1 CC1E compare shadow register Comparator Capture compare preload register Counter IC1PS CC1S 0 CC1S 1 Capture I...

Page 843: ...must 5 internal clock cycles We must program a filter duration longer than these 5 clock cycles We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected sam...

Page 844: ...te the CC1S bits to 01 in the TIMx_CCMR1 register TI1 selected 3 Select the active polarity for TI1FP1 used both for capture in TIMx_CCR1 and counter clear write the CC1P to 0 and the CC1NP bit to 0 a...

Page 845: ...to a programmable value defined by the output compare mode OCxM bits in the TIMx_CCMRx register and the output polarity CCxP bit in the TIMx_CCER register The output pin can keep its level OCXM 000 be...

Page 846: ...the TIMx_CCMRx register and eventually the auto reload preload register in upcounting or center aligned modes by setting the ARPE bit in the TIMx_CR1 register As the preload registers are transferred...

Page 847: ...in the TIMx_CR1 register PWM edge aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low Refer to Upcounting mode on page 827 In the following exa...

Page 848: ...n the CMS bits in TIMx_CR1 register are different from 00 all the remaining configurations having the same effect on the ocxref OCx signals The compare flag is set when the counter counts up when it c...

Page 849: ...n is not updated if a value greater than the auto reload value is written in the counter TIMx_CNT TIMx_ARR For example if the counter was counting up it continues to count up The direction is updated...

Page 850: ...ance if an OC1REFC signal is generated on channel 1 Asymmetric PWM mode 1 it is possible to output either the OC2REF signal on channel 2 or an OC2REFC signal resulting from asymmetric PWM mode 2 Figur...

Page 851: ...igured in PWM mode 1 Channel 3 is configured in Combined PWM mode 2 Channel 4 is configured in PWM mode 1 Figure 221 Combined PWM mode on channels 1 and 3 26 3 12 Clearing the OCxREF signal on an exte...

Page 852: ...ger prescaler should be kept off bits ETPS 1 0 in the TIMx_SMCR register are cleared to 00 2 The external clock mode 2 must be disabled bit ECE in the TIM1_SMCR register is cleared to 0 3 The external...

Page 853: ...starting when the timer is waiting for the trigger the configuration must be CNT CCRx ARR in particular 0 CCRx Figure 223 Example of one pulse mode For example one may want to generate a positive puls...

Page 854: ...er Then the comparison between the counter and the compare value makes the output toggle But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get...

Page 855: ...ransitions of the two inputs is evaluated and generates count pulses as well as the direction signal Depending on the sequence the counter counts up or down the DIR bit in the TIMx_CR1 register is mod...

Page 856: ...r TI1FP1 mapped on TI1 CC2S 01 TIMx_CCMR2 register TI2FP2 mapped on TI2 CC1P and CC1NP 0 TIMx_CCER register TI1FP1 noninverted TI1FP1 TI1 CC2P and CC2NP 0 TIMx_CCER register TI2FP2 noninverted TI2FP2...

Page 857: ...update interrupt flag UIF into bit 31 of the timer counter register s bit 31 TIMxCNT 31 This permits to atomically read both the counter value and a potential roll over condition signaled by the UIFCP...

Page 858: ...in TIMx_CCER register to validate the polarity and detect rising edges only 2 Configure the timer in reset mode by writing SMS 100 in TIMx_SMCR register Select TI1 as the input source by writing TS 0...

Page 859: ...ter starts or stops The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input Figure 228 Control circuit in gated mode 1 The conf...

Page 860: ...rating in reset mode gated mode or trigger mode It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register In the following example the upcounter is incremented at each risi...

Page 861: ...ly for timer synchronization or chaining When one Timer is configured in Master Mode it can reset start stop or clock the counter of another Timer configured in Slave Mode Figure 231 Master Slave time...

Page 862: ...TIM1_CR2 register a rising edge is output on TRGO each time an update event is generated 2 To connect the TRGO output of TIM1 to TIM2 TIM2 must be configured in slave mode using ITR0 as internal trigg...

Page 863: ...e timers can easily be reset by software using the UG bit in the TIMx_EGR registers In the next example refer to Figure 234 we synchronize TIM1 and TIM2 TIM1 is the master and starts from 0 TIM2 is th...

Page 864: ...counter clock frequencies are divided by 3 by the prescaler compared to CK_INT fCK_CNT fCK_INT 3 1 Configure TIM1 master mode to send its Update Event UEV as trigger output MMS 010 in the TIM1_CR2 reg...

Page 865: ...overhead but it can also be used to read several registers in a row at regular intervals The DMA controller destination is unique and must point to the virtual register TIMx_DMAR On a given timer even...

Page 866: ...ble TIMx 5 Enable the DMA channel This example is for the case where every CCRx register has to be updated once If every CCRx register is to be updated twice for example the number of data to transfer...

Page 867: ...n ratio between the timer clock CK_INT frequency and sampling clock used by the digital filters ETR TIx 00 tDTS tCK_INT 01 tDTS 2 tCK_INT 10 tDTS 4 tCK_INT 11 Reserved Bit 7 ARPE Auto reload preload e...

Page 868: ...st if enabled Bit 1 UDIS Update disable This bit is set and cleared by software to enable disable UEV event generation 0 UEV enabled The Update UEV event is generated by one of the following events Co...

Page 869: ...D between CEN control bit and the trigger input when configured in gated mode When the Counter Enable signal is controlled by the trigger input there is a delay on TRGO except if the master slave mode...

Page 870: ...bit enables External clock mode 2 0 External clock mode 2 disabled 1 External clock mode 2 enabled The counter is clocked by any active edge on the ETRF signal Note Setting the ECE bit has the same e...

Page 871: ...G fCK_INT N 4 0011 fSAMPLING fCK_INT N 8 0100 fSAMPLING fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 101...

Page 872: ...111 External Trigger input ETRF 01000 Internal Trigger 4 ITR4 01001 Internal Trigger 5 ITR5 01010 Internal Trigger 6 ITR6 01011 Internal Trigger 7 ITR7 01100 Internal Trigger 8 ITR8 Others Reserved Se...

Page 873: ...ising edge of the trigger TRGI but it is not reset Only the start of the counter is controlled 0111 External Clock Mode 1 Rising edges of the selected trigger TRGI clock the counter 1000 Combined rese...

Page 874: ...rrupt disabled 1 CC4 interrupt enabled Bit 3 CC3IE Capture Compare 3 interrupt enable 0 CC3 interrupt disabled 1 CC3 interrupt enabled Bit 2 CC2IE Capture Compare 2 interrupt enable 0 CC2 interrupt di...

Page 875: ...e TIMx_CCR1 register input capture mode only 0 No compare match No input capture occurred 1 A compare match or an input capture occurred If channel CC1 is configured as output this flag is set when th...

Page 876: ...t 1 CC1G Capture compare 1 generation This bit is set by software in order to generate an event it is automatically cleared by hardware 0 No action 1 A capture compare event is generated on channel 1...

Page 877: ...9 8 7 6 5 4 3 2 1 0 IC2F 3 0 IC2PSC 1 0 CC2S 1 0 IC1F 3 0 IC1PSC 1 0 CC1S 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 12 IC2F 3 0 Input...

Page 878: ...NG fDTS 8 N 8 1010 fSAMPLING fDTS 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Bits 3 2 IC1PSC 1 0 Inpu...

Page 879: ...pare 2 fast enable Bits 9 8 CC2S 1 0 Capture Compare 2 selection This bit field defines the direction of the channel input output as well as the used input 00 CC2 channel is configured as output 01 CC...

Page 880: ...tected on TRGI signal Then a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update In down counting mode the channel is inactive until a trigger event is...

Page 881: ...rigger is ON The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles 1 An active edge on the trigger input acts like a compare match on CC1 output Then OC i...

Page 882: ...0 Input capture 3 filter Bits 3 2 IC3PSC 1 0 Input capture 3 prescaler Bits 1 0 CC3S 1 0 Capture Compare 3 selection This bit field defines the direction of the channel input output as well as the us...

Page 883: ...This bit field defines the direction of the channel input output as well as the used input 00 CC3 channel is configured as output 01 CC3 channel is configured as input IC3 is mapped on TI3 10 CC3 cha...

Page 884: ...t mode Edge sensitivity selection input mode see below When CC1 channel is configured as input both CC1NP CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations CC...

Page 885: ...rw rw rw rw rw rw rw rw Bits 31 0 CNT 31 0 counter value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UIFCPY CNT 30 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4...

Page 886: ...ior The counter is blocked while the auto reload value is null 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR1 31 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4...

Page 887: ...o the counter TIMx_CNT and signalled on OC2 output If channel CC2 is configured as input CCR2 is the counter value transferred by the last input capture 2 event IC2 The TIMx_CCR2 register is read only...

Page 888: ...4S bits in TIMx_CCMR4 register CCR4 is the counter value transferred by the last input capture 4 event IC4 The TIMx_CCR4 register is read only and cannot be programmed 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 889: ...Mx_DCR register DMA index is automatically controlled by the DMA transfer and ranges from 0 to DBL DBL configured in TIMx_DCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Re...

Page 890: ...internal clock as per ETR_RMP bit in TIM2_OR1 0001 COMP1 0010 COMP2 Others Reserved Bits 13 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res...

Page 891: ...CC3OF CC2OF CC1OF Res Res TIF Res CC4IF CC3IF CC2IF CC1IF UIF Reset value 0 0 0 0 0 0 0 0 0 0 0x14 TIMx_EGR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 892: ...0 0 0 0 0 0 0 0 0 0x40 TIMx_CCR4 CCR4 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x44 Reserved 0x48 TIMx_DCR Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 893: ...s 0x68 TIM2_TISEL Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TI2SEL 3 0 Res Res Res Res TI1SEL 3 0 Reset value 0 0 0 0 0 0 0 0 Table 185 TIM2 register map and rese...

Page 894: ...troller prescalers The TIM16 TIM17 timers are completely independent and do not share any resources 27 2 TIM16 TIM17 main features The TIM16 TIM17 timers include the following features 16 bit auto rel...

Page 895: ...uto reload register CNT counter Capture compare 1 register TI1FP1 IC1 REP register Repetition counter DTG registers DTG Output control CK_PSC CK_CNT IC1PS Stop clear or up down OC1REF CC1I C1I U UI U...

Page 896: ...enable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The gener...

Page 897: ...00 CEN Timerclock CK_CNT Counter register Update event UEV 0 Prescaler control register 1 0 Write a new value in TIMx_PSC Prescaler buffer 1 0 Prescaler counter 0 1 0 1 0 1 0 1 01 02 03 FA FB F7 F8 F9...

Page 898: ...registers Then no update event occurs until the UDIS bit has been written to 0 However the counter restarts from 0 as well as the counter of the prescaler but the prescale rate does not change In addi...

Page 899: ...ng diagram internal clock divided by 2 00 02 03 04 05 06 07 32 33 34 35 36 31 MS31078V2 CK_PSC CNT_EN Timerclock CK_CNT Counter register Update event UEV Counter overflow Update interrupt flag UIF 01...

Page 900: ...4 Figure 243 Counter timing diagram internal clock divided by N 0000 0001 0035 0036 MS31080V2 CK_PSC Timerclock CK_CNT Counter register Update event UEV Counter overflow Update interrupt flag UIF CNT_...

Page 901: ...erclock CK_CNT Counter register Update event UEV Counter overflow Update interrupt flag UIF 00 02 03 04 05 06 07 32 33 34 35 36 31 01 CEN Auto reload preload register Write a new value in TIMx_ARR MS3...

Page 902: ...aler register but also TIMx_CCRx capture compare registers in compare mode every N counter overflows where N is the value in the TIMx_RCR repetition counter register The repetition counter is decremen...

Page 903: ...er is disabled SMS 000 then the CEN in the TIMx_CR1 register and UG bits in the TIMx_EGR register are actual control bits and can be changed only by software except UG which remains cleared automatica...

Page 904: ...ected input Figure 248 TI2 external clock connection example For example to configure the upcounter to count in response to a rising edge on the TI2 input use the following procedure Internal clock Co...

Page 905: ...to be configured When a rising edge occurs on TI2 the counter counts once and the TIF flag is set The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchron...

Page 906: ...e mode controller TI1FP1 11 01 CC1S 1 0 IC1 TI2FP1 TRC from slave mode controller 10 IC1PS 0 1 TIMx_CCER CC1P TIMx_CCMR1 TI1F_Rising TI1F_Falling ICF 3 0 Edge detector TIMx_CCMR1 TIMx_CCER TI2F_Rising...

Page 907: ...lowing example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises To do this use the following procedure 1 Select the proper TI1x source internal or external with the TI1SEL 3 0...

Page 908: ...commended to read the data before the overcapture flag This is to avoid missing an overcapture which could happen after reading the flag and before reading the data Note IC interrupt and or DMA reques...

Page 909: ...n be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register In output compare mode the update event UEV has no effect on OCxREF and OCx output The timing resolutio...

Page 910: ...TIMx_EGR register OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register It can be programmed as active high or active low OCx output is enabled by a combination of the CCx...

Page 911: ...the TIMx_CCER register and the MOE OISx OISxN OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers Refer to Table 187 Output control bits for complementary OCx and OCxN channels with break featu...

Page 912: ...wing figures show the relationships between the output signals of the dead time generator and the reference signal OCxREF we suppose CCxP 0 CCxNP 0 MOE 1 CCxE 1 and CCxNE 1 in these examples Figure 25...

Page 913: ...high whereas OCxN is complemented and becomes active when OCxREF is low 27 3 11 Using the break function The purpose of the break function is to protect power switches driven by PWM signals generated...

Page 914: ...forces a Hi Z state else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high The break status flag BIF bit in the TIMx_SR register is set An interrupt can be gen...

Page 915: ...OCxN not implemented CCxP 0 OISx 0 OCx OCxN not implemented CCxP 1 OISx 1 OCx OCxN not implemented CCxP 1 OISx 0 OCx OCxN CCxE 1 CCxP 0 OISx 0 CCxNE 1 CCxNP 0 OISxN 1 OCx OCxN CCxE 1 CCxP 0 OISx 1 CCx...

Page 916: ...arity for safety purposes The break software event BG also causes the break I O to be forced to 0 to indicate to the external components that the timer has entered in break state However this is valid...

Page 917: ...bit until it is cleared by hardware when the application break condition disappears From this point the break circuitry is armed and active and the MOE bit can be set to re enable the PWM outputs Fig...

Page 918: ...counter can be controlled through the slave mode controller Generating the waveform can be done in output compare mode or PWM mode One pulse mode is selected by setting the OPM bit in the TIMx_CR1 re...

Page 919: ...er prescaler The tDELAY is defined by the value written in the TIMx_CCR1 register The tPULSE is defined by the difference between the auto reload value and the compare value TIMx_ARR TIMx_CCR1 Let s s...

Page 920: ...rupt Update Interrupt There is no latency between the assertions of the UIF and UIFCPY flags 27 3 15 Slave mode combined reset trigger mode In this case a rising edge of the selected trigger input TRG...

Page 921: ...red to CCR4 and on the second update DMA request data4 is transferred to CCR2 data5 is transferred to CCR3 and data6 is transferred to CCR4 Note A null value can be written to the reserved registers 2...

Page 922: ...division This bit field indicates the division ratio between the timer clock CK_INT frequency and the dead time and sampling clock tDTS used by the dead time generators and the digital filters TIx 00...

Page 923: ...es Res Res OIS1N OIS1 Res Res Res Res CCDS CCUS Res CCPC rw rw rw rw rw Bits 15 10 Reserved must be kept at reset value Bit 9 OIS1N Output Idle state 1 OC1N output 0 OC1N 0 after a dead time when MOE...

Page 924: ...Res Res CC1IE UIE rw rw rw rw rw rw Bits 15 10 Reserved must be kept at reset value Bit 9 CC1DE Capture Compare 1 DMA request enable 0 CC1 DMA request disabled 1 CC1 DMA request enabled Bit 8 UDE Upd...

Page 925: ...g is set by hardware on a COM event once the capture compare control bits CCxE CCxNE OCxM have been updated It is cleared by software 0 No COM event occurred 1 COM interrupt pending Bits 4 2 Reserved...

Page 926: ...ur if enabled Bit 6 Reserved must be kept at reset value Bit 5 COMG Capture Compare control update generation This bit can be set by software it is automatically cleared by hardware 0 No action 1 When...

Page 927: ...xt section The direction of a channel is defined by configuring the corresponding CCxS bits All the other bits of this register have a different function in input and in output mode Input capture mode...

Page 928: ...N 4 0011 fSAMPLING fCK_INT N 8 0100 fSAMPLING fDTS 2 N 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1010 fSAMPLING...

Page 929: ...x_CCR1 0100 Force inactive level OC1REF is forced low 0101 Force active level OC1REF is forced high 0110 PWM mode 1 Channel 1 is active as long as TIMx_CNT TIMx_CCR1 else inactive 0111 PWM mode 2 Chan...

Page 930: ...1 0 CC1S 1 0 Capture Compare 1 selection This bit field defines the direction of the channel input output as well as the used input 00 CC1 channel is configured as output 01 CC1 channel is configured...

Page 931: ...falling edge capture or trigger operations in reset external clock or trigger mode TIxFP1 is inverted trigger operation in gated mode or encoder mode CC1NP 1 CC1P 1 non inverted both edges The circuit...

Page 932: ...ty OCxN OCxREF XOR CCxNP 0 1 0 OCxREF Polarity OCx OCxREF XOR CCxP Output Disabled not driven by the timer Hi Z OCxN 0 X 1 1 OCREF Polarity dead time Complementary to OCREF not OCREF Polarity dead tim...

Page 933: ...0 16 Reserved must be kept at reset value Bits 15 0 CNT 15 0 Counter value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler v...

Page 934: ...ts counting from REP value As REP_CNT is reloaded with REP value only at the repetition update event U_RC any write to the TIMx_RCR register is not taken in account until the next repetition update ev...

Page 935: ...has been programmed LOCK bits in TIMx_BDTR register Note Any write operation to this bit takes a delay of 1 APB clock cycle to become effective Bit 27 Reserved must be kept at reset value Bit 26 BKDSR...

Page 936: ...vent enabled Note This bit cannot be modified when LOCK level 1 has been programmed LOCK bits in TIMx_BDTR register Any write operation to this bit takes a delay of 1 APB clock cycle to become effecti...

Page 937: ...n TIMx_CCER register as long as the related channel is configured in output through the CCxS bits as well as OSSR and OSSI bits can no longer be written 11 LOCK Level 3 LOCK Level 2 CC Control bits OC...

Page 938: ...r DMA transfers when read write access are done through the TIMx_DMAR address DBA is defined as an offset starting from the address of the TIMx_CR1 register Example 00000 TIMx_CR1 00001 TIMx_CR2 00010...

Page 939: ...TC wake up interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res BKCM P2P BKCM...

Page 940: ...K level 1 has been programmed LOCK bits in TIMx_BDTR register Bit 1 BKCMP1E BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input COMP1 output is ORed with the other BRK sources 0 COMP...

Page 941: ...25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res BKCM P2P BKCM P1P BKINP Res Res Res Res Res Res BKCM...

Page 942: ...OCK bits in TIMx_BDTR register Bit 1 BKCMP1E BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input COMP1 output is ORed with the other BRK sources 0 COMP1 input disabled 1 COMP1 input...

Page 943: ...Res BIF Res COMIF Res Res Res CC1IF UIF Reset value 0 0 0 0 0 0x14 TIMx_EGR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res BG Res COMG Res Res Res CC1...

Page 944: ...es Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TI1_ RMP 1 0 Reset value 0 0 0x50 TIM17_OR1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res R...

Page 945: ...ize Timeout functions with extremely low power consumption The LPTIM introduces a flexible clock scheme that provides the needed functionalities and performance while minimizing the power consumption...

Page 946: ...LPTIM2 LPTIM3 Encoder mode X External input clock X X X Wakeup from Stop 2 3 3 1 X supported 2 Wakeup supported from Stop 0 Stop 1 and Stop 2 modes 3 Wakeup supported from Stop 0 and Stop 1 modes a L...

Page 947: ...al type Description lptim_pclk Digital input LPTIM APB clock domain lptim_ker_ck Digital input LPTIM kernel clock lptim_in1 Digital input Internal LPTIM input 1 lptim_in2 Digital input Internal LPTIM...

Page 948: ...tim_ext_trig7 COMP2_OUT Table 194 LPTIM3 external trigger connection TRIGSEL External trigger lptim_ext_trig0 GPIO pin as LPTIM3_ETR alternate function lptim_ext_trig1 LPTIM1_OUT lptim_ext_trig2 LPTIM...

Page 949: ...ernal clock source or an internal one When configured to use an external clock source the CKPOL bits are used to select the external clock signal active edge If both edges are configured to be active...

Page 950: ...LPTIM inputs to consider a signal level change as a valid transition Figure 262 shows an example of glitch filter behavior in case of a 2 consecutive samples programmed Figure 262 Glitch filter timing...

Page 951: ...before setting the SNGSTRT CNTSTRT bits Any write on these bits when the timer is disabled is discarded by hardware Note When starting the counter by software TRIGEN 1 0 00 there is a delay of 3 kerne...

Page 952: ...and Set once mode activated WAVE bit is set In case of software start TRIGEN 1 0 00 the SNGSTRT setting starts the counter for one shot counting Continous mode To enable the continuous counting the CN...

Page 953: ...rts A low power timeout function can be realized The timeout value corresponds to the compare value if no trigger occurs within the expected time frame the MCU is waked up by the compare match event 2...

Page 954: ...ure 266 below shows the three possible waveforms that can be generated on the LPTIM output Also it shows the effect of the polarity change using the WAVPOL bit Figure 266 Waveform generation 28 4 11 R...

Page 955: ...d depending on CKSEL and COUNTMODE values CKSEL 0 the LPTIM is clocked by an internal clock source COUNTMODE 0 The LPTIM is configured to be clocked by an internal clock source and the LPTIM counter i...

Page 956: ...is located in the LPTIM kernel clock domain a delay of 3 clock cycles of the kernel clock is needed to synchronize the reset signal issued by the APB clock domain when writing 1 to the COUNTRST bit Th...

Page 957: ...e the Encoder mode the ENC bit has to be set to 1 The LPTIM must first be configured in Continuous mode When Encoder mode is active the LPTIM counter is modified automatically following the speed and...

Page 958: ...the content of the REP 7 0 bitfield which belongs to the repetition register LPTIM_RCR A repetition underflow event is generated on each and every LPTIM counter overflow when the REP 7 0 register is s...

Page 959: ...cycles plus three LPTIM kernel clock cycles and it is signaled by the REPOK flag located in the LPTIM_ISR register when it is elapsed When the LPTIM kernel clock cycle is relatively slow for instance...

Page 960: ...he interrupts cause the device to exit the Stop mode refer to Section 28 3 LPTIM implementation Standby The LPTIM peripheral is powered down and must be reinitialized after exiting Standby mode Table...

Page 961: ...o the REPOKCF bit in the LPTIM_ICR register Bit 7 UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated UE flag can be cleared by writing 1 to t...

Page 962: ...25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res REPOK CF UECF DOWN CF UPCF ARRO KCF CMP...

Page 963: ...ved must be kept at reset value Bit 8 REPOKIE Repetition register update OK interrupt Enable 0 Repetition register update OK interrupt disabled 1 Repetition register update OK interrupt enabled Bit 7...

Page 964: ...T 1 0 Res CKFLT 1 0 CKPOL 1 0 CKSEL rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 30 Reserved must be kept at reset value Bit 29 Reserved must be kept at reset value Bits 28 25 Reserved must be kept...

Page 965: ...rols whether the LPTIM counter is started by an external trigger or not If the external trigger option is selected three configurations are possible for the trigger active edge 00 software trigger cou...

Page 966: ...red as a valid transition 01 external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition 10 external clock signal level change must be st...

Page 967: ...ly check that COUNTRST bit is already cleared to 0 before attempting to set it to 1 Bit 2 CNTSTRT Timer start in Continuous mode This bit is set by software and cleared by hardware In case of software...

Page 968: ...Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMP 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset va...

Page 969: ...unning with an asynchronous clock reading the LPTIM_CNT register may return unreliable values So in this case it is necessary to perform two consecutive read accesses and verify that the two returned...

Page 970: ...2 Reserved must be kept at reset value Bits 1 0 OR_ 1 0 00 input 1 is connected to I O 01 input 1 is connected to COMP1_OUT 10 input 1 is connected to COMP2_OUT 11 input 1 is connected to COMP1_OUT O...

Page 971: ...PTIM_RCR register must be changed at least five counter cycles before the auto reload match event otherwise an unpredictable behavior may occur 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res...

Page 972: ...R Res Res Res Res Res Res Res ENC 1 COUNTMODE PRELOAD WAVPOL WAVE TIMOUT TRIGEN Res TRIGSEL 2 0 Res PRESC Res TRGFLT Res CKFLT CKPOL CKSEL Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x010 L...

Page 973: ...Res OR_1 OR_0 Reset value 0 0 0x028 LPTIM_RCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res REP 7 0 Reset value 0 0 0 0 0 0 0 0 1 If LPTIM does not s...

Page 974: ...through a basic input capture mode Figure 269 IRTIM internal hardware connections with TIM16 and TIM17 All standard IR pulse modulation modes can be obtained by programming the two timer output compa...

Page 975: ...her information on the window watchdog refer to Section 31 on page 984 30 2 IWDG main features Free running downcounter Clocked from an independent RC oscillator can operate in Standby and Stop modes...

Page 976: ...ue and ease the cycle number calculation to generate the next reload Configuring the IWDG when the window option is enabled 1 Enable the IWDG by writing 0x0000 CCCC in the IWDG key register IWDG_KR 2...

Page 977: ...m this mode Refer to User and read protection option bytes for more details 30 3 5 Register access protection Write access to IWDG prescaler register IWDG_PR IWDG reload register IWDG_RLR and IWDG win...

Page 978: ...Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w w w w w w w w w w w w w w w w Bits 31 16 Reserved must be kept at reset value Bits 15 0 KEY 15 0 Key value wri...

Page 979: ...rotected see Section 30 3 5 Register access protection They are written by software to select the prescaler divider feeding the counter clock PVU bit of the IWDG status register IWDG_SR must be reset...

Page 980: ...on They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG key register IWDG_KR The watchdog counter counts down from th...

Page 981: ...Res Res Res Res Res Res Res WVU RVU PVU r r r Bits 31 3 Reserved must be kept at reset value Bit 2 WVU Watchdog counter window value update This bit is set by hardware to indicate that an update of th...

Page 982: ...ue These bits are write access protected see Section 30 3 5 they contain the high limit of the window value to be compared with the downcounter To prevent a reset the downcounter must be reloaded when...

Page 983: ...KEY 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 IWDG_PR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PR 2 0 Reset valu...

Page 984: ...uited for applications which require the watchdog to react within an accurate timing window 31 2 WWDG main features Programmable free running down counter Conditional reset Reset if watchdog activated...

Page 985: ...hdog produces a reset The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register see Figure 272 The WWDG configuration regi...

Page 986: ...he WWDG_CR register always write 1 in the T6 bit to avoid generating an immediate reset Figure 272 Window watchdog timing diagram The formula to calculate the timeout value is given by where tWWDG WWD...

Page 987: ...ions or data logging before resetting the device In some applications the EWI interrupt can be used to manage a software system check and or system recovery graceful degradation without generating a W...

Page 988: ...0 9 8 7 6 5 4 3 2 1 0 Res Res WDGTB 2 0 Res EWI Res Res W 6 0 rw rw rw rs rw rw rw rw rw rw rw Bits 31 14 Reserved must be kept at reset value Bits 13 11 WDGTB 2 0 Timer base The timebase of the presc...

Page 989: ...lag This bit is set by hardware when the counter has reached the value 0x40 It must be cleared by software by writing 0 Writing 1 has no effect This bit is also set if the interrupt is not enabled Tab...

Page 990: ...detection a more precise second source clock 50 or 60 Hz can be used to enhance the calendar precision Digital calibration circuit with 0 95 ppm resolution to compensate for quartz crystal inaccuracy...

Page 991: ...TC_OUT2 TAMP TAMPOE Shadow register RTC_SSR Calendar Synchronous prescaler default 256 RTC_PRER CALIB OSEL 1 0 ck_apre default 256 Hz TAMPALARM ALARM rtc_tamp_evt RTC_REFIN RTC_TS Time stamp registers...

Page 992: ...fer to Section 32 4 RTC low power modes for more details Table 207 RTC input output pins Pin name Signal type Description RTC_TS Input RTC timestamp input RTC_REFIN Input RTC 50 or 60 Hz reference clo...

Page 993: ...and TAMP functions mapped on PC13 are available in all low power modes and in VBAT mode The output mechanism follows the priority order shown in Table 210 Table 209 RTC interconnection Signal name Sou...

Page 994: ...are TAMP_IN1 input floating 00 0 0 Don t care Don t care Don t care 1 0 00 0 1 1 Don t care Don t care 0 RTC_TS and TAMP_IN1 input floating 00 0 0 Don t care Don t care Don t care 1 1 00 0 1 1 Don t c...

Page 995: ...ation refer to Reset and clock control RCC Wakeup pin or Standard GPIO 00 0 0 Don t care Don t care Don t care 0 0 00 0 1 1 Don t care Don t care 0 1 OD open drain PP push pull 2 In this configuration...

Page 996: ...nary RTC_SSR subseconds downcounter When it reaches 0 RTC_SSR is reloaded with the content of PREDIV_S fck_spre is given by the following formula The ck_spre clock can be used either to update the cal...

Page 997: ...D 0 mode the frequency of the APB clock fAPB must be at least 7 times the frequency of the RTC clock fRTCCLK The shadow registers are reset by system reset 32 3 6 Calendar ultra low power mode It is p...

Page 998: ...from 1 s to around 36 hours with one second resolution This large programmable time range is divided in 2 parts from 1 s to 18 hours when WUCKSEL 2 1 10 and from around 18 h to 36 h when WUCKSEL 2 1 1...

Page 999: ...when BYPSHAD 0 RTC register write protection After system reset the RTC registers are protected against parasitic write access by the DBP bit in the power control peripheral refer to the PWR power co...

Page 1000: ...a 32768 Hz clock is obtained with PREDIV_S set to 0x7FFF However increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler output at 1 Hz In this way th...

Page 1001: ...RTC clock frequency fRTCCLK This ensures a secure behavior of the synchronization mechanism If the APB1 clock frequency is less than seven times the RTC clock frequency the software must read the cale...

Page 1002: ...RTC The calendar shadow registers RTC_SSR RTC_TR and RTC_DR and some bits of the RTC status register RTC_ICSR are reset to their default values by all available system reset sources On the contrary t...

Page 1003: ...RTC_CR set to 1 the calendar is still clocked by the LSE and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency 1 Hz Each 1 Hz clock edge is compared to the nearest...

Page 1004: ...ifies the number of ck_cal clock cycles to be masked during the calibration cycle Setting the bit CALM 0 to 1 causes exactly one pulse to be masked during the calibration cycle Setting CALM 1 to 1 cau...

Page 1005: ...If PREDIV_S is reduced in this way the formula given the effective frequency of the calibrated input clock is as follows FCAL FRTCCLK x 1 256 CALM 220 CALM 256 In this case CALM 7 0 equals 0x100 the...

Page 1006: ...C_CR register to 1 When TSE is set The calendar is saved in the timestamp registers RTC_TSSSR RTC_TSTR RTC_TSDR when a timestamp event is detected on the RTC_TS pin When TAMPTS is set The calendar is...

Page 1007: ...f the 6th stage of the asynchronous prescaler If LPCAL is changed from 0 to 1 the output can be irregular glitch during the LPCAL switch If LPCAL 1 this output is always available If LPCAL 0 no output...

Page 1008: ...rupts cause the device to exit the Stop mode Standby The RTC remains active when the RTC clock source is LSE or LSI RTC interrupts cause the device to exit the Standby mode Shutdown The RTC remains ac...

Page 1009: ...RAIE write 1 in CALRAF Yes Yes 3 Yes 4 Alarm B ALRBF ALRBIE write 1 in CALRBF Yes Yes 3 Yes 4 Timestamp TSF TSIE write 1 in CTSF Yes Yes 3 Yes 4 Wakeup timer interrupt WUTF WUTIE write 1 in CWUTF Yes...

Page 1010: ...set 0x00 Backup domain reset value 0x0000 0000 System reset value 0x0000 0000 when BYPSHAD 0 Not affected when BYPSHAD 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res...

Page 1011: ...YPSHAD 1 Note The calendar is frozen when reaching the maximum value and can t roll over 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res YT 3 0 YU 3 0 rw rw rw rw rw rw...

Page 1012: ...unter MSB values When Binary or Mixed mode is selected BIN 01 or 10 or 11 SS 31 16 are the 16 MSB of the SS 31 0 free running down counter When BCD mode is selected BIN 00 SS 31 16 are forced by hardw...

Page 1013: ...ode Binary mode disabled 01 Free running Binary mode BCD mode disabled 10 Free running BCD calendar and Binary modes 11 Free running BCD calendar and Binary modes Bit 7 INIT Initialization mode 0 Free...

Page 1014: ...A shift operation is pending Bit 2 WUTWF Wakeup timer write flag This bit is set by hardware when WUT value can be changed after the WUTE bit has been set to 0 in RTC_CR It is cleared by hardware in i...

Page 1015: ...ardware when the auto reload downcounter reaches WUTOCLR 15 0 When WUTOCLR 15 0 0x0000 WUTF is set by hardware when the WUT down counter reaches 0 and is cleared by software Bits 15 0 WUT 15 0 Wakeup...

Page 1016: ...and with the polarity provided by POL Bit 25 TAMPTS Activate timestamp on tamper detection event 0 Tamper detection event does not cause a RTC timestamp to be saved 1 Save RTC timestamp on tamper det...

Page 1017: ...tracts 1 hour to the current time This can be used for winter time change Bit 16 ADD1H Add 1 hour summer time change When this bit is set outside initialization mode 1 hour is added to the calendar ti...

Page 1018: ...cycles 1 Calendar values when reading from RTC_SSR RTC_TR and RTC_DR are taken directly from the calendar counters Note If the frequency of the APB1 clock is less than seven times the frequency of RTC...

Page 1019: ...es Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res KEY 7 0 w w w w w w w w Bits 31 8 Reserved must be kept at reset value Bits...

Page 1020: ...TC smooth digital calibration Bit 13 CALW16 Use a 16 second calibration cycle period When CALW16 is set to 1 the 16 second calibration cycle period is selected This bit must not be set to 1 if CALW8 1...

Page 1021: ...added to the synchronous prescaler counter Since this counter counts down this operation effectively subtracts from delays the clock by Delay seconds SUBFS PREDIV_S 1 A fraction of a second can effec...

Page 1022: ...reset value Bits 6 4 ST 2 0 Second tens in BCD format Bits 3 0 SU 3 0 Second units in BCD format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Re...

Page 1023: ...3 0 MSK1 ST 2 0 SU 3 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 MSK4 Alarm A date mask 0 Alarm A set if the date day match 1 Date day don t care in alarm A comparison Bit 30 WDSEL Week d...

Page 1024: ...FFFF when reaching RTC_ALRMABINR SS 31 0 Note SSCLR must be kept to 0 when BCD or mixed mode is used BIN 00 10 or 11 Bit 30 Reserved must be kept at reset value Bits 29 24 MASKSS 5 0 Mask the most si...

Page 1025: ...arison Bit 30 WDSEL Week day selection 0 DU 3 0 represents the date units 1 DU 3 0 represents the week day DT 1 0 is don t care Bits 29 28 DT 1 0 Date tens in BCD format Bits 27 24 DU 3 0 Date units o...

Page 1026: ...ode is used BIN 00 10 or 11 Bit 30 Reserved must be kept at reset value Bits 29 24 MASKSS 5 0 Mask the most significant bits starting at this bit 0 No comparison on sub seconds for Alarm B The alarm i...

Page 1027: ...t by hardware when a timestamp event occurs while TSF is already set It is recommended to check and then clear TSOVF only after clearing the TSF bit Otherwise an overflow might not be noticed if a tim...

Page 1028: ...rs and timestampinterrupt is raised Bit 4 TSOVMF Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set It is recommended to check and...

Page 1029: ...this bit clears the ITSF bit in the RTC_SR register Bit 4 CTSOVF Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register It is recommended to check and then cl...

Page 1030: ...rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 SS 31 0 Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is...

Page 1031: ...alue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x18 RTC_CR OUT2EN TAMPALRM_TYPE TAMPALRM_PU Res Res TAMPOE TAMPTS ITSE COE O SEL 1 0 POL COSEL BKP SUB1H ADD1H TSIE WUTIE ALRBIE A...

Page 1032: ...0 0 0 0 0 0 0 0 0 0 0 0 0x50 RTC_SR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res SSRUF ITSF TSOVF TSF WUTF ALRBF ALRAF Reset value 0 0 0 0 0 0 0...

Page 1033: ...er detection The external tamper pins can be configured for edge detection or level detection with or without filtering 33 2 TAMP main features 20 backup registers the backup registers TAMP_BKPxR are...

Page 1034: ...n EDGE detection LEVEL detection TAMP2F Tamper detection EDGE detection LEVEL detection TAMPxF 1 Tamper detection EDGE detection LEVEL detection Backup registers tamp_it tamp_erase tamp_ker_ck tamp_ke...

Page 1035: ...k connected to rtc_pclk tamp_itamp y y signal index Inputs Internal tamper event sources tamp_evt Output Tamper event detection internal or external The tamp_evt is used to generate a RTC timestamp ev...

Page 1036: ...crets erased by tamp_erase signal refer to Table 218 TAMP interconnection can be reset by software by setting the BKERASE bit in the TAMP_CR2 register Note The backup registers are also erased when th...

Page 1037: ...s selected Caution When using the edge detection it is recommended to check by software the tamper pin level just after enabling the tamper detection by reading the GPIO registers and before writing s...

Page 1038: ...lock source is LSE or LSI Tamper events cause the device to exit the Standby mode Shutdown No effect on all features except for level detection with filtering mode which remain active only when the cl...

Page 1039: ...4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res TAMP3 E TAMP2 E TAMP1 E rw rw rw Bits 31 24 Reserved must be kept at reset value Bit 23 ITAMP8E Internal tamper 8 enable 0 Internal tampe...

Page 1040: ...26 TAMP3TRG Active level for tamper 3 input 0 If TAMPFLT 00 Tamper 3 input staying low triggers a tamper detection event If TAMPFLT 00 Tamper 3 input rising edge and high level triggers a tamper dete...

Page 1041: ...ed The tamper 2 interrupt must not be enabled when TAMP2MSK is set Bit 16 TAMP1MSK Tamper 1 mask 0 Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper...

Page 1042: ...erase the backup registers 1 Bit 3 Reserved must be kept at reset value Bit 2 ITAMP3NOER Internal Tamper 3 no erase 0 Internal Tamper 3 event erases the backup registers 1 Internal Tamper 3 event doe...

Page 1043: ...ples at the active level 0x2 Tamper event is activated after 4 consecutive samples at the active level 0x3 Tamper event is activated after 8 consecutive samples at the active level Bits 2 0 TAMPFREQ 2...

Page 1044: ...served must be kept at reset value Bits 15 3 Reserved must be kept at reset value Bit 2 TAMP3IE Tamper 3 interrupt enable 0 Tamper 3 interrupt disabled 1 Tamper 3 interrupt enabled Bit 1 TAMP2IE Tampe...

Page 1045: ...t is detected on the TAMP3 input Bit 1 TAMP2F TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input Bit 0 TAMP1F TAMP1 detection flag This flag...

Page 1046: ...24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res C ITAMP 8F Res C ITAMP 6F C ITAMP 5F Res C ITAMP 3F Res Res w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res...

Page 1047: ...ection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register Bit 1 CTAMP2F Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register Bit 0 CTAMP...

Page 1048: ...is done to this register This register cannot roll over and is frozen when reaching the maximum value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BKP 31 16 rw rw rw rw rw rw rw rw rw rw rw rw rw r...

Page 1049: ...es Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TAMPPUDIS TAMPPRCH 1 0 TAMPFLT 1 0 TAMPFREQ 2 0 Reset value 0 0 0 0 0 0 0 0 0x2C TAMP_IER Res Res Res Res Res Res Res Res ITAMP8IE Res IT...

Page 1050: ...so SMBus system management bus and PMBus power management bus compatible DMA can be used to reduce CPU overload 34 2 I2C main features I2C bus specification rev03 compatibility Slave and master modes...

Page 1051: ...C2 and I2C3 with full or limited feature sets as shown in the following table 34 4 I2C functional description In addition to receiving and transmitting data this interface converts it from serial to p...

Page 1052: ...e 275 Figure 275 I2C block diagram The I2C is clocked by an independent clock source which allows the I2C to operate independently from the PCLK frequency MSv46198V2 I2CCLK Wakeup on address match SMB...

Page 1053: ...Analog filter delay is maximum 260 ns Digital filter delay is DNF x tI2CCLK The PCLK clock period tPCLK must respect the following condition tPCLK 4 3 tSCL with tSCL SCL period Caution When the I2C k...

Page 1054: ...own addresses 7 or 10 bit and the general call address The general call address detection can be enabled or disabled by software The reserved SMBus addresses can also be enabled by software Data and a...

Page 1055: ...d or select a digital filter by configuring the DNF 3 0 bit in the I2C_CR1 register When the digital filter is enabled the level of the SCL or the SDA line is internally changed only if it remains sta...

Page 1056: ...OLD TIME tHD DAT SCLDEL SCL stretched low by the I2C SCL SDA DATA SETUP TIME tSU STA Data hold time in case of transmission the data is sent on SDA output after the SDADEL delay if it is already avail...

Page 1057: ...stretch the LOW period tLOW of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock The SDA rising edge is usually the worst case so in...

Page 1058: ...ed a delay is inserted before releasing the SCL output This delay is tSCLL SCLL 1 x tPRESC where tPRESC PRESC 1 x tI2CCLK tSCLL impacts the SCL low time tLOW When the SCL rising edge is internally det...

Page 1059: ...ed register bits 1 I2C_CR2 register START STOP NACK 2 I2C_ISR register BUSY TXE TXIS RXNE ADDR NACKF TCR TC STOPF BERR ARLO OVR and in addition when the SMBus feature is supported 1 I2C_CR2 register P...

Page 1060: ...ata byte is received the shift register is copied into I2C_RXDR register if it is empty RXNE 0 If RXNE 1 meaning that the previous received data byte has not yet been read the SCL line is stretched lo...

Page 1061: ...s always used in master mode By default it is disabled in slave mode but it can be enabled by software by setting the SBC Slave Byte Control bit in the I2C_CR2 register The number of bytes to be trans...

Page 1062: ...e by setting the OA1MODE bit in the I2C_OAR1 register OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register If additional slave addresses are required the 2nd slave address OA2 can be confi...

Page 1063: ...his stretch is released when I2C_RXDR is read When TCR 1 in Slave Byte Control mode reload mode SBC 1 and RELOAD 1 meaning that the last data byte has been transferred This stretch is released when th...

Page 1064: ...it or not by configuring the ACK bit in the I2C_CR2 register The SCL stretch is released by programming NBYTES to a non zero value the acknowledge or not acknowledge is sent and next byte can be rece...

Page 1065: ...etting the TXE bit in order to program a new data byte In Slave byte control mode SBC 1 the number of bytes to be transmitted must be programmed in NBYTES in the address match interrupt subroutine ADD...

Page 1066: ...82 Transfer sequence flowchart for I2C slave transmitter NOSTRETCH 0 MS19851V2 Slave initialization Slave transmission Read ADDCODE and DIR in I2C_ISR Optional Set I2C_ISR TXE 1 Set I2C_ICR ADDRCF Wri...

Page 1067: ...ce 1117 Figure 283 Transfer sequence flowchart for I2C slave transmitter NOSTRETCH 1 MS19852V2 Slave initialization Slave transmission Optional Set I2C_ISR TXE 1 and I2C_ISR TXIS 1 Write I2C_TXDR TXDA...

Page 1068: ...I2C slave transmitter 3 bytes NOSTRETCH 1 EV1 wr data1 EV2 TXIS ISR wr data2 EV3 TXIS ISR wr data3 EV4 TXIS ISR wr data4 not sent EV5 STOPF ISR optional set TXE and TXIS set STOPCF A TXIS TXIS TXE leg...

Page 1069: ...E is cleared when I2C_RXDR is read When a STOP is received and STOPIE is set in I2C_CR1 STOPF is set in I2C_ISR and an interrupt is generated Figure 285 Transfer sequence flowchart for slave receiver...

Page 1070: ...857V2 EV1 ADDR ISR check ADDCODE and DIR set ADDRCF EV2 RXNE ISR rd data1 EV3 RXNE ISR rd data2 EV4 RXNE ISR rd data3 A ADDR A A RXNE A RXNE RXNE legend transmission reception SCL stretch EV1 EV2 EV3...

Page 1071: ...ion to the I2CxCLK clock The I2C releases SCL to high level once the SCLL counter reaches the value programmed in the SCLL 7 0 bits in the I2C_TIMINGR register The I2C detects its own SCL high level a...

Page 1072: ...SCLH SCL SCL master clock generation SCL released SCL low level detected SCLL counter starts SCL driven low SCLL tSYNC2 SCL master clock synchronization SCLL SCL driven low by another device SCL low...

Page 1073: ...er automatically sends the START condition followed by the slave address as soon as it detects that the bus is free BUSY 0 and after a delay of tBUF In case of an arbitration loss the master automatic...

Page 1074: ...ization of a master receiver addressing a 10 bit address slave If the slave address is in 10 bit format the user can choose to send the complete read sequence by clearing the HEAD10R bit in the I2C_CR...

Page 1075: ...case when NBYTES data have been transferred the TCR flag is set and the SCL line is stretched low until NBYTES 7 0 is written to a non zero value The TXIS flag is not set when a NACK is received When...

Page 1076: ...transmitter for N 255 bytes MS19860V2 Master initialization Master transmission Write I2C_TXDR I2C_ISR TXIS 1 No Yes I2C_ISR NACKF 1 Yes No NBYTES N AUTOEND 0 for RESTART 1 for STOP Configure slave a...

Page 1077: ...tialization Master transmission Write I2C_TXDR I2C_ISR TXIS 1 No Yes I2C_ISR NACKF 1 Yes No NBYTES 0xFF N N 255 RELOAD 1 Configure slave address Set I2C_CR2 START End NBYTES transmitted I2C_ISR TC 1 Y...

Page 1078: ...TXIS ISR wr data2 TXIS TXIS legend transmission reception SCL stretch EV1 EV2 xx 2 INIT Example I2C master transmitter 2 bytes software end mode RESTART INIT program Slave address program NBYTES 2 AU...

Page 1079: ...en to a non zero value When RELOAD 0 and NBYTES 7 0 data have been transferred In automatic end mode AUTOEND 1 a NACK and a STOP are automatically sent after the last received byte In software end mod...

Page 1080: ...hart for I2C master receiver for N 255 bytes MS19863V2 Master initialization Master reception Read I2C_RXDR I2C_ISR RXNE 1 No Yes NBYTES N AUTOEND 0 for RESTART 1 for STOP Configure slave address Set...

Page 1081: ...4V2 Master initialization Master reception Read I2C_RXDR I2C_ISR RXNE 1 No Yes NBYTES 0xFF N N 255 RELOAD 1 Configure slave address Set I2C_CR2 START NBYTES received I2C_ISR TC 1 Yes End No Yes No Set...

Page 1082: ...V2 RXNE ISR rd data2 A RXNE RXNE NBYTES legend transmission reception SCL stretch EV1 xx 2 INIT Example I2C master receiver 2 bytes software end mode RESTART INIT program Slave address program NBYTES...

Page 1083: ...s 2 x 125 ns 250 ns 1 SCL period tSCL is greater than tSCLL tSCLH due to SCL internal detection delay Values provided for tSCL are examples only 2 tSYNC1 tSYNC2 minimum value is 4 x tI2CCLK 500 ns Exa...

Page 1084: ...may use any or all of the eleven protocols to communicate The protocols are Quick Command Send Byte Receive Byte Write Byte Write Word Read Byte Read Word Process Call Block Read Block Write and Block...

Page 1085: ...N bit in the I2C_CR1 register The Alert Response Address is enabled at the same time When configured as a host SMBHEN 1 the ALERT flag is set in the I2C_ISR register when a falling edge is detected on...

Page 1086: ...ter than tLOW SEXT Therefore this parameter is measured with the slave device as the sole target of a full speed master 2 tLOW MEXT is the cumulative time a master device is allowed to extend its cloc...

Page 1087: ...lave mode the Slave byte control mode must be enabled by setting the SBC bit in the I2C_CR1 register Refer to Slave byte control mode on page 1064 for more details Specific address Slave mode The spec...

Page 1088: ...tLOW MEXT for a master As the standard specifies only a maximum the user can choose the same value for the both Then the timer is enabled by setting the TEXTEN bit in the I2C_TIMEOUTR register If the...

Page 1089: ...rogrammed to 1 in order to allow the PEC transmission at the end of the programmed number of data bytes When the PECBYTE bit is set the number of bytes programmed in NBYTES 7 0 includes the PEC transm...

Page 1090: ...2 Slave initialization SMBus slave transmission Write I2C_TXDR TXDATA I2C_ISR TXIS 1 No Yes I2C_ISR ADDR 1 Yes No Read ADDCODE and DIR in I2C_ISR I2C_CR2 NBYTES N 1 PECBYTE 1 Set I2C_ICR ADDRCF SCL st...

Page 1091: ...red with the internal I2C_PECR register content A NACK is automatically generated if the comparison does not match and an ACK is automatically generated if the comparison matches whatever the ACK bit...

Page 1092: ...ation SMBus slave reception Read I2C_RXDR RXDATA I2C_ISR RXNE 1 I2C_ISR TCR 1 No Yes I2C_ISR ADDR 1 Yes No Read ADDCODE and DIR in I2C_ISR I2C_CR2 NBYTES 1 RELOAD 1 PECBYTE 1 Set I2C_ICR ADDRCF SCL st...

Page 1093: ...cally transmitted If the SMBus master wants to send a STOP condition after the PEC automatic end mode must be selected AUTOEND 1 In this case the STOP condition automatically follows the PEC transmiss...

Page 1094: ...SMBus master transmitter MS19871V2 Example SMBus master transmitter 2 bytes PEC automatic end mode STOP Address S INIT program Slave address program NBYTES 3 AUTOEND 1 set PECBYTE set START EV1 TXIS I...

Page 1095: ...CK response is given to the PEC byte followed by a STOP condition When the SMBus master receiver wants to receive the PEC byte followed by a RESTART condition at the end of the transfer software mode...

Page 1096: ...ISR rd PEC A data1 A RXNE RXNE data2 A NBYTES NA legend transmission reception SCL stretch 3 V E 1 V E xx 3 INIT Example SMBus master receiver 2 bytes PEC software end mode RESTART Address S INIT prog...

Page 1097: ...a master or as an addressed slave after the ADDR flag is set This can be managed by clearing SLEEPDEEP bit in the ADDR interrupt routine and setting it again only after the STOPF flag is set Caution...

Page 1098: ...E 0 0xFF if not When a new byte must be sent and the I2C_TXDR register has not been written yet 0xFF is sent When an overrun or underrun error is detected the OVR flag is set in the I2C_ISR register a...

Page 1099: ...n master mode the initialization the slave address direction number of bytes and START bit are programmed by software the transmitted slave address cannot be transferred with DMA When all data are tra...

Page 1100: ...ops depending on the DBG_I2Cx_ configuration bits in the DBG module 34 5 I2C low power modes Table 236 Effect of low power modes on the I2C Mode Description Sleep No effect I2C interrupts cause the de...

Page 1101: ...C_TXDR register Stop detection interrupt flag STOPF STOPIE Write STOPCF 1 Transfer complete reload TCR TCIE Write I2C_CR2 with NBYTES 7 0 0 Transfer complete TC Write START 1 or STOP 1 Address matched...

Page 1102: ...upported this bit is reserved and forced by hardware to 0 Refer to Section 34 3 I2C implementation Bit 22 ALERTEN SMBus alert enable 0 The SMBus alert pin SMBA is not supported in host mode SMBHEN 1 I...

Page 1103: ...control in slave mode 0 Slave byte control disabled 1 Slave byte control enabled Bit 15 RXDMAEN DMA reception requests enable 0 DMA mode disabled for reception 1 DMA mode enabled for reception Bit 14...

Page 1104: ...ble 0 Stop detection STOPF interrupt disabled 1 Stop detection STOPF interrupt enabled Bit 4 NACKIE Not acknowledge received Interrupt enable 0 Not acknowledge NACKF received interrupts disabled 1 Not...

Page 1105: ...1 PEC transmission reception is requested Note Writing 0 to this bit has no effect This bit has no effect when RELOAD is set This bit has no effect is slave mode when SBC 0 If the SMBus feature is no...

Page 1106: ...ddress sequence is sent by an arbitration loss by an address matched in slave mode by a timeout error detection or when PE 0 0 No Start generation 1 Restart Start generation If the I2C is already in m...

Page 1107: ...hen the START bit is set is not allowed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OA1EN Res...

Page 1108: ...address 2 enabled The received slave address OA2 is ACKed Bits 14 11 Reserved must be kept at reset value Bits 10 8 OA2MSK 2 0 Own Address 2 masks 000 No mask 001 OA2 1 is masked and don t care Only...

Page 1109: ...on page 1071 tPRESC PRESC 1 x tI2CCLK Bits 27 24 Reserved must be kept at reset value Bits 23 20 SCLDEL 3 0 Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL ris...

Page 1110: ...a timeout error is detected TIMEOUT 1 Bits 30 28 Reserved must be kept at reset value Bits 27 16 TIMEOUTB 11 0 Bus timeout B This field is used to configure the cumulative clock extension timeout In m...

Page 1111: ...ve enters receiver mode 1 Read transfer slave enters transmitter mode Bit 15 BUSY Bus busy This flag indicates that a communication is in progress on the bus It is set by hardware when a START conditi...

Page 1112: ...sfer Complete Reload This flag is set by hardware when RELOAD 1 and NBYTES data have been transferred It is cleared by software when NBYTES is written to a non zero value Note This bit is cleared by h...

Page 1113: ...next data to be sent is written in the I2C_TXDR register This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR Note This bit is set by hardware when PE 0 31 3...

Page 1114: ...t be kept at reset value Bit 5 STOPCF STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register Bit 4 NACKCF Not Acknowledge flag clear Writing 1 to this bit clears...

Page 1115: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res RXDATA 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 RXDATA 7 0 8 bit receive data Data byte received fro...

Page 1116: ...s Res Res Res Res Res Res Res Res OA2EN Res Res Res Res OA2MS K 2 0 OA2 7 1 Res Reset value 0 0 0 0 0 0 0 0 0 0 0 0x10 I2C_ TIMINGR PRESC 3 0 Res Res Res Res SCLDEL 3 0 SDADEL 3 0 SCLH 7 0 SCLL 7 0 Re...

Page 1117: ...ndary addresses 0x28 I2C_TXDR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TXDATA 7 0 Reset value 0 0 0 0 0 0 0 0 Table 238 I2C register map and rese...

Page 1118: ...equipments requiring an industry standard NRZ asynchronous serial data format A very wide range of baud rates can be achieved through a fractional baud rate generator The USART supports both synchron...

Page 1119: ...bits Programmable data order with MSB first or LSB first shifting Configurable stop bits 1 or 2 stop bits Synchronous master slave mode and clock output input for synchronous communications SPI slave...

Page 1120: ...ature CR LF character recognition 35 4 USART implementation The table below describes USART implementation on STM32WL5x devices It also includes LPUART for comparison Table 239 USART LPUART features U...

Page 1121: ...he usart_ker_ck clock is stopped When the dual clock domain feature is disabled the usart_ker_ck clock is the same as the usart_pclk clock There is no constraint between usart_pclk and usart_ker_ck us...

Page 1122: ...to transmit and receive data RS232 Hardware flow control mode The following pins are required in RS232 Hardware flow control mode CTS Clear To Send When driven high this signal blocks the data transmi...

Page 1123: ...gth M 1 0 01 Note In 7 bit data length mode the Smartcard mode LIN master mode and Auto baud rate 0x7F and 0x55 frames detection are not supported By default the signal TX or RX is in low state during...

Page 1124: ...ta frame Clock Start bit Stop bit Start bit Stop bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Start bit Stop bit Next Start bit Idle frame 8 bit word length M 00 1 Stop bit Possible Parity bit Break fr...

Page 1125: ...This means that the RXFIFO is filled until the number of data in the RXFIFO is equal to the programmed threshold RXFTCFG data have been received one data in USART_RDR and RXFTCFG 1 data in the RXFIFO...

Page 1126: ...12 1 stop bit This is the default value of number of stop bits 2 stop bits This is supported by normal USART Single wire and Modem modes 1 5 stop bits To be used in Smartcard mode An idle frame transm...

Page 1127: ...RT_CR1 to send an idle frame as first transmission 7 Write the data to send in the USART_TDR register Repeat this for each data to be transmitted in case of single buffer When FIFO mode is disabled wr...

Page 1128: ...rdware to indicate that the TXFIFO is not full the USART_TDR register is empty the next data can be written to the USART_TDR register without overwriting the previous data When a transmission is ongoi...

Page 1129: ...current transmission When FIFO mode is enabled sending the break character has priority on sending data even if the TXFIFO is full Idle characters Setting the TE bit drives the USART to send an idle...

Page 1130: ...at 0 The start bit is validated but the NE noise flag is set if a for both samplings 2 out of the 3 sampled bits are at 0 sampling on the 3rd 5th and 7th bits and sampling on the 8th 9th and 10th bit...

Page 1131: ...ith the corresponding error bits An interrupt is generated if the RXNEIE RXFNEIE when FIFO mode is enabled bit is set The error flags can be set if a frame error noise parity or an overrun error was d...

Page 1132: ...during overrun is lost an interrupt is generated if either the RXNEIE or the EIE bit is set FIFO mode enabled An overrun error occurs when the shift register is ready to be transferred and the receive...

Page 1133: ...when needed in order to transfer the received data by performing a software read to the USART_RDR register or by DMA For the other clock sources the system must be active to enable USART communicatio...

Page 1134: ...se the receiver tolerance to clock deviations see Section 35 5 8 Tolerance of the USART receiver to clock deviation on page 1137 In this case the NE bit is never set When noise is detected in a frame...

Page 1135: ...FIFO mode is enabled no interrupt is generated in case of single byte communication However this bit rises at the same time as the RXNE bit RXFNE in case FIFO mode is enabled which itself generates a...

Page 1136: ...bits is done on the 16th 17th and 18th samples 1 baud clock period after the beginning of the stop bit The 1 5 stop bit can be broken into 2 parts one 0 5 baud clock period during which nothing happen...

Page 1137: ...ual to 16 How to derive USARTDIV from USART_BRR register values Example 1 To obtain 9600 baud with usart_ker_ck_pres 8 MHz In case of oversampling by 16 USARTDIV 8 000 000 9600 BRR USARTDIV 0d833 0x03...

Page 1138: ...of the start bit falling edge and the instant when the clock requested by the peripheral is ready and reaching the peripheral and the regulator is ready The USART receiver can receive data correctly a...

Page 1139: ...o be obtained without measuring the clock deviation The clock source frequency must be compatible with the expected communication speed When oversampling by 16 the baud rate ranges from usart_ker_ck_p...

Page 1140: ...tly synchronized with the receiver the receiver being based on the baud rate calculated on bit 0 Prior to activating the auto baud rate detection the USART_BRR register must be initialized by writing...

Page 1141: ...USART_CR1 register Note When FIFO management is enabled and MME is already set MME bit must not be cleared and then set again quickly within two usart_ker_ck cycles otherwise Mute mode might remain ac...

Page 1142: ...ART enters Mute mode when an address character is received which does not match its programmed address In this case the RWU bit is set by hardware The RXNE flag is not set for this address byte and no...

Page 1143: ...SART_CR2 register and the RTOIE in the USART_CR1 register The value corresponding to a timeout of 2 character times for example 22 x bit time must be programmed in the RTO register When the receive li...

Page 1144: ...parity bit As an example if data 00110101 and 4 bits set then the parity bit is equal to 1 if odd parity is selected PS bit in USART_CR1 1 Parity checking in reception If the parity check fails the PE...

Page 1145: ...al The method for detecting start bits is the same when searching break characters or data After a start bit has been detected the circuit samples the next bits exactly like for the data on the 8th 9t...

Page 1146: ...ne Capture strobe Break state machine Read samples Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 B10 Idle 0 0 0 0 0 0 0 0 0 0 0 Case 2 break signal just long enough break detected LBDF is set...

Page 1147: ...SART_CR2 register is used to select the clock polarity and the CPHA bit in the USART_CR2 register is used to select the phase of the external clock see Figure 317 Figure 318 and Figure 319 During the...

Page 1148: ...transmitting data Figure 317 USART example of synchronous master transmission Figure 318 USART data clock timing diagram in synchronous master mode M bits 00 MSv31158V2 USART Synchronous device slave...

Page 1149: ...the frequency of peripheral clock source usart_ker_ck_pres must be greater than 3 times the CK input frequency The CPOL bit and the CPHA bit in the USART_CR2 register are used to select the clock pol...

Page 1150: ...ting the master communications or between frames while the clock is stable Otherwise if the USART slave is enabled while the master is in the middle of a frame it becomes desynchronized with the maste...

Page 1151: ...made with a control bit HDSEL in USART_CR3 As soon as HDSEL is written to 1 The TX and RX lines are internally connected The RX pin is no longer used The TX pin is always released when no data is tran...

Page 1152: ...the guard time period Figure 321 shows examples of what can be seen on the data line with and without parity error Figure 321 ISO 7816 3 asynchronous protocol When connected to a Smartcard the TX outp...

Page 1153: ...the Guard Time as programmed in the Guard Time register between two successive characters As the Guard Time is measured after the stop bit of the previous character the GT 7 0 register must be progra...

Page 1154: ...parallel the DMA must be enabled only after the first received byte After the reception of the first character RXNE RXFNE interrupt the RTO register must be programmed to the CWT character wait time 1...

Page 1155: ...to use this convention the following control bits must be programmed MSBFIRST 0 DATAINV 0 default values The inverse convention is defined as MSB first logical bit value 1 corresponds to an L state o...

Page 1156: ...18 USART IrDA SIR ENDEC block This section is relevant only when IrDA mode is supported Refer to Section 35 4 USART implementation on page 1120 IrDA mode is selected by setting the IREN bit in the US...

Page 1157: ...and less than two periods may be accepted or rejected those greater than two periods are accepted as a pulse The IrDA encoder decoder doesn t work when PSC 0 The receiver can communicate with a low p...

Page 1158: ...re 323 IrDA SIR ENDEC block diagram Figure 324 IrDA data modulation 3 16 Normal mode MSv31164V1 USART OR SIR Transmit Encoder SIR Receive DEcoder TX SIREN RX USART_RX IrDA_IN IrDA_OUT USART_TX MSv3116...

Page 1159: ...d to this address from memory after each TXE or TXFNF if FIFO mode is enabled event 2 Write the memory address in the DMA control register to configure it as the source of the transfer The data is loa...

Page 1160: ...er The data is loaded from USART_RDR to this memory area after each RXNE RXFNE in case FIFO mode is enabled event 3 Configure the total number of bytes to be transferred to the DMA control register 4...

Page 1161: ...USART_CR3 register which if set enables an interrupt after the current byte if any of these errors occur 35 5 20 RS232 Hardware flow control and RS485 Driver Enable It is possible to control the seri...

Page 1162: ...FO is full RS232 CTS flow control If the CTS flow control is enabled CTSE 1 then the transmitter checks the nCTS input before transmitting the next frame If nCTS is asserted tied low then the next dat...

Page 1163: ...e time between the activation of the DE signal and the beginning of the start bit It is programmed using the DEAT 4 0 bitfields in the USART_CR1 control register The deassertion time is the time betwe...

Page 1164: ...ow power mode the number of received data corresponds to the RXFIFO size and the RXFF flag is not set TXFIFO empty In this case the TXFEIE bit must be set before entering low power mode This enables s...

Page 1165: ...te mode on address match is used then the low power mode wakeup source must also be the address match If the RXNE flag was set when entering the low power mode the interface remains in Mute mode upon...

Page 1166: ...disabled Note The figures above are valid when address match or any received frame is used as wakeup event If the wakeup event is the start bit detection the USART sends the wakeup event to the MCU at...

Page 1167: ...racy For example if HSI is used as usart_ker_ck and the HSI inaccuracy is of 1 then we obtain tWUUSART 3 s values provided only as examples for correct values refer to the device datasheet DWUmax 3 41...

Page 1168: ...ead RXNE RXNEIE Read RDR or write 1 in RXFRQ YES YES NO Receive FIFO Not Empty RXFNE RXFNEIE Read RDR until RXFIFO empty or write 1 in RXFRQ YES Receive FIFO Full RXFF 2 RXFFIE Read RDR YES Receive FI...

Page 1169: ...OVRDIS 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXF FIE TXFEIE FIFO EN M1 EOBIE RTOIE DEAT 4 0 DEDT 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O...

Page 1170: ...rtion time This 5 bit value defines the time between the activation of the DE Driver Enable signal and the beginning of the start bit It is expressed in sample time units 1 8 or 1 16 bit time dependin...

Page 1171: ...ed on the received data This bit is set and cleared by software Once it is set PCE is active after the current byte in reception and in transmission 0 Parity control disabled 1 Parity control enabled...

Page 1172: ...ake up the MCU from low power mode When this bit is set the USART can wake up the MCU from low power mode This bit is set and cleared by software 0 USART not able to wake up the MCU from low power mod...

Page 1173: ...d in IrDA and LIN modes Bit 28 M1 Word length This bit must be used in conjunction with bit 12 M0 to determine the word length It is set or cleared by software M 1 0 00 1 start bit 8 Data bits n Stop...

Page 1174: ...be written when the USART is disabled UE 0 Note In LIN IrDA and Smartcard modes this bit must be kept cleared Bit 14 CMIE Character match interrupt enable This bit is set and cleared by software 0 Int...

Page 1175: ...by software 0 Interrupt inhibited 1 USART interrupt generated whenever TC 1 in the USART_ISR register Bit 5 RXNEIE Receive data register not empty This bit is set and cleared by software 0 Interrupt i...

Page 1176: ...value Refer to Section 35 4 USART implementation on page 1120 Bit 0 UE USART enable When this bit is cleared the USART prescalers and outputs are stopped immediately and all current operations are di...

Page 1177: ...this feature is enabled the RTOF flag in the USART_ISR register is set if the RX line is idle no reception for the duration programmed in the RTOR receiver timeout register Note If the USART does not...

Page 1178: ...al values are inverted VDD 0 mark Gnd 1 idle This enables the use of an external inverter on the RX line This bitfield can only be written when the USART is disabled UE 0 Bit 15 SWAP Swap TX RX pins T...

Page 1179: ...he CPOL bit to produce the desired clock data relationship see Figure 311 and Figure 312 0 The first clock transition is the first data capture edge 1 The second clock transition is the first data cap...

Page 1180: ...9 bit data modes the address detection is done on 6 bit and 8 bit address ADD 5 0 and ADD 7 0 respectively Bit 3 DIS_NSS When the DIS_NSS bit is set the NSS pin input is ignored 0 SPI slave selection...

Page 1181: ...of its depth 101 Receive FIFO becomes full Remaining combinations Reserved Bit 24 TCBGTIE Transmission Complete before guard time interrupt enable This bit is set and cleared by software 0 Interrupt i...

Page 1182: ...at reset value Refer to Section 35 4 USART implementation on page 1120 Bit 16 Reserved must be kept at reset value Bit 15 DEP Driver enable polarity selection 0 DE signal is active high 1 DE signal i...

Page 1183: ...kept at reset value Refer to Section 35 4 USART implementation on page 1120 Bit 9 CTSE CTS enable 0 CTS hardware flow control disabled 1 CTS mode enabled data is only transmitted when the nCTS input i...

Page 1184: ...is not selected 1 Half duplex mode is selected This bit can only be written when the USART is disabled UE 0 Bit 2 IRLP IrDA low power This bit is used for selecting between normal and low power IrDA...

Page 1185: ...6 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRR 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 1...

Page 1186: ...s In Smartcard mode PSC 4 0 Prescaler value PSC 4 0 is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock The value given in the register 5 significant bi...

Page 1187: ...also in other modes In this case the Block length counter is reset when RE 0 receiver disabled and or when the EOBCF bit is written to 1 Note This value can be programmed after the start of the block...

Page 1188: ...o data are written in the data register Bit 3 RXFRQ Receive data flush request Writing 1 to this bit empties the entire receive FIFO i e clears the bit RXFNE This enables to discard the received data...

Page 1189: ...ten in the USART_TDR has been transmitted correctly out of the shift register It is set by hardware in Smartcard mode if the transmission of a frame containing data is complete and if the smartcard di...

Page 1190: ...WU Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode It is cleared set by hardware when a wakeup mute sequence is recognized The Mute mode control sequence address or IDLE...

Page 1191: ...fer to Section 35 4 USART implementation on page 1120 Bit 12 EOBF End of block flag This bit is set by hardware when a complete block has been received for example T 1 Smartcard mode The detection is...

Page 1192: ...tion 35 4 USART implementation on page 1120 Bit 7 TXFNF TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR Every write operation to the...

Page 1193: ...er 0 No Idle line is detected 1 Idle line is detected Note The IDLE bit is not set again until the RXFNE bit has been set i e a new idle line occurs If Mute mode is enabled MME 1 IDLE is set if the US...

Page 1194: ...s associated with the character in the USART_RDR Bit 1 FE Framing error This bit is set by hardware when a de synchronization excessive noise or a break character is detected It is cleared by software...

Page 1195: ...efore entering low power mode Note If the USART does not support the wakeup from Stop feature this bit is reserved and kept at reset value Refer to Section 35 4 USART implementation on page 1120 Bit 2...

Page 1196: ...o the ABRRQ in the USART_RQR register Note If the USART does not support the auto baud rate feature this bit is reserved and kept at reset value Bit 14 ABRE Auto baud rate error This bit is set by har...

Page 1197: ...is bit is reserved and kept at reset value Bit 9 CTSIF CTS interrupt flag This bit is set by hardware when the nCTS input toggles if the CTSE bit is set It is cleared by software by writing 1 to the C...

Page 1198: ...ed 1 Received data is ready to be read Bit 4 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected An interrupt is generated if IDLEIE 1 in the USART_CR1 register It is cle...

Page 1199: ...in Smartcard mode this bit is set when the maximum number of transmit attempts is reached without success the card NACKs the data frame An interrupt is generated if EIE 1 in the USART_CR1 register 0...

Page 1200: ...r Note If the hardware flow control feature is not supported this bit is reserved and must be kept at reset value Refer to Section 35 4 USART implementation on page 1120 Bit 8 LBDCF LIN break detectio...

Page 1201: ...ft register and the internal bus see Figure 305 When receiving with the parity enabled the value read in the MSB bit is the received parity bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res...

Page 1202: ...1 4 Reserved must be kept at reset value Bits 3 0 PRESCALER 3 0 Clock prescaler The USART input clock can be divided by a prescaler factor 0000 input clock not divided 0001 input clock divided by 2 00...

Page 1203: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0C USART_BRR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res BRR 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 USART_GTPR Res Res Res...

Page 1204: ...s Res Res Res Res Res Res Res Res Res Res Res Res Res Res TDR 8 0 Reset value 0 0 0 0 0 0 0 0 0 0x2C USART_ PRESC Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Re...

Page 1205: ...enable UART communications up to 9600 baud Higher baud rates can be reached when the LPUART is clocked by clock sources different from the LSE clock Even when the device is in low power mode the LPUAR...

Page 1206: ...ta order with MSB first or LSB first shifting Configurable stop bits 1 or 2 stop bits Single wire Half duplex communications Continuous communications using DMA Received transmitted bytes are buffered...

Page 1207: ...communication using DMA X X Multiprocessor communication X X Synchronous mode Master Slave X Smartcard mode X Single wire Half duplex communication X X IrDA SIR ENDEC block X LIN mode X Dual clock dom...

Page 1208: ...when the lpuart_ker_ck is stopped When the dual clock domain feature is disabled the lpuart_ker_ck is the same as the lpuart_pclk clock There is no constraint between lpuart_pclk and lpuart_ker_ck lp...

Page 1209: ...quired in RS485 Hardware control mode DE Driver Enable This signal activates the transmission mode of the external transceiver Note DE and RTS share the same pin 36 4 3 LPUART character description Th...

Page 1210: ...receiver does not only store MS33194V2 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Start bit Stop bit Next Start bit Idle frame 9 bit word length M 01 1 Stop bit Possible Parity bit Break frame Data...

Page 1211: ...FT flag is set in the LPUART_ISR register and the corresponding interrupt if enabled is generated when the number of empty locations in the TXFIFO reaches the threshold programmed in the TXFTCFG bits...

Page 1212: ...buffer Communication is to take place Configure the DMA register as explained in Section 35 5 10 USART multiprocessor communication 6 Set the TE bit in LPUART_CR1 to send an idle frame as first trans...

Page 1213: ...transmission starts and the TXE bit is set When FIFO mode is enabled the TXFNF TXFIFO Not Full flag is set by hardware to indicate that the TXFIFO is not full the LPUART_TDR register is empty the nex...

Page 1214: ...n sending data even if the TXFIFO is full Idle characters Setting the TE bit drives the LPUART to send an idle frame before the first data frame 36 4 6 LPUART receiver The LPUART can receive data word...

Page 1215: ...he RXFIFO When a data is received it is stored in the RXFIFO together with the corresponding error bits An interrupt is generated if the RXNEIE RXFNEIE in case of FIFO mode bit is set The error flags...

Page 1216: ...that any data received during overrun is lost an interrupt is generated if either the RXNEIE bit or EIE bit is set FIFO mode enabled An overrun error occurs when the shift register is ready to be tran...

Page 1217: ...e Depending on the received data and wakeup mode selection the LPUART wakes up the MCU when needed in order to transfer the received data by software reading the LPUART_RDR register or by DMA For the...

Page 1218: ...ister Note The baud counters are updated to the new value in the baud registers after a write operation to LPUART_BRR Hence the baud rate register value should not be changed during communication It i...

Page 1219: ...timing where DWU is the error due to sampling point deviation when the wakeup from low power mode is used The LPUART receiver can receive data correctly at up to the maximum tolerated deviation speci...

Page 1220: ...e by means of the muting function To use the Mute mode feature the MME bit must be set in the LPUART_CR1 register Note When FIFO management is enabled and MME is already set MME bit must not be cleare...

Page 1221: ...using the ADDM7 bit This 4 bit 7 bit word is compared by the receiver with its own address which is programmed in the ADD bits in the LPUART_CR2 register Note In 7 bit and 9 bit data modes address de...

Page 1222: ...ected PS bit in LPUART_CR1 0 Odd parity The parity bit is calculated to obtain an odd number of 1s inside the frame made of the 6 7 or 8 LSB bits depending on M bit values and the parity bit As an exa...

Page 1223: ...a standard I O in idle or in reception It means that the I O must be configured so that TX is configured as alternate function open drain with an external pull up Apart from this the communication pro...

Page 1224: ...the DMA channel interrupt vector In transmission mode once the DMA has written all the data to be transmitted the TCIF flag is set in the DMA_ISR register the TC flag can be monitored to make sure th...

Page 1225: ...interrupt generation after half full transfer as required by the application 6 Activate the channel in the DMA control register When the number of data transfers programmed in the DMA Controller is re...

Page 1226: ...e RTSE and CTSE bits respectively to 1 in the LPUART_CR3 register RS232 RTS flow control If the RTS flow control is enabled RTSE 1 then nRTS is asserted tied low as long as the LPUART receiver is read...

Page 1227: ...be asserted at least 3 LPUART clock source periods before the end of the current character In addition it should be noted that the CTSCF flag may not be set for pulses shorter than 2 x PCLK periods R...

Page 1228: ...the TXFIFO or to empty the RXFIFO In this case the lpuart_wkup interrupt source can be RXFIFO not empty In this case the RXFNEIE bit must be set before entering low power mode RXFIFO full In this cas...

Page 1229: ...use idle detection cannot work in low power mode If the wakeup from Mute mode on address match is used then the low power mode wakeup source from must also be the address match If the RXNE flag was se...

Page 1230: ...ddress match or any received frame is used as wakeup event In the case the wakeup event is the start bit detection the LPUART sends the wakeup event to the MCU at the end of the start bit MSv40860V2 l...

Page 1231: ...of DWU is 3 41 In reality we need to consider at least the lpuart_ker_ck inaccuracy For example if HSI is used as lpuart_ker_ck and the HSI inaccuracy is of 1 then we obtain tWULPUART 3 s values prov...

Page 1232: ...IF CTSIE Write 1 in CTSCF NO Transmission Complete TC TCIE Write TDR or write 1 in TCCF NO Receive data register not empty data ready to be read RXNE RXNEIE Read RDR or write 1 in RXFRQ YES YES Receiv...

Page 1233: ...a in LPUART_RDR In Stop mode LPUART_RDR is not clocked As a result this register is not written and once n data are received and written in the RXFIFO the RXFF interrupt is asserted RXFF flag is not s...

Page 1234: ...DE Driver Enable signal It is expressed in lpuart_ker_ck clock cycles For more details refer Section 36 4 13 RS232 Hardware flow control and RS485 Driver Enable If the LPUART_TDR register is written d...

Page 1235: ...NFIE TXFIFO not full interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 A LPUART interrupt is generated whenever TXE TXFNF 1 in the LPUART_ISR register Bit 6 TCIE Tran...

Page 1236: ...tive the clock source for the LPUART must be HSI or LSE see RCC chapter Note It is recommended to set the UESM bit just before entering low power mode and clear it on exit from low power mode Bit 0 UE...

Page 1237: ...RT is disabled UE 0 Bits 20 16 DEDT 4 0 Driver Enable deassertion time This 5 bit value defines the time between the end of the last stop bit in a transmitted message and the de activation of the DE D...

Page 1238: ...enabled PCE bit set It is set and cleared by software The parity is selected after the current byte 0 Even parity 1 Odd parity This bitfield can only be written when the LPUART is disabled UE 0 Bit 8...

Page 1239: ...ck selection is HSI or LSE in the RCC This bit is set and cleared by software 0 LPUART not able to wake up the MCU from low power mode 1 LPUART able to wake up the MCU from low power mode When this fu...

Page 1240: ...ta is transmitted received with data bit 0 first following the start bit 1 data is transmitted received with the MSB bit 7 8 first following the start bit This bitfield can only be written when the LP...

Page 1241: ...This bit is for selection between 4 bit address detection or 7 bit address detection 0 4 bit address detection 1 7 bit address detection in 8 bit data mode This bit can only be written when the LPUAR...

Page 1242: ...FTIE TXFIFO threshold interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG Bit 22...

Page 1243: ...Error Flag ORE is set when received data is not read before receiving new data 1 Overrun functionality is disabled If new data is received while the RXNE flag is still set the ORE flag is not set and...

Page 1244: ...ed for reception Bits 5 4 Reserved must be kept at reset value Bit 3 HDSEL Half duplex selection Selection of Single wire Half duplex mode 0 Half duplex mode is not selected 1 Half duplex mode is sele...

Page 1245: ...he TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register Bit 3 RXFRQ Receive data flush request Writing 1 to this bit clea...

Page 1246: ...bit is set by hardware when TXFIFO is empty When the TXFIFO contains at least one data this flag is cleared The TXFE flag can also be set by writing 1 to the bit TXFRQ bit 4 in the LPUART_RQR registe...

Page 1247: ...r defined by ADD 7 0 is received It is cleared by software writing 1 to the CMCF in the LPUART_ICR register An interrupt is generated if CMIE 1in the LPUART_CR1 register 0 No Character match detected...

Page 1248: ...y software writing 1 to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register An interrupt is generated if TCIE 1 in the LPUART_CR1 register 0 Transmission is not complete 1 Tra...

Page 1249: ...ected 1 Noise is detected Note This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt An interrupt is generated when the NE flag is...

Page 1250: ...reset by hardware when the Transmit Enable value is taken into account by the LPUART It can be used when an idle frame request is generated by writing TE 0 followed by TE 1 in the LPUART_CR1 register...

Page 1251: ...ion on going Bits 15 11 Reserved must be kept at reset value Bit 10 CTS CTS flag This bit is set reset by hardware It is an inverted copy of the status of the nCTS input pin 0 nCTS line set 1 nCTS lin...

Page 1252: ...be read Bit 4 IDLE Idle line detected This bit is set by hardware when an Idle Line is detected An interrupt is generated if IDLEIE 1 in the LPUART_CR1 register It is cleared by software writing 1 to...

Page 1253: ...the LPUART_CR1 register 0 No Framing error is detected 1 Framing error or break character is detected Bit 0 PE Parity error This bit is set by hardware when a parity error occurs in receiver mode It...

Page 1254: ...it 1 FECF Framing error clear flag Writing 1 to this bit clears the FE flag in the LPUART_ISR register Bit 0 PECF Parity error clear flag Writing 1 to this bit clears the PE flag in the LPUART_ISR reg...

Page 1255: ...e written only when TXE TXFNF 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Re...

Page 1256: ...Res HDSEL Res Res EIE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0C LPUART_BRR Res Res Res Res Res Res Res Res Res Res Res Res BRR 19 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 0x...

Page 1257: ...er boundary addresses 0x2C LPUART_ PRESC Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PRESCALER 3 0 Reset value 0 0 0 0 Table 254 LPU...

Page 1258: ...t audio standards including the Philips I2 S standard the MSB and LSB justified standards and the PCM standard 37 2 SPI main features Master or slave operation Full duplex synchronous transfers on thr...

Page 1259: ...MSB justified standard left justified LSB justified standard right justified PCM standard with short and long frame synchronization on 16 bit channel frame or 16 bit data frame extended to 32 bit chan...

Page 1260: ...it data in master mode and receive data in slave mode SCK Serial Clock output pin for SPI masters and input pin for SPI slaves NSS Slave select pin Depending on the SPI and NSS settings this pin can b...

Page 1261: ...hifted the information between the master and slave is exchanged Figure 347 Full duplex single master single slave application 1 The NSS pins can be used to provide a hardware control flow between mas...

Page 1262: ...ng the SPI in transmit only or in receive only using the RXONLY bit in the SPIx_CR1 register In this configuration only one line is used for the transfer between the shift registers of the master and...

Page 1263: ...andard transmit only mode e g OVF flag 3 In this configuration both the MISO pins can be used as GPIOs Note Any simplex communication can be alternatively replaced by a variant of the half duplex comm...

Page 1264: ...etection NSS pin is used configured at hardware input mode The connection of more than two SPI nodes working at this mode is impossible as only one node can apply its output on a common data line at t...

Page 1265: ...bit value in register SPIx_CR1 The external NSS pin is free for other application uses Hardware NSS management SSM 0 in this case there are two possible configurations The configuration used depends...

Page 1266: ...nsferred This bit affects both master and slave modes If CPOL is reset the SCK pin has a low level idle state If CPOL is set the SCK pin has a high level idle state If the CPHA bit is set the second e...

Page 1267: ...r can be set up to shift out MSB first or LSB first depending on the value of the LSBFIRST bit The data frame size is chosen by using the DS bits It can be set from 4 bit up to 16 bit length and the s...

Page 1268: ...igure the LSBFIRST bit to define the frame format Note 2 e Configure the CRCL and CRCEN bits if CRC is needed while SCK clock signal is at idle state f Configure SSM and SSI Notes 2 3 g Configure the...

Page 1269: ...d in all SPI modes except for receiver only mode slave or master with CRC calculation enabled see Section 37 5 14 CRC calculation The handling of FIFOs depends on the data exchange mode duplex simplex...

Page 1270: ...lock or separate frames or data sessions with sufficient delays Be aware there is no underflow error signal for master or slave in SPI mode and data from the slave is always transacted and processed b...

Page 1271: ...r When transactions streams from DMA or FIFO are completed while the last data frame or CRC frame transaction is still ongoing in the peripheral bus The correct disable procedure is except when receiv...

Page 1272: ...a DMA capability which implements a simple request acknowledge protocol A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is set Separate requests must be issued to th...

Page 1273: ...y following the SPI disable procedure 3 Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register if DMA Tx and or DMA Rx are used Packing with DMA If the transfer...

Page 1274: ...all the data to be sent can fit into TxFIFO the DMA Tx TCIF flag can be raised even before communication on the SPI bus starts This flag always rises before the SPI transaction is completed 6 The CRC...

Page 1275: ...to 3 Number of Rx frames transacted by DMA is set to 3 See also Communication diagrams on page 1274 for details about common assumptions and notes DTx1 10 DRx1 NSS SCK BSY MOSI MSB MSB MSB DTx2 DTx3 S...

Page 1276: ...3 Number of Rx frames transacted by DMA is set to 3 See also Communication diagrams on page 1274 for details about common assumptions and notes DTx1 10 DRx1 NSS SCK BSY MISO MSB MSB MSB DTx2 DTx3 SPE...

Page 1277: ...ansacted by DMA is set to 2 Number of Rx frames transacted by DMA is set to 3 See also Communication diagrams on page 1274 for details about common assumptions and notes DTx1 10 DRx1 NSS SCK BSY MOSI...

Page 1278: ...set to 3 PSIZE for both Tx and Rx DMA channel is set to 16 bit LDMA_TX 1 and LDMA_RX 1 See also Communication diagrams on page 1274 for details about common assumptions and notes 4 3 2 1 10 NSS SCK BS...

Page 1279: ...rue Busy flag BSY The BSY flag is set and cleared by hardware writing to this flag has no effect When BSY is set it indicates that a data transfer is in progress on the SPI the SPI bus is busy The BSY...

Page 1280: ...set The SPE bit is cleared This blocks all output from the device and disables the SPI interface The MSTR bit is cleared thus forcing the device into slave mode Use the following software sequence to...

Page 1281: ...mpling edge is the rising edge of SCK and NSS assertion and deassertion refer to this sampling edge 37 5 13 TI mode TI protocol in master mode The SPI interface is compatible with the TI protocol The...

Page 1282: ...endently of the frame data length which can be fixed to 8 bit or 16 bit For all the other data frame lengths no CRC is available CRC principle CRC calculation is enabled by setting the CRCEN bit in th...

Page 1283: ...d by DMA When SPI communication is enabled with CRC communication and DMA mode the transmission and reception of the CRC at the end of communication is automatic with the exception of reading CRC data...

Page 1284: ...rresponding setting CPOL 0 CPHA 1 has to be kept at the SPIx_CR1 register anyway if CRC is applied In addition the CRC calculation has to be reset between sessions by SPI disable sequence with re enab...

Page 1285: ...the I2SMOD bit in the SPIx_I2SCFGR register This interface mainly uses the same pins flags and interrupts as the SPI Tx buffer Shift register 16 bit Communication Rx buffer 16 bit MOSI SD Master cont...

Page 1286: ...registers are not used in the I2 S mode Likewise the SSOE bit in the SPIx_CR2 register and the MODF and CRCERR bits in the SPIx_SR are not used The I2S uses the same SPI register for data transfer SPI...

Page 1287: ...re the first bit MSB is available Figure 363 I2 S Philips protocol waveforms 16 32 bit full accuracy Data are latched on the falling edge of CK for the transmitter and are read on the rising edge for...

Page 1288: ...at If the data to transmit or the received data are 0x76A3 0x76A30000 extended to 32 bit the operation shown in Figure 368 is required Figure 368 Example of 16 bit data frame extended to 32 bit channe...

Page 1289: ...provided between two write or read operations which prevents underrun or overrun conditions depending on the direction of the data transfer MSB justified standard For this standard the WS signal is g...

Page 1290: ...LSB justified 16 bit or 32 bit full accuracy Figure 373 LSB justified 24 bit frame length In transmission mode If data 0x3478AE have to be transmitted two write operations to the SPIx_DR register are...

Page 1291: ...re to 0x0000 to extend the data to 32 bit format In this case it corresponds to the half word MSB If the data to transmit or the received data are 0x76A3 0x0000 76A3 extended to 32 bit the operation s...

Page 1292: ...tions to prevent underrun or overrun conditions PCM standard For the PCM standard there is no need to use channel side information The two PCM modes short and long frame are available and configurable...

Page 1293: ...number of bits between two consecutive pieces of data and so two synchronization signals needs to be specified DATLEN and CHLEN bits in the SPIx_I2SCFGR register even in slave mode 37 7 3 Start up des...

Page 1294: ...ardware waits for the appropriate transition on the incoming WS signal using the CK signal MSv37520V2 dum not significant data WS O SD O CK O CKPOL 0 Left sample Right sample I2SE WS O CK O CKPOL 1 SD...

Page 1295: ...e I2S clock signal frequency I2S bit rate number of bits per channel number of channels sampling audio frequency For a 16 bit audio left and right channel the I2S bit rate is calculated as follows I2S...

Page 1296: ...range In order to reach the desired frequency the linear divider needs to be programmed according to the formulas below For I2 S modes When the master clock is generated MCKOE in the SPIx_I2SPR regis...

Page 1297: ...16 23 1 No 32000 31914 8936 0 2660 48 32 11 1 No 32000 32608 696 1 9022 48 16 34 0 No 22050 22058 8235 0 0400 48 32 17 0 No 22050 22058 8235 0 0400 48 16 47 0 No 16000 15957 4468 0 2660 48 32 23 1 No...

Page 1298: ...bit in SPIx_I2SCFGR register must be set WS and CK are configured in output mode MCK is also an output if the MCKOE bit in SPIx_I2SPR is set Transmission sequence The transmission sequence begins when...

Page 1299: ...enerated and the OVR flag is set If the ERRIE bit is set in the SPIx_CR2 register an interrupt is generated to indicate the error To switch off the I2S specific actions are required to ensure that the...

Page 1300: ...e CHSIDE flag indicates which channel is to be transmitted Compared to the master transmission mode in slave mode CHSIDE is sensitive to the WS signal coming from the external master This means that t...

Page 1301: ...is set in the SPIx_CR2 register an interrupt is generated to indicate the error To switch off the I2S in reception mode I2SE has to be cleared immediately after receiving the last RXNE 1 Note The ext...

Page 1302: ...SPIx_SR is set and the ERRIE bit in SPIx_CR2 is also set an interrupt is generated This interrupt can be cleared by reading the SPIx_SR status register once the interrupt source has been cleared 37 7...

Page 1303: ...ication clock or on the WS frame synchronization line An error interrupt can be generated if the ERRIE bit is set The desynchronization flag FRE is cleared by software when the status register is read...

Page 1304: ...E Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode 0 Output disabled receive only mode 1 Output enabled transmit only...

Page 1305: ...effect only when the SSM bit is set The value of this bit is forced onto the NSS pin and the I O value of the NSS pin is ignored Note This bit is not used in I2 S mode and SPI TI mode Bit 7 LSBFIRST F...

Page 1306: ...e TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used data length 8 bit and write access to SPIx_DR is 16 bit wide It has to be written when the SPI is disabled SPE 0 in the SPIx_C...

Page 1307: ...E interrupt not masked Used to generate an interrupt request when the RXNE flag is set Bit 5 ERRIE Error interrupt enable This bit controls the generation of an interrupt when an error condition occur...

Page 1308: ...buffer DMA enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res FTLVL 1 0 FRLVL 1 0 FRE BSY OVR MODF CRCE RR UDR CHSIDE TXE RXNE r r r r r r r r rc_w0 r r r r Bits 15 13 Reserved must be kept at...

Page 1309: ...fault MODF on page 1280 for the software sequence Note This bit is not used in I2 S mode Bit 4 CRCERR CRC error flag 0 CRC value received matches the SPIx_RXCRCR value 1 CRC value received does not ma...

Page 1310: ...between the Rx and Tx FIFOs When the data register is read RxFIFO is accessed while the write to data register accesses TxFIFO See Section 37 5 9 Data transmission and reception procedures Note Data i...

Page 1311: ...n the BSY Flag is set could return an incorrect value These bits are not used in I2 S mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCRC 15 0 r r r r r r r r r r r r r r r r Bits 15 0 TXCRC 15 0 Tx CRC...

Page 1312: ...ion Bit 11 I2SMOD I2S mode selection 0 SPI mode is selected 1 I2S mode is selected Note This bit should be configured when the SPI is disabled Bit 10 I2SE I2S enable 0 I2S peripheral is disabled 1 I2S...

Page 1313: ...umber of bits per audio channel 0 16 bit wide 1 32 bit wide The bit write operation has a meaning only if DATLEN 00 otherwise the channel length is fixed to 32 bit by hardware whatever the value fille...

Page 1314: ...M0453 Rev 2 Bits 7 0 I2SDIV 7 0 I2S linear prescaler I2SDIV 7 0 0 or I2SDIV 7 0 1 are forbidden values Refer to Section 37 7 3 on page 1293 Note These bits should be configured when the I2S is disable...

Page 1315: ...es Res Res Res Res Res Res Res Res Res Res Res Res FTLVL 1 0 FRLVL 1 0 FRE BSY OVR MODF CRCERR UDR CHSIDE TXE RXNE Reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 0x0C SPIx_DR Res Res Res Res Res Res Res Res Re...

Page 1316: ...ug features ROM table see Section 38 8 System control space SCS Breakpoint unit FPB see Section 38 9 Data watchpoint and trace unit DWT see Section 38 6 Instrumentation trace macrocell ITM see Section...

Page 1317: ...ore stops due to a breakpoint or a debugger stop command the other core can be stopped as well Similarly the cores can be restarted at the same time This allows the user to debug loosely coupled appli...

Page 1318: ...SWDIO I JTAG test mode select IO Serial wire data in out PA13 JTCK SWCLK I JTAG test clock I Serial wire clock PA14 JTDI I JTAG test data input PA15 JTDO TRACESWO 1 1 Debug access port JTDO and Trace...

Page 1319: ...ked with the corresponding core clock 38 3 5 DBG power domains The debug components are located in the core power domain This means that debugger connection is not possible in Shutdown or Standby low...

Page 1320: ...the following serial data sequence on JTMS SWDIO 50 or more ones 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 50 or more ones JTCK SWCLK must be cycled for each data bit In SW DP mode the unused JTAG pins JTDI JTD...

Page 1321: ...M goes through the Update IR state the value scanned into the IR scan chain is transferred into the instruction register When the TAPSM goes through the Capture DR state a value is transferred from on...

Page 1322: ...an AP abort 1001 BYPASS 1 Reserved BYPASS selected 1010 DPACC 35 Debug port access register Initiates the debug port and gives access to a debug port register When transferring data IN Bits 34 3 DATA...

Page 1323: ...or by the target in case of a read see Table 266 The data transfer only occurs if the acknowledge response is OK Between each phase if the direction of the data is reversed a single clock cycle turn a...

Page 1324: ...68 DP register map and reset values The debugger accesses the DP registers as follows Program the A 3 2 field in the DPACC register if using JTAG with the register address within the bank Program the...

Page 1325: ...read or DP_RDBUFFR read Used in the event of a corrupted read transfer W DP_SELECTR register see Section 38 4 8 Selects the access port access port register bank and DP register at address 0x4 0xC 11...

Page 1326: ...ode 0x5 Bits 27 20 PARTNO 7 0 part number for the debug port 0xBA Bits 19 17 Reserved must be kept at reset value Bit 16 MIN minimal debug port MINDP implementation 0x0 MINDP not implemented transacti...

Page 1327: ...ky compare clear 0 No effect 1 Clears DP_CTRLSTATR STICKYCMP bit Bit 0 DAPABORT data AP abort Aborts current AP transaction if an excessive number of WAIT responses are returned indicating that the tr...

Page 1328: ...te data error read only in SW DP There is a parity or framing error on the data phase of a write or a write that has been accepted by the DP is then discarded without being submitted to the AP This bi...

Page 1329: ...is set 0x3 reserved In pushed operation only the data bytes indicated by the MASKLANE field are included in the compare Bit 1 STICKYORUN overrun read only in SW DP R W in JTAG DP Indicates that an ov...

Page 1330: ...Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TREVISION 3 0 TPARTNO 15 4 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPARTNO 3 0 TDESI...

Page 1331: ...9 18 17 16 RESEND 31 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESEND 15 0 r r r r r r r r r r r r r r r r Bits 31 0 RESEND 31 0 Returns the value that was returned by t...

Page 1332: ...IDR 0x3 DP_DLPIDR 0x4 to 0xF reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDBUFF 31 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDBUFF 15 0 r r r r r r r r r r...

Page 1333: ...R to select this device Bit 0 Reserved must be kept at reset value Table 268 DP register map and reset values Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 1334: ...re listed in Table 270 AP register map and reset values 0x04 4 DP_DLPIDR TINSTANCE 3 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PROTSVN 3 0 Reset...

Page 1335: ...x00 0x0 0 AP_CSWR Control status word register see Section 38 5 1 0x04 0x0 1 AP_TAR Transfer address register see Section 38 5 2 Target address for the bus transaction 0x08 Reserved 0x0C 0x0 3 AP_DRWR...

Page 1336: ...cessary with the transfer parameters AddrInc for example 3 Write to or read from the AP_DRWR register to initiate a bus transaction at the address held in the AP_TAR register Alternatively a read or w...

Page 1337: ...k 0x1 0x10 0xF4 0xF8 0xFC Control status word CSW Transfer address TAR Reserved Data read write DRW Bank 0xF 0xF0 Address incrementer Memory access port MEM AP APSEL decode Data 31 0 A 7 4 A 3 2 RnW A...

Page 1338: ...ROT 4 0 bus transfer protection In the AHB APs this field sets the protection attributes HPROT 4 0 of the bus transfer XXXX0 Instruction fetch XXXX1 Data access XXX0X User mode XXX1X Privileged mode X...

Page 1339: ...corresponding to the programmed transaction size The data is packed or unpacked accordingly 0x3 reserved Bit 3 Reserved must be kept at reset value Bits 2 0 SIZE 2 0 size of next memory access transa...

Page 1340: ...ess incrementing is not performed on AP_BD 3 0 R Banked transfers are only supported for word transfers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BASEADDR 19 4 r r r r r r r r r r r r r r r r 15...

Page 1341: ...s Res Res Res Res IDENTITY 7 0 r r r r r r r r Bits 31 28 REVISION 3 0 revision 0x2 CPU1 Cortex M4 r0p3 0x6 CPU2 Cortex M0 r0p7 Bits 27 24 JEDECBANK 3 0 JEDEC bank 0x4 Arm Bits 23 17 JEDECCODE 6 0 JED...

Page 1342: ...31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x18 AP_BD2R TBD 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C AP_BD3R TBD 31...

Page 1343: ...ssor to halt execution and enter Debug state For more details on how to use the DWT refer to the Arm v7 M Architecture Reference Manual 5 38 6 1 DWT control register DWT_CTRLR Address offset 0x000 Res...

Page 1344: ...ed Bits 15 13 Reserved must be kept at reset value Bit 12 PCSAMPLENA enable for POSTCNT counter used as a timer for periodic PC sample packet generation 0 Disabled 1 Enabled Bits 11 10 SYNCTAP 1 0 syn...

Page 1345: ...0 CYCCNT 31 0 processor clock cycle counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res R...

Page 1346: ...s Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res SLEEPCNT 7 0 rw rw rw rw rw rw rw rw Bits 31 8 Reserved must be kept at reset value Bits 7 0 SLEEPCNT 7...

Page 1347: ...Res Res Res FOLDCNT 7 0 rw rw rw rw rw rw rw rw Bits 31 8 Reserved must be kept at reset value Bits 7 0 FOLDCNT 7 0 folded instruction counter Increments on each instruction that takes 0 cycles 31 30...

Page 1348: ...23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res MATCH ED Res Res Res Res DATAVADDR1 3 0 r rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAVADDR0 3 0 DATAVSIZE 1 0 LNK1E NA DATAV MATCH CYCMA...

Page 1349: ...ved must be kept at reset value Bit 5 EMITRANGE Enables generation of data trace address offset packets containing data address bits 0 to 15 0x0 Disabled 0x1 Enabled Bit 4 Reserved must be kept at res...

Page 1350: ...8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PARTNUM 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PARTNUM 7 0 part number bits 7 0 0x02 DWT part number 31 30 29 28...

Page 1351: ...JEDEC JEP106ID 6 4 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVISION 3 0 component revision number 0x3 r0p4 Bit 3 JEDEC JEDEC assigned value 0x1 Designer ID specified by...

Page 1352: ...3 2 1 0 Res Res Res Res Res Res Res Res PREAMBLE 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PREAMBLE 7 0 component ID bits 7 0 0x0D Common ID value 31 30 29 28 27 26 2...

Page 1353: ...25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PREAMBLE 27 20 r r r r r r r r Bits...

Page 1354: ...es Res Res Res Res Res Res MATCHED Res Res Res Res DATAVADDR1 3 0 DATAVADDR0 3 0 DATAVSIZE 1 0 LNK1ENA DATAVMATCH CYCMATCH Res EMITRANGE Res FUNCTION 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1355: ...es Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res JEP106ID 3 0 PARTNUM 11 8 Reset value 1 0 1 1 0 0 0 0 0xFE8 DWT_PIDR2 Res Res Res Res Res Res Res Res Res Res Res Res...

Page 1356: ...y For example a breakpoint reached in one of the processor cores can stop the other processor Each CTI has up to eight trigger inputs and eight trigger outputs Any input can be connected to any output...

Page 1357: ...ut signal Destination component Comments 0 EDBGRQ CPU2 CPU2 halt request Puts CPU2 in debug mode 1 Not used 2 Not used 3 Not used 4 Not used 5 Not used 6 Not used 7 DBGRESTART CPU2 CPU2 restart reques...

Page 1358: ...ame input on the CPU1 CTI Hence the CTI_IENR0 register is programmed on each CTI to connect these inputs to a CTM channel such as channel 0 As shown in Table 273 and Table 275 the EDBGRQ signals to th...

Page 1359: ...n also force both cores to stop simultaneously by writing 0x01 to the CTI_APPPULSER register in either CTI which generates a pulse on channel 0 For more information on the CTI CoreSight component refe...

Page 1360: ...es Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res GLBEN rw Bits 31 1 Reserved must be kept at reset value Bit 0 GLBEN global enable 0 Cross t...

Page 1361: ...4 Reserved must be kept at reset value Bits 3 0 APPSET 3 0 channel event setting Read XXX0 Channel 0 event inactive XXX1 Channel 0 event active XX0X Channel 1 event inactive XX1X Channel 1 event activ...

Page 1362: ...4 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res APPPULSE 3 0 w w w w Bit...

Page 1363: ...27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res TRIGOUTEN 3 0...

Page 1364: ...es Res Res Res Res Res Res TRIGOUTSTATUS 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 TRIGOUTSTATUS 7 0 trigger output status There is one bit of the register for each C...

Page 1365: ...the register for each channel output When a bit is set to 1 it indicates that the corresponding channel output is active When it is set to 0 the corresponding channel output is inactive 31 30 29 28 27...

Page 1366: ...d must be kept at reset value Bits 3 0 CLAIMSET 3 0 claim tag bits setting Write 0000 No effect XXX1 Sets bit 0 XX1X Sets bit 1 X1XX Sets bit 2 1XXX Sets bit 3 Read 1111 Indicates there are four bits...

Page 1367: ...C5AC CE55 Write access enabled Other values Write access disabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8...

Page 1368: ...d Bits 5 4 SID 1 0 security level for secure invasive debug 0x0 Not implemented Bits 3 2 NSNID 1 0 security level for non secure non invasive debug 0x2 Disabled 0x3 Enabled Bits 1 0 NSID 1 0 security...

Page 1369: ...reset value Bits 7 4 SUBTYPE 3 0 sub classification 0x1 Indicates that this component is a cross triggering component Bits 3 0 MAJORTYPE 3 0 major classification 0x4 Indicates that this component allo...

Page 1370: ...4 3 2 1 0 Res Res Res Res Res Res Res Res PARTNUM 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PARTNUM 7 0 part number bits 7 0 0x06 CTI part number 31 30 29 28 27 26 2...

Page 1371: ...ID 6 4 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVISION 3 0 component revision number 0x4 r0p5 Bit 3 JEDEC JEDEC assigned value 0x1 Designer identifier specified by JED...

Page 1372: ...0 Res Res Res Res Res Res Res Res PREAMBLE 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PREAMBLE 7 0 component ID bits 7 0 0x0D Common ID value 31 30 29 28 27 26 25 24...

Page 1373: ...s Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PREAMBLE 27 20 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 P...

Page 1374: ...3 0 Reset value 0 0 0 0 0x038 CTI_INENR6 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TRIGINEN 3 0 Reset value 0 0 0 0 0x03C CTI_INEN...

Page 1375: ...EEN 3 0 Reset value 1 1 1 1 0x144 to 0xF8C Reserved Reserved 0xFA0 CTI_CLAIMSETR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CLAIMSE...

Page 1376: ...0 Reset value 0 0 0 0 0 1 1 0 0xFE4 CTI_PIDR1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res JEP106ID 3 0 PARTNUM 11 8 Reset value 1 0 1 1 1 0 0 1 0xF...

Page 1377: ...Entry 0xE00FF000 SCS 0xE000E000 0xFFF0F000 4 K 0xFFF0F003 0xE00FF004 DWT 0xE0001000 0xFFF02000 4 K 0xFFF02003 0xE00FF008 FPB 0xE0002000 0xFFF03000 4 K 0xFFF03003 0xE00FF00C ITM 0xE0000000 0xFFF01000...

Page 1378: ...point trace DWT 0xE0001000 0x000 PIDR4 0xFD0 CIDR3 0xFFC Register file base Instrumentation trace ITM 0xE0000000 0x000 PIDR4 0xFD0 CIDR3 0xFFC Offset 0xFFF0F000 0x000 Offset 0xFFF02000 0x004 Offset 0x...

Page 1379: ...0 Res Res Res Res Res Res Res Res F4KCOUNT 3 0 JEP106CON 3 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 F4KCOUNT 3 0 register file size 0x0 Register file occupies a single...

Page 1380: ...r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 JEP106ID 3 0 JEP106 identity code bits 3 0 0x0 STMicroelectronics JEDEC code Bits 3 0 PARTNUM 11 8 part number bits 11 8 0x4 STM32WL5x 3...

Page 1381: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res REVAND 3 0 CMOD 3 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVAND 3 0 metal fix version 0x0 No metal...

Page 1382: ...5 4 3 2 1 0 Res Res Res Res Res Res Res Res CLASS 3 0 PREAMBLE 11 8 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 CLASS 3 0 component ID bits 15 12 component class 0x1 ROM ta...

Page 1383: ...0 JEP106CON 3 0 Reset value 0 0 0 0 0 0 0 0 0xFD4 0xFDC Reserved Reserved 0xFE0 ROM_PIDR0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PARTNUM 7 0 Re...

Page 1384: ...20 Reset value 1 0 1 1 0 0 0 1 Table 278 CPU1 ROM table register map and reset values continued Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 1385: ...whether Flash memory patch remap is supported read only 1 Remapping supported Bits 28 5 REMAP 23 0 remap target address Bits 28 5 of the base address in SRAM to which the FPB remaps the address The r...

Page 1386: ...2 of accesses to instruction code memory 0x00000000 to 0x1FFFFFFF If a match occurs the action to be taken is defined by the REPLACE field Bit 1 Reserved must be kept at reset value Bit 0 ENABLE compa...

Page 1387: ...9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PARTNUM 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PARTNUM 7 0 part number bits 7 0 0x03 FPB part number 31 30 29...

Page 1388: ...EC JEP106ID 6 4 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVISION 3 0 component revision number 0x2 r0p3 Bit 3 JEDEC JEDEC assigned value 0x1 Designer ID specified by JE...

Page 1389: ...4 3 2 1 0 Res Res Res Res Res Res Res Res PREAMBLE 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PREAMBLE 7 0 component ID bits 7 0 0x0D Common ID value 31 30 29 28 27 26...

Page 1390: ...pt at reset value Bits 7 0 PREAMBLE 19 12 component ID bits 23 16 0x05 Common ID value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 1...

Page 1391: ...0 0 0 0xFE8 FPB_PIDR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res REVISION 3 0 JEDEC JEP106ID 6 4 Reset value 0 0 1 0 1 0 1 1 0xFEC FPB_PIDR3 Res R...

Page 1392: ...or pending in bit 0 2 Hardware trace The DWT generates trace packets in response to a data trace event a PC sample or a performance profiling counter wraparound The ITM outputs these packets on the t...

Page 1393: ...17 16 PRIVMASK 31 16 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRIVMASK 15 0 r r r r r r r r r r r r r r r r Bits 31 0 PRIVMASK 31 0 Enables unprivileged access to ITM sti...

Page 1394: ...ifferent IDs must be used for each trace source in the system Bits 15 10 Reserved must be kept at reset value Bits 9 8 TSPRESCALE 1 0 local timestamp prescaler Used with the trace packet reference clo...

Page 1395: ...3 2 1 0 Res Res Res Res Res Res Res Res F4KCOUNT 3 0 JEP106CON 3 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 F4KCOUNT 3 0 register file size 0x0 Register file occupies a...

Page 1396: ...r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 JEP106ID 3 0 JEP106 identity code bits 3 0 0xB Arm JEDEC code Bits 3 0 PARTNUM 11 8 part number bits 11 8 0x0 ITM part number 3...

Page 1397: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res REVAND 3 0 CMOD 3 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVAND 3 0 metal fix version 0x0 No metal fix...

Page 1398: ...2 1 0 Res Res Res Res Res Res Res Res CLASS 3 0 PREAMBLE 11 8 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 CLASS 3 0 component ID bits 15 12 component class 0xE Trace genera...

Page 1399: ...080 ITM_TER STIMENA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x084 to 0xDCC Reserved Reserved 0xE00 ITM_TPR PRIVMASK 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1400: ...s Res Res Res Res Res Res Res Res Res REVAND 3 0 CMOD 3 0 Reset value 0 0 0 0 0 0 0 0 0xFF0 ITM_CIDR0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PR...

Page 1401: ...t indicates that port size n is supported 0x0000 000F Port sizes 1 to 4 supported 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PORTSIZE 31 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 1...

Page 1402: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res TXMODE 1 0 rw rw Bits 31 2 Reserved must be kept at reset value Bits 1 0 TXMODE 1 0 selects the protocol used fo...

Page 1403: ...reflects the status of the AFVALIDS output A flush can be initiated by the flush control bits in the TPIU_FFCR register 0 No flush in progress 1 Flush in progress 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 1404: ...of 128 bits It is a 12 bit counter with a maximum count value of 4096 This equates to synchronization every 65536 bytes that is 4096 packets x 16 bytes per packet The default is set up for a synchron...

Page 1405: ...CLAIMCLR 3 0 resets claim tag bits Write 0000 No effect xxx1 Clears bit 0 xx1x Clears bit 1 x1xx Clears bit 2 1xxx Clears bit 3 Read Returns current value of claim tag 31 30 29 28 27 26 25 24 23 22 2...

Page 1406: ...Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res SUBTYPE 3 0 MAJORTYPE 3 0 r r r r r r r r Bits 31 8 Reserved must be kept at...

Page 1407: ...10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PARTNUM 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PARTNUM 7 0 part number bits 7 0 0x02 TPIU part number 31 30...

Page 1408: ...JEDEC JEP106ID 6 4 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVISION 3 0 component revision number 0x4 r0p5 Bit 3 JEDEC JEDEC assigned value 0x1 Designer ID specified b...

Page 1409: ...7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PREAMBLE 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PREAMBLE 7 0 component ID bits 7 0 0x0D Common ID value 31 30 29 2...

Page 1410: ...7 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PREAMBLE 27 20 r r r r r r r r...

Page 1411: ...s Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CLAIMCLR 3 0 Reset value 0 0 0 0 0xFA8 to 0xF Reserved Reserved 0xFC8 TPIU_DEVIDR Res Res Res Res Res Res Res...

Page 1412: ...0xFE8 TPIU_PIDR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res REVISION 3 0 JEDEC JEP106ID 6 4 Reset value 0 1 0 0 1 0 1 1 0xFEC TPIU_PIDR3 Res Res R...

Page 1413: ...r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res DEV_ID 11 0 r r r r r r r r r r r r Bits 31 16 REV_ID 15 0 revision For values refer to the device errata sheet Bits 15 12 Reserved...

Page 1414: ...clocks and oscillators continue to run during Stop mode allowing full debug capability On exit from Stop mode the clock settings are set to the Stop mode exit state Bit 0 DBG_SLEEP Allows CPU1 debug i...

Page 1415: ...debug mode 1 Stop in debug IWDG is frozen while CPU1 is in debug mode Bit 11 DBG_WWDG_STOP WWDG stop in CPU1 debug 0 Normal operation WWDG continues to operate while CPU1 is in debug mode 1 Stop in d...

Page 1416: ...CPU2 debug 0 Normal operation I2C1 SMBUS timeout continues to operate while CPU2 is in debug mode 1 Stop in debug I2C1 SMBUS timeout is frozen while CPU2 is in debug mode Bits 20 13 Reserved must be k...

Page 1417: ...in debug mode Bits 4 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5...

Page 1418: ...operation TIM17 continues to operate while CPU1 is in debug mode 1 Stop in debug TIM17 is frozen while CPU1 is in debug mode Bit 17 DBG_TIM16_STOP TIM16 stop in CPU1 debug 0 Normal operation TIM16 con...

Page 1419: ...8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 DBGMCU_ IDCODER REV_ID 15 0 Res Res Res Res DEV_ID 11 0 Reset value x x x x x x x x x x x x x x x x 0 1 0 0 1 0 0 1 0 1 1 1 0x004 DBGMCU_CR Res Res...

Page 1420: ...ide chunk of AHB address space from 0xF0000000 to 0xF0000FFC 0x048 DBGMCU_ C2APB1FZR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DBG_LPTIM3_STO...

Page 1421: ...0FCC to 0xF0000FFC ROM table registers See Table 285 Table 283 ROM1 table Address in ROM table Component name Component base address Component address offset Size Entry Table 284 ROM2 table Address in...

Page 1422: ...ASER register 0xF8 CPU2 ROM1 table 0xF0000000 Top of table PIDR4 CIDR3 Offset 0x00001000 Offset 0x00002000 Offset 0x10000000 CPU2 ROM2 table 0xE00FF000 0x000 Top of table 0x004 0x008 0x00C Register fi...

Page 1423: ...1 0 Res Res Res Res Res Res Res Res F4KCOUNT 3 0 JEP106CON 3 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 F4KCOUNT 3 0 register file size 0x0 Register file occupies a sin...

Page 1424: ...8 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 JEP106ID 3 0 JEP106 identity code bits 3 0 0xB Arm JEDEC code Bits 3 0 PARTNUM 11 8 part number bits 11 8 0x4 Cortex M0 proces...

Page 1425: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res REVAND 3 0 CMOD 3 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVAND 3 0 metal fix version 0x0 No m...

Page 1426: ...7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res CLASS 3 0 PREAMBLE 11 8 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 CLASS 3 0 component ID bits 15 12 component class 0x1 R...

Page 1427: ...Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res F4KCOUNT 3 0 JEP106CON 3 0 Reset value 0 0 0 0 0 1 0 0 0xFD4 0xFDC Reserved Reserved 0xFE0 C2ROM1_PIDR0 Res Res Res Res Res Res Res Res...

Page 1428: ...s Res Res Res Res PREAMBLE 27 20 Reset value 1 0 1 1 0 0 0 1 Table 285 CPU2 processor ROM table register map and reset values continued Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 1429: ...28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PARTNUM 7 0 r r r r r r r...

Page 1430: ...ON 3 0 JEDEC JEP106ID 6 4 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVISION 3 0 component revision number 0x0 rev r0p0 Bit 3 JEDEC JEDEC assigned value 1 Designer ID spe...

Page 1431: ...Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PREAMBLE 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 P...

Page 1432: ...r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PREAMBLE 27 20 component ID bits 31 24 0xB1 Common ID value Table 286 CPU2 ROM table register map and reset values Offset Register name...

Page 1433: ...s Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PREAMBLE 7 0 Reset value 0 0 0 0 1 1 0 1 0xFF4 C2ROM2_CIDR1 Res Res Res Res Res Res Res Res Res Res Res Re...

Page 1434: ...it 1 KEY write protect key A write to BPU_CTRLR register is ignored if this bit is not set to 1 Bit 0 ENABLE BPU enable 0 Disabled 1 Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res RMP...

Page 1435: ...28 2 of accesses to instruction code memory 0x00000000 to 0x1FFFFFFF If a match occurs the action to be taken is defined by the REPLACE field Bit 1 Reserved must be kept at reset value Bit 0 ENABLE co...

Page 1436: ...8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res PARTNUM 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PARTNUM 7 0 part number bits 7 0 0x0C BPU part number 31 30 29 28...

Page 1437: ...JEDEC JEP106ID 6 4 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 4 REVISION 3 0 component revision number 0x2 r0p3 Bit 3 JEDEC JEDEC assigned value 1 Designer ID specified by...

Page 1438: ...3 2 1 0 Res Res Res Res Res Res Res Res PREAMBLE 7 0 r r r r r r r r Bits 31 8 Reserved must be kept at reset value Bits 7 0 PREAMBLE 7 0 component ID bits 7 0 0x0D Common ID value 31 30 29 28 27 26...

Page 1439: ...e kept at reset value Bits 7 0 PREAMBLE 19 12 component ID bits 23 16 0x05 Common ID value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res R...

Page 1440: ...alue 1 0 1 1 0 0 0 0 0xFE8 BPU_PIDR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res REVISION 3 0 JEDEC JEP106ID 6 4 Reset value 0 0 1 0 1 0 1 1 0xFEC B...

Page 1441: ...5 3 DDI 0461B ID010111 Arm CoreSight Trace Memory Controller r0p1 Technical Reference Manual Issue B 10 Dec 2010 4 DDI 0314H Arm CoreSight Components Technical Reference Manual Issue H 10 July 2009 5...

Page 1442: ...USB string serial number or other end applications for use as part of the security keys to increase the code security in the Flash memory while using and combining this unique ID with software crypto...

Page 1443: ...7 6 5 4 3 2 1 0 UID 47 32 r r r r r r r r r r r r r r r r Bits 31 8 UID 63 40 LOT_NUM 23 0 lot number ASCII encoded Bits 7 0 UID 39 32 WAF_NUM 7 0 wafer number 8 bit unsigned number 31 30 29 28 27 26...

Page 1444: ...0x00 Reset value 0xXXXX XXXX Note X is factory programmed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res PKG 4 0 r r r r r Bits 15 5 Reserved must be kept at reset v...

Page 1445: ...lue 0x0080 E115 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STID 23 8 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STID 7 0 DEVID 7 0 r r r r r r r r r r r r r r r r Bits...

Page 1446: ...m PVD naming in Section 6 6 2 PWR control register 2 PWR_CR2 and Section 6 6 6 Power status register 2 PWR_SR2 First sentence in Section 7 1 2 System reset External source HSE32 TXCO First sentence of...

Page 1447: ...IDR3 1439 BPU_COMPxR 1434 BPU_CTRLR 1433 BPU_PIDR0 1436 BPU_PIDR1 1436 BPU_PIDR2 1437 BPU_PIDR3 1437 BPU_PIDR4 1435 BPU_REMAPR 1434 C C1ROM_CIDR3 1383 C2ROM1_CIDR0 1425 C2ROM1_CIDR1 1426 C2ROM1_CIDR2...

Page 1448: ...469 DMA_CMARx 475 DMA_CNDTRx 474 DMA_CPARx 475 DMA_IFCR 468 DMA_ISR 465 DMAMUX_CCFR 492 DMAMUX_CSR 492 DMAMUX_CxCR 491 DMAMUX_RGCFR 495 DMAMUX_RGSR 494 DMAMUX_RGxCR 493 DP_ABORTR 1326 DP_BUFFR 1332 DP...

Page 1449: ...H_AFRL 421 GPIOH_BRR 422 GPIOH_BSRR 420 GPIOH_IDR 419 GPIOH_LCKR 420 GPIOH_MODER 417 GPIOH_ODR 419 GPIOH_OSPEEDR 418 GPIOH_OTYPER 417 GPIOH_PUPDR 418 GPIOx_AFRH 407 GPIOx_AFRL 407 GPIOx_BRR 408 GPIOx_...

Page 1450: ...RT_RQR 1245 LPUART_TDR 1254 P PKA_CLRFR 720 PKA_CR 718 PKA_SR 719 PKG 1444 PWR_C2CR1 268 PWR_C2CR3 269 PWR_CR1 253 PWR_CR2 255 PWR_CR3 256 PWR_CR4 258 PWR_CR5 263 PWR_EXTSCR 270 PWR_PDCRA 264 PWR_PDCR...

Page 1451: ...020 RTC_SR 1027 RTC_SSR 1012 RTC_TR 1010 RTC_TSDR 1022 RTC_TSSSR 1022 RTC_TSTR 1021 RTC_WPR 1019 RTC_WUTR 1015 S SPIx_CR1 1304 SPIx_CR2 1306 SPIx_CRCPR 1310 SPIx_DR 1310 SPIx_I2SCFGR 1311 SPIx_I2SPR 1...

Page 1452: ...19 TIM16_AF1 939 TIM16_OR1 939 TIM16_TISEL 940 TIM17_AF1 941 TIM17_OR1 940 TIM17_TISEL 942 TIM2_AF1 889 TIM2_ARR 886 TIM2_CCER 883 TIM2_CCMR1 877 878 TIM2_CCMR2 881 882 TIM2_CCR1 886 TIM2_CCR2 886 TIM...

Page 1453: ...1401 U UID 1442 UID64 1444 USART_BRR 1185 USART_CR1 1169 1173 USART_CR2 1176 USART_CR3 1180 USART_GTPR 1185 USART_ICR 1199 USART_ISR 1188 1194 USART_PRESC 1202 USART_RDR 1201 USART_RQR 1187 USART_RTOR...

Page 1454: ...selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted...

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