S i 4 4 3 0
88
Preliminary Rev. 0.4
Reset value = xx000110
Register 0Ah. Microcontroller Output Clock
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved
clkt[1:0]
enlfc
mclk[2:0]
Type
R
R/W
R/W
R/W
Bit
Name
Function
7:6
Reserved
Reserved.
5:4
clkt[1:0]
Clock Tail.
If enlfc = 0 then it can be useful to provide a few extra cycles for the microcontroller to
complete its operation. Setting the clkt[1:0] register will provide the addition cycles of the
clock before it shuts off.
00: 0
cycle
01: 128
cycles
10: 256
cycles
11: 512
cycles
3
enlfc
Enable Low Frequency Clock.
When enlfc = 1 and the chip is in Sleep mode then the 32.768 kHz clock will be provided
to the microcontroller no matter what the selection of mclk[2:0] is. For example if
mclk[2:0] = ‘000’, 30 MHz will be available through the GPIO to output to the microcon-
troller in all Idle, TX, or RX states. When the chip is commanded to Sleep mode the
30 MHz clock will become 32.768 kHz.
2:0
mclk[2:0]
Microcontroller Clock.
Different clock frequencies may be selected for configurable GPIO clock output. All clock
frequencies are created by dividing the XTAL except for the 32 kHz clock which comes
directly from the 32 kHz RC Oscillator. The mclk[2:0] setting is only valid when xton = 1
except the 111.
000: 30
MHz
001: 15
MHz
010: 10
MHz
011: 4
MHz
100: 3
MHz
101: 2
MHz
110: 1
MHz
111:
32.768 kHz
