Silicon Laboratories Si4430, Manual

Page: 83 / 152

Si4430
Preliminary Rev. 0.4 83
Reset value = 00000000
Register 05h. Interrupt Enable 1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name
enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror
Type
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 enfferr
Enable FIFO Underflow/Overflow.
When set to 1 the FIFO Underflow/Overflow interrupt will be enabled.
6 entxffafull
Enable TX FIFO Almost Full.
When set to 1 the TX FIFO Almost Full interrupt will be enabled.
5 entxffaem
Enable TX FIFO Almost Empty.
When set to 1 the TX FIFO Almost Empty interrupt will be enabled.
4 enrxffafull
Enable RX FIFO Almost Full.
When set to 1 the RX FIFO Almost Full interrupt will be enabled.
3 enext
Enable External Interrupt.
When set to 1 the External Interrupt will be enabled.
2 enpksent
Enable Packet Sent.
When ipksent =1 the Packet Sense Interrupt will be enabled.
1 enpkvalid
Enable Valid Packet Received.
When ipkvalid = 1 the Valid Packet Received Interrupt will be enabled.
0 encrcerror
Enable CRC Error.
When set to 1 the CRC Error interrupt will be enabled.