Silicon Laboratories Si4430, Manual

Page: 148 / 152

S i 4 4 3 0
148 Preliminary Rev. 0.4
Reset value = 00000100
Reset value = 00110111
Reset value = NA
Register 7Dh. TX FIFO Control 2
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name
Reserved txfaethr[5:0]
Type
R/W R/W
Bit Name Function
7:6 Reserved
Reserved.
5:0 txfaethr[5:0]
TX FIFO Almost Empty Threshold.
Register 7Eh. RX FIFO Control
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name
Reserved rxafthr[5:0]
Type
R/W R/W
Bit Name Function
7:6 Reserved
Reserved.
5:0 rxafthr[5:0]
RX FIFO Almost Full Threshold.
Register 7Fh. FIFO Access
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name
fifod[7:0]
Type
R/W
Bit Name Function
7:0 fifod[7:0]
FIFO Data.
A Write (R/W = 1) to this Address will begin a Burst Write to the TX FIFO. The FIFO will
be loaded in the same manner as a Burst SPI Write but the SPI address will not be incre-
mented. To conclude the TX FIFO Write the SEL pin should be brought HIGH. A Read
(R/W = 0) to this address will begin a burst read of the RX FIFO, in the same manner.