Silicon Laboratories Si4430, Manual

Page: 76 / 152

S i 4 4 3 0
76 Preliminary Rev. 0.4
3D R/W Transmit Header 0 txhd[7] txhd[6] txhd[5] txhd[4] txhd[3] txhd[2] txhd[1] txhd[0] 00h
3E R/W Transmit Packet Length pklen[7] pklen[6] pklen[5] pklen[4] pklen[3] pklen[2] pklen[1] pklen[0] 00h
3F R/W Check Header 3 chhd[31] chhd[30] chhd[29] chhd[28] chhd[27] chhd[26] chhd[25] chhd[24] 00h
40 R/W Check Header 2 chhd[23] chhd[22] chhd[21] chhd[20] chhd[19] chhd[18] chhd[17] chhd[16] 00h
41 R/W Check Header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] 00h
42 R/W Check Header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] 00h
43 R/W Header Enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26] hden[25] hden[24] FFh
44 R/W Header Enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] FFh
45 R/W Header Enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] FFh
46 R/W Header Enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2] hden[1] hden[0] FFh
47 R Received Header 3 rxhd[31] rxhd[30] rxhd[29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] —
48 R Received Header 2 rxhd[23] rxhd[22] rxhd[21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] —
49 R Received Header 1 rxhd[15] rxhd[14] rxhd[13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] —
4A R Received Header 0 rxhd[7] rxhd[6] rxhd[5] rxhd[4] rxhd[3] rxhd[2] rxhd[1] rxhd[0] —
4B R Received Packet Length rxplen[7] rxplen[6] rxplen[5] rxplen[4] rxplen[3] rxplen[2] rxplen[1] rxplen[0] —
4C-4E Reserved
4F R/W ADC8 Control Reserved Reserved adc8[5] adc8[4] adc8[3] adc8[2] adc8[1] adc8[0] 00h
50 R/W Analog Test Bus Reserved Reserved Reserved atb[4] atb[3] atb[2] atb[1] atb[0] 00h
51 R/W Digital Test Bus Reserved ensctest dtb[5] dtb[4] dtb[3] dtb[2] dtb[1] dtb[0] 00h
52 R/W TX Ramp Control Reserved txmod[2] txmod[1] txmod[0] ldoramp[1] ldoramp[0] txramp[1] txramp[0] 2Fh
53 R/W PLL Tune Time pllts[4] pllts[3] pllts[2] pllts[1] pllts[0] pllt0[2] pllt0[1] pllt0[0] 52h
54 R/W Invalid Preamble Threshold and PA Misc Reserved Reserved inv_pre_th[3] inv_pre_th[2] inv_pre_th[1] inv_pre_th[0] Ido_pa_boost pa_vbias_
boost
14h
55 R/W Calibration Control Reserved xtalstarthalf adccaldone enrcfcal rccal vcocaldp vcocal skipvco 44h
56 R/W Modem Test bcrfbyp slicfbyp dttype oscdeten OOkth refclksel refclkinv distogg 00h
57 R/W Chargepump Test pfdrst fbdiv_rst cpforceup cpforcedn cdconly cdccur[2] cdccur[1] cdccur[0] 00h
58 R/W Chargepump Current Trimming/Override cpcurr[1] cpcurr[0] cpcorrov cpcorr[4] cpcorr[3] cpcorr[2] cpcorr[1] cpcorr[0] 80h
59 R/W Divider Current Trimming txcorboosten fbdivhc d3trim[1] d3trim[0] d2trim[1] d2trim[0] d1p5trim[1] d1p5trim[0] 40h
5A R/W VCO Current Trimming txcurboosten vcocorrov vcocorr[3] vcocorr[2] vcocorr[1] vcocorr[0] vcocur[1] vcocur[0] 03h
5B R/W VCO Calibration / Override vcocalov/
vcdone
vcocal[6] vcocal[5] vcocal[4] vcocal[3] vcocal[2] vcocal[1] vcocal[0] 00h
5C R/W Synthesizer Test dsmdt vcotype enoloop dsmod dsorder[1] dsorder[0] dsrstmod dsrst 0Eh
5D R/W Block Enable Override 1 enmix enlna enpga enpa enbf5 endv32 enbf12 enmx2 00h
5E R/W Block Enable Override 2 ends enldet enmx3 enbf4 enbf3 enbf11 enbf2 pllreset 40h
5F R/W Block Enable Override 3 enfrdv endv31 endv2 endv1p5 dvbshunt envco encp enbg 00h
60 R/W Channel Filter Coefficient Address Reserved Reserved Reserved Reserved chfiladd[3] chfiladd[2] chfiladd[1] chfiladd[0] 00h
61 R/W Channel Filter Coefficient Value Reserved Reserved chfilval[5] chfilval[4] chfilval[3] chfilval[2] chfilval[1] chfilval[0] 00h
62 R/W Crystal Oscillator / Control Test pwst[2] pwst[1] pwst[0] clkhyst enbias2x enamp2x bufovr enbuf 24h
63 R/W RC Oscillator Coarse Calibration/Override rccov rcc[6] rcc[5] rcc[4] rcc[3] rcc[2] rcc[1] rcc[0] 00h
64 R/W RC Oscillator Fine Calibration/Override rcfov rcf[6] rcf[5] rcf[4] rcf[3] rcf[2] rcf[1] rcf[0] 00h
65 R/W LDO Control Override enspor enbias envcoldo enifldo enrfldo enpllldo endigldo endigpwdn 81h
66 R/W LDO Level Setting enovr enxtal ents enrc32 Reserved diglvl[2] diglvl[1] diglvl[0] 02h
67 R/W Deltasigma ADC Tuning 1 adcrst enrefdac enadc adctuneovr adctune[3] adctune[2] adctune[1] adctune[0] 1Dh
68 R/W Deltasigma ADC Tuning 2 Reserved Reserved Reserved envcm adcoloop adcref[2] adcref[1] adcref[0] 03h
69 R/W AGC Override 1 Reserved Reserved agcen lnagain pga3 pga2 pga1 pga0 20h
6A R/W AGC Override 2 agcovpm agcslow lnacomp[3] lnacomp[2] lnacomp[1] lnacomp[0] pgath[1] pgath[0] 1Dh
6B R/W GFSK FIR Filter Coefficient Address Reserved Reserved Reserved Reserved Reserved firadd[2] firadd[1] firadd[0] 00h
6C R/W GFSK FIR Filter Coefficient Value Reserved Reserved firval[5] firval[4] firval[3] firval[2] firval[1] firval[0] 01h
6D R/W TX Power Reserved Reserved Reserved Reserved Ina_sw txpow[2] txpow[1] txpow[0] 08h
6E R/W TX Data Rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0Ah
6F R/W TX Data Rate 0 txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] 3Dh
70 R/W Modulation Mode Control 1 Reserved Reserved txdtrtscale enphpwdn manppol enmaninv enmanch enwhite 0Ch
71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h
72 R/W Frequency Deviation fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] 20h
73 R/W Frequency Offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h
74 R/W Frequency Offset 2 Reserved Reserved Reserved Reserved Reserved Reserved fo[9] fo[8] 00h
75 R/W Frequency Band Select Reserved sbsel Reserved fb[4] fb[3] fb[2] fb[1] fb[0] 75h
76 R/W Nominal Carrier Frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh
77 R/W Nominal Carrier Frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h
78 R/W Miscellaneous Settings Reserved Reserved Reserved Reserved Alt_PA_Seq rcosc[2] rcosc[1] rcosc[0] 09h
79 R/W Frequency Hopping Channel Select fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h
7A R/W Frequency Hopping Step Size fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h
7B R/W Turn Around and 15.4 Length Compliance 15.4 Length Reserved Reserved Reserved Reserved turn_around
_en
Phase[1] Phase[0] 09h
7C R/W TX FIFO Control 1 Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h
7D R/W TX FIFO Control 2 Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h
7E R/W RX FIFO Control Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h
7F R/W FIFO Access fifod[7] fifod[6] fifod[5] fifod[4] fifod[3] fifod[2] fifod[1] fifod[0] —
Table 27. Register Descriptions (Continued)
Add R/W Function/Desc Data POR
Default
D7 D6 D5 D4 D3 D2 D1 D0