S i 4 4 3 0
24
Preliminary Rev. 0.4
3.5. System Timing
The system timing for TX and RX modes is shown in Figures 8 and 7. The timing is shown transitioning from
STANDBY mode to TX mode and going automatically through the built-in sequencer of required steps. If a small
range of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at
the initial power up of the device. The relevant system timing registers are shown below.
The VCO will automatically calibrate at every frequency change or power up. The VCO CAL may also be forced by
setting the vcocal bit. The 32.768 kHz RC oscillator is also automatically calibrated but the calibration may also be
forced. The enrcfcal will enable the RC Fine Calibration which will occur every 30 seconds. The rccal bit will force a
complete calibration of the RC oscillator which will take approximately 2 ms. The PLL T0 time is to allow for bias
settling of the VCO, the default for this should be adequate. The PLL TS time is for the settling time of the PLL,
which has a default setting of 200 µs. This setting should be adequate for most applications but may be reduced if
small frequency jumps are used. For more information on the PLL register configuration options, see “Register
53h. PLL Tune Time,” on page 126 and “Register 55h. Calibration Control,” on page 127.
Figure 7. TX Timing
Add R/W Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
53
R/W
PLL Tune Time
pllts[4:0]
pllt0[2:0]
45h
54
R/W
Reserved 1
X
X
X
X
X
X
X
X
00h
55
R/W
Calibration Control
xtal-
starthalf
adccal-
done
enrcfcal
rccal
vco-
caldp
vcocal
skip-
vco
04h
TX Packet
XTAL Settling
Time
PLL T0
PL
L CAL
PLLTS
600us
Con
fig
u
ra
b
le
0
-70us
, De
fa
ul
t
= 50
us
45us, May
be
sk
ip
pe
d
P
R
E PA
RAMP
PA
RA
M
P
U
P
PA RA
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D
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N
Co
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fi
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ur
a
b
le 0-3
1
0
u
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R
eco
mmen
d
100u
s
6
u
s,
Fi
xe
d
Co
nf
igur
able 5-2
0
us, Recom
m
en
d 5u
s
Config
ur
a
b
le 5-
2
0
us, Recom
m
end
5us
