Si4430
Preliminary Rev. 0.4
53
8. Auxiliary Functions
8.1. Smart Reset
The Si4430 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a
classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable
reset signal in any circumstances. Reset will be initiated if any of the following conditions occur:
Initial power on, when VDD starts from 0V: reset is active till VDD reaches V
RR
(see table);
When VDD decreases below V
LD
for any reason: reset is active till VDD reaches V
RR
again;
A software reset via “Register 08h. Operating Mode and Function Control 2,” on page 86: reset is active for time
T
SWRST
On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit:
Figure 23. POR Glitch Parameters
The reset will initialize all registers to their default values. The reset signal is also available for output and use by
the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on
GPIO_1.
Table 22. POR Parameters
Parameter
Symbol
Comment
Min
Typ
Max
Unit
Release Reset Voltage
VRR
0.85
1.3
1.75
V
Power-On VDD Slope
SVDD
tested VDD slope region
0.03
300
V/ms
Low VDD Limit
VLD
VLD<VRR is guaranteed
0.7
1
1.3
V
Software Reset Pulse
TSWRST
50
470
us
Threshold Voltage
VTSD
0.4
V
Reference Slope
k
0.2
V/ms
VDD Glitch Reset Pulse
TP
Also occurs after SDN, and
initial power on
5
15
40
ms
Reset
T
P
t=0,
VDD starts to rise
t
VDD(t)
reset:
Vglitch>=0.4+t*0.2V/ms
actual VDD(t)
showing glitch
reset limit:
0.4V+t*0.2V/ms
VDD nom.
0.4V
