S i 4 4 3 0
142
Preliminary Rev. 0.4
Reset value = 00000000
The frequency deviation can be calculated: Fd = 625 Hz x fd[8:0].
Register 71h. Modulation Mode Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
trclk[1:0]
dtmod[1:0]
eninv
fd[8]
modtyp[1:0]
Type
R/W
R/W
R/W
R/W
R/W
Bit
Name
Function
7:6
trclk[1:0]
TX Data Clock Configuration.
00:
No TX Data CLK is available (asynchronous mode – Can only work with modula-
tions FSK or OOK).
01:
TX Data CLK is available via the GPIO (one of the GPIO’s should be programmed
as well).
10:
TX Data CLK is available via the SDO pin.
11:
TX Data CLK is available via the nIRQ pin.
5:4
dtmod[1:0]
Modulation Source.
00:
Direct Mode using TX_Data function via the GPIO pin (one of the GPIO’s should
be programmed accordingly as well)
01:
Direct Mode using TX_Data function via the SDI pin (only when nSEL is high)
10: FIFO
Mode
11: PN9
(internally
generated)
3
eninv
Invert TX and RX Data.
2
fd[8]
MSB of Frequency Deviation Setting, see "Register 72h. Frequency Deviation".
1:0
modtyp[1:0]
Modulation Type.
00:
Unmodulated carrier
01:
OOK
10:
FSK
11:
GFSK (enable TX Data CLK (trclk[1:0]) when direct mode is used)
