Silicon Laboratories Si4430, Manual

Page: 19 / 152

Si4430
Preliminary Rev. 0.4 19
Figure 3. SPI Timing—READ Mode
The SPI interface contains a burst read/write mode which will allows for reading/writing sequential registers without
having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An SPI burst write
transaction is demonstrated in Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be
latched into the Si4430 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5.
Figure 4. SPI Timing—Burst Write Mode
Figure 5. SPI Timing—Burst Read Mode
nSEL
SCLK
SDI
First Bit Last Bit
A0
D7
=X
SDO D7
A1 A2
First Bit Last Bit
A3
D6
=X D5
=X D4
=X D3
=X D2
=X D1
=X D0
=X
D6 D5 D4 D3 D2 D1 D0
A4 A5 A6
RW
=0
nSEL
SCLK
SDI
First Bit
A0
D7
=X
A1 A2 A3
D6
=X D5
=X D4
=X D3
=X D2
=X D1
=X D0
=X
A4 A5 A6
RW
=1
Last Bit
D7
=X D6
=X D5
=X D4
=X D3
=X D2
=X D1
=X D0
=X
nSEL
SCLK
SDI
First Bit Last Bit
A0
D7
=X
SDO D7
A1 A2
First Bit
A3
D6
=X D5
=X D4
=X D3
=X D2
=X D1
=X D0
=X
D6 D5 D4 D3 D2 D1 D0
A4 A5 A6
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0