S i 4 4 3 0
126
Preliminary Rev. 0.4
The total settling time (cold start) of the PLL after the calibration can be calculated as T
CS
= T
S
+ T
O
.
Reset value = 01010010
Reset value = 01010100
Invalid preamble will be evaluated during this period: (invalid_preamble_Threshold x 4) x Bit Rate period.
Register 53h. PLL Tune Time
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
pllts[4:0]
pllt0
Type
R/W
R/W
Bit
Name
Function
7:3
pllts[4:0]
PLL Soft Settling Time (T
S
).
This register will set the settling time for the PLL from a previous locked frequency in
Tune mode. The value is configurable between 0 µs and 310 µs, in 10 µs intervals. The
default plltime corresponds to 100 µs. See formula above.
2:0
pllt0
PLL Settling Time (T
O
).
This register will set the time allowed for PLL settling after the calibrations are completed.
The value is configurable between 0 µs and 70 µs, in 10 µs steps. The default pllt0 corre-
sponds to 20 µs. See formula above.
Register 54h. PA Boost
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved[7:6]
inv_pre_th
ldo_pa_boost pa_vbias_boost
Type
R/W
R/W
R/W
R/W
Bit
Name
Function
7:6
Reserved[7:6]
Reserved.
5:2
inv_pre_th[5:2]
Invalid Preamble Threshold.
1
ldo_pa_boost
LDO PA Boost.
0
pa_vbias_boost
PA VBIAS Boost.
