Si4430
Preliminary Rev. 0.4
149
13. Pin Descriptions: Si4430
Pin
Pin Name
I/O
Description
1
VDD_RF
VDD
+1.8 to +3.6 V supply voltage input to all 1.7 V regulators. The recommended V
DD
supply voltage
is +3.3 V.
2
TX
O
Transmit output pin. The PA output is an open-drain connection so the L-C match must supply VDD
(+3.3 VDC nominal) to this pin.
3
RXp
I
Differential RF input pins of the LNA. See application schematic for example matching network.
4
RXn
I
5
VR_IF
O
Regulated Output Voltage of the IF 1.7 V Regulator. A 1 µF decoupling capacitor is required.
6
NC
—
No Connect.
7
GPIO_0
I/O
General Purpose Digital I/O that may be configured through the registers to perform various functions
including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW,
AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for
more information.
8
GPIO_1
I/O
9
GPIO_2
I/O
10
VDR
O
Regulated Output Voltage of the Digital 1.7 V Regulator. A 1 µF decoupling capacitor is required.
11
NC
—
No Connect.
12
VDD_DIG
VDD
+1.8 to +3.6 V supply voltage input to the D1.7 V Regulator. The recommended V
DD
supply voltage
is +3.3 V.
13
SDO
O
0–V
DD
V digital output that provides a serial readback function of the internal control registers.
20
SDI
I
Serial Data input. 0–V
DD
V digital input. This pin provides the serial data stream for the 4-line serial data
bus.
21
SCLK
I
Serial Clock input. 0–V
DD
V digital input. This pin provides the serial data clock function for the 4-line
serial data bus. Data is clocked into the Si4430 on positive edge transitions.
22
nSEL
I
Serial Interface Select input. 0– V
DD
V digital input. This pin provides the Select/Enable function for the 4-
line serial data bus. The signal is also used to signify burst read/write mode.
23
nIRQ
O
General Microcontroller Interrupt Status output. When the Si4430 exhibits anyone of the Interrupt Events
the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information on the
Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corre-
sponding SPI Interrupt Status Registers, Address 03h and 04h.
24
XOUT
O
Crystal Oscillator Output. Connect to an external 30 MHz crystal or leave floating if driving the Xin pin with
an external signal source.
25
XIN
I
Crystal Oscillator Input. Connect to an external 30 MHz crystal or to an external source. If using an exter-
nal clock source with no crystal, dc coupling with a nominal 0.8 VDC level is recommended with a mini-
mum ac amplitude of 700 mVpp.
26
SDN
I
Shutdown input pin. 0–V
DD
V digital input. SDN should be = 0 in all modes except Shutdown mode. When
SDN =1 the chip will be completely shutdown and the contents of the registers will be lost.
PKG
PADDLE_GND
GND
The exposed metal paddle on the bottom of the Si4430 supplies the RF and circuit ground(s) for the entire
chip. It is very important that a good solder connection is made between this exposed metal paddle and
the ground plane of the PCB underlying the Si4430.
VDD_RF
1
2
3
4
15
14
13
12
6
7
8
9
19 18 17
20
TX
RXp
RXn
SCLK
SDI
SDO
VDD_DIG
NC
GPI
O
_
0
GPI
O
_
1
GPI
O
_
2
XIN
XO
UT
SD
N
nIR
Q
Metal
Paddle
5
11
VR_IF
NC
10
16
VD
R
nSE
L
