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12-bit Analog-to-Digital Converter (S08ADCV1)

MC9S08QE128 MCU Series Reference Manual, Rev. 2

Freescale Semiconductor

183

10.3.2

Status and Control Register 2 (ADCSC2)

The ADCSC2 register is used to control the compare function, conversion trigger and conversion active of
the ADC module.

Figure 10-5. Status and Control Register 2 (ADCSC2)

01000

AD8

11000

AD24

01001

AD9

11001

AD25

01010

AD10

11010

AD26

01011

AD11

11011

AD27

01100

AD12

11100

Reserved

01101

AD13

11101

V

REFH

01110

AD14

11110

V

REFL

01111

AD15

11111

Module disabled

7

6

5

4

3

2

1

0

R

ADACT

ADTRG

ACFE

ACFGT

0

0

R

1

1

Bits 1 and 0 are reserved bits that must always be written to 0.

R

1

W

Reset:

0

0

0

0

0

0

0

0

= Unimplemented or Reserved

Table 10-4. ADCSC2 Register Field Descriptions

Field

Description

7

ADACT

Conversion Active — ADACT indicates that a conversion is in progress. ADACT is set when a conversion is
initiated and cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress

6

ADTRG

Conversion Trigger Select — ADTRG is used to select the type of trigger to be used for initiating a conversion.
Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a
conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated
following the assertion of the ADHWT input.
0 Software trigger selected
1 Hardware trigger selected

Figure 10-4. Input Channel Select (continued)

ADCH

Input Select

ADCH

Input Select

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Summary of Contents for MC9S08QE128

Page 1: ...8QE64 Reference Manual MC9S08QE128RM Rev 2 6 2007 Related Documentation MC9S08QE128 Data Sheet Contains pin assignments and diagrams all electrical specifications and mechanical drawing outlines Find the most current versions of all documents at http www freescale com ...

Page 2: ......

Page 3: ...rcuit debugging plus two more breakpoints in on chip debug module On chip in circuit emulator ICE debug module containing three comparators and nine trigger modes Eight deep FIFO for storing change of flow addresses and event only data Debug module supports both tag and force breakpoints Peripherals ADC 24 channel 12 bit resolution 2 5 μs conversion time automatic compare function 1 7 mV C tempera...

Page 4: ......

Page 5: ...ale com MC9S08QE128 Reference Manual Covers MC9S08QE128 MC9S08QE96 MC9S08QE64 MC9S08QE128RM Rev 2 6 2007 Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Freescale Semiconductor Inc 2007 All rights reserved ...

Page 6: ...ave the latest information available refer to http freescale com The following revision history table summarizes changes contained in this document Revision Number Revision Date Description of Changes 1 30 Apr 2007 Initial preliminary release 2 25 Jun 2007 Initial public release Freescale Semiconductor Inc 2007 All rights reserved This product incorporates SuperFlash Technology licensed from SST ...

Page 7: ...rupt S08KBIV2 139 Chapter 8 Central Processor Unit S08CPUV4 145 Chapter 9 Analog Comparator 3V ACMPVLPV1 167 Chapter 10 Analog to Digital Converter S08ADC12V1 175 Chapter 11 Internal Clock Source S08ICSV3 203 Chapter 12 Inter Integrated Circuit S08IICV2 217 Chapter 13 Real Time Counter S08RTCV1 237 Chapter 14 Serial Communications Interface S08SCIV4 247 Chapter 15 Serial Peripheral Interface S08SP...

Page 8: ... Reference Pins VREFH VREFL 35 2 2 6 General Purpose I O and Peripheral Ports 35 Chapter 3 Modes of Operation 3 1 Introduction 39 3 2 Features 39 3 3 Run Mode 39 3 3 1 Low Power Run Mode LPRun 39 3 4 Active Background Mode 41 3 5 Wait Mode 42 3 5 1 Low Power Wait Mode LPWait 42 3 6 Stop Modes 42 3 6 1 Stop2 Mode 43 3 6 2 Stop3 Mode 44 3 6 3 Active BDM Enabled in Stop Mode 45 3 6 4 LVD Enabled in S...

Page 9: ...etect LVD System 96 5 6 1 Power On Reset Operation 96 5 6 2 Low Voltage Detection LVD Reset Operation 96 5 6 3 Low Voltage Detection LVD Interrupt Operation 96 5 6 4 Low Voltage Warning LVW Interrupt Operation 96 5 7 Peripheral Clock Gating 96 5 8 Reset Interrupt and System Control Registers and Control Bits 98 5 8 1 Interrupt Pin Request Status and Control Register IRQSC 98 5 8 2 System Reset Sta...

Page 10: ...ters 115 6 5 2 Port B Registers 117 6 5 3 Port C Registers 119 6 5 4 Port D Registers 123 6 5 5 Port E Registers 125 6 5 6 Port F Registers 129 6 5 7 Port G Registers 131 6 5 8 Port H Registers 133 6 5 9 Port J Registers 135 Chapter 7 Keyboard Interrupt S08KBIV2 7 1 Introduction 139 7 1 1 KBI Clock Gating 139 7 1 2 Features 139 7 1 3 Modes of Operation 139 7 1 4 Block Diagram 140 7 2 External Sign...

Page 11: ...ct Addressing Mode DIR 150 8 3 5 Extended Addressing Mode EXT 150 8 3 6 Indexed Addressing Mode 150 8 4 Special Operations 151 8 4 1 Reset Sequence 151 8 4 2 Interrupt Sequence 151 8 4 3 Wait Mode Operation 152 8 4 4 Stop Mode Operation 152 8 4 5 BGND Instruction 153 8 5 HCS08 Instruction Set Summary 155 Chapter 9 Analog Comparator 3V ACMPVLPV1 9 1 Introduction 167 9 1 1 ACMP Configuration Informa...

Page 12: ...sult High Register ADCRH 184 10 3 4 Data Result Low Register ADCRL 184 10 3 5 Compare Value High Register ADCCVH 185 10 3 6 Compare Value Low Register ADCCVL 185 10 3 7 Configuration Register ADCCFG 185 10 3 8 Pin Control 1 Register APCTL1 187 10 3 9 Pin Control 2 Register APCTL2 188 10 3 10Pin Control 3 Register APCTL3 189 10 4 Functional Description 190 10 4 1 Clock Select and Divide Control 190...

Page 13: ... Switching 214 11 4 3 Bus Frequency Divider 215 11 4 4 Low Power Bit Usage 215 11 4 5 DCO Maximum Frequency with 32 768 kHz Oscillator 215 11 4 6 Internal Reference Clock 215 11 4 7 External Reference Clock 216 11 4 8 Fixed Frequency Clock 216 11 4 9 Local Clock 216 Chapter 12 Inter Integrated Circuit S08IICV2 12 1 Introduction 217 12 1 1 Module Configuration 217 12 1 2 Interrupt Vectors 217 12 1 ...

Page 14: ...es 237 13 1 3 RTC Modes of Operation 237 13 1 4 RTC Clock Gating 237 13 1 5 Interrupt Vector 238 13 1 6 Features 240 13 1 7 Modes of Operation 240 13 1 8 Block Diagram 241 13 2 External Signal Description 241 13 3 Register Definition 241 13 3 1 RTC Status and Control Register RTCSC 242 13 3 2 RTC Counter Register RTCCNT 243 13 3 3 RTC Modulo Register RTCMOD 243 13 4 Functional Description 244 13 4...

Page 15: ... 1 Introduction 267 15 1 1 SPI Clock Gating 267 15 1 2 Interrupt Vector 267 15 1 3 Features 269 15 1 4 Block Diagrams 269 15 1 5 SPI Baud Rate Generation 271 15 2 External Signal Description 272 15 2 1 SPSCK SPI Serial Clock 272 15 2 2 MOSI Master Data Out Slave Data In 272 15 2 3 MISO Master Data In Slave Data Out 272 15 2 4 SS Slave Select 272 15 3 Modes of Operation 273 15 3 1 SPI in Stop Modes...

Page 16: ...nSC 295 16 3 5 TPM Channel Value Registers TPMxCnVH TPMxCnVL 296 16 4 Functional Description 298 16 4 1 Counter 298 16 4 2 Channel Mode Selection 300 16 5 Reset Overview 303 16 5 1 General 303 16 5 2 Description of Reset Operation 303 16 6 Interrupts 303 16 6 1 General 303 16 6 2 Description of Interrupt Operation 304 Chapter 17 Development Support 17 1 Introduction 307 17 1 1 Forcing Active Backg...

Page 17: ...Block Diagram 322 18 2 Signal Description 322 18 3 Memory Map and Registers 323 18 3 1 Module Memory Map 323 18 3 2 324 18 3 3 Register Descriptions 325 18 4 Functional Description 338 18 4 1 Comparator 338 18 4 2 Breakpoints 339 18 4 3 Trigger Selection 339 18 4 4 Trigger Break Control TBC 340 18 4 5 FIFO 343 18 4 6 Interrupt Priority 344 18 5 Resets 344 18 6 Interrupts 345 18 7 Electrical Specif...

Page 18: ...E128 Series of MCUs t Table 1 1 MC9S08QE128 Series Features by MCU and Package Feature MC9S08QE128 MC9S08QE96 MC9S08QE64 Flash size bytes 131 072 98 304 65 536 RAM size bytes 8064 6016 4096 Pin quantity 80 64 48 44 80 64 48 44 64 48 44 32 ACMP1 yes ACMP2 yes ADC channels 24 22 10 10 24 22 10 10 22 10 10 10 DBG yes ICS yes IIC1 yes IIC2 yes yes no no yes yes no no yes no no no IRQ yes KBI 16 16 16 ...

Page 19: ...Chapter 1 Device Overview MC9S08QE128 MCU Series Reference Manual Rev 2 20 Freescale Semiconductor 1 2 MCU Block Diagram The block diagram in Figure 1 1 shows the structure of the MC9S08QE128 Series MCU ...

Page 20: ...A1 XTAL PTB7 SCL1 EXTAL PTC3 TPM3CH3 PTC4 TPM3CH4 RSTO PTC5 TPM3CH5 ACMP2O PTC2 TPM3CH2 PTC1 TPM3CH1 PTC0 TPM3CH0 PORT C PTC6 RxD2 ACMP2 PTC7 TxD2 ACMP2 PTD3 KBI2P3 SS2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13 PTF4 ADP14 PTF5 ADP15 PTF2 AD...

Page 21: ...g Comparator ACMPVLP 1 12 bit Analog to Digital Converter ADC12 1 Central Processor Unit CPU 4 General Purpose I O GPIO 2 Inter Integrated Circuit IIC 2 Internal Clock Source ICS 3 Keyboard Interrupt KBI 2 Low Power Oscillator XOSCVLP 1 On Chip In Circuit Debug Emulator DBG 3 Port Set Clear PSC 1 Real Time Counter RTC 1 Serial Communications Interface SCI 4 Serial Peripheral Interface SPI 3 Timer ...

Page 22: ...08ICSV3 explains the ICSERCLK in more detail See Chapter 10 Analog to Digital Converter S08ADC12V1 for more information regarding the use of ICSERCLK with these modules ICSIRCLK This is the internal reference clock and can be selected as the real time counter clock source The Internal Reference Clock section in Chapter 11 Internal Clock Source S08ICSV3 explains the ICSERCLK in more detail See Chap...

Page 23: ...The fixed frequency clock FFCLK is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency Flash has frequency requirements for program and erase operation See the data sheet for details ADC has min and max frequency requirements See the ADC chapter and data sheet for details XOSC EXTAL XTAL SPI1 FFCLK ICSFFCLK RTC 1 kHZ LPO TPM1CLK ICSIRCLK 2 IIC2 IIC1 DBG...

Page 24: ...nd Connections This section describes signals that connect to package pins It includes pinout diagrams recommended system connections and detailed discussions of signals 2 1 Device Pin Assignment This section shows the pin assignments for MC9S08QE128 Series devices in the available packages ...

Page 25: ...BI2P7 PTC0 TPM3CH0 PTC1 TPM3CH1 PTD6 KBI2P6 PTD5 KBI2P5 PTB3 KBI1P7 MOSI1 ADP7 PTB2 KBI1P6 SPSCK1 ADP6 PTE5 PTF7 ADP17 PTF6 ADP16 PTF5 ADP15 PTF4 ADP14 PTD4 KBI2P4 VDD VSS PTA7 TPM2CH2 ADP9 PTB1 KBI1P5 TxD1 ADP5 PTB0 KBI1P4 RxD1 ADP4 PTA2 KBI1P2 SDA1 ADP2 PTA3 KBI1P3 SCL1 ADP3 PTA6 TPM1CH2 ADP8 PTD3 KBI2P3 SS2 PTD2 KBI2P2 MISO2 PTE4 PTF0 ADP10 PTF1 ADP11 PTF2 ADP12 PTF3 ADP13 PTE2 MISO1 PTA5 IRQ T...

Page 26: ...3CH0 PTC1 TPM3CH1 PTD6 KBI2P6 PTD5 KBI2P5 PTB3 KBI1P7 MOSI1 ADP7 PTB2 KBI1P6 SPSCK1 ADP6 PTE5 PTD4 KBI2P4 VDD VSS PTA7 TPM2CH2 ADP9 PTB1 KBI1P5 TxD1 ADP5 PTB0 KBI1P4 RxD1 ADP4 PTA2 KBI1P2 SDA11 ADP2 PTA3 KBI1P3 SCL1 ADP3 PTA6 TPM1CH2 ADP8 PTD3 KBI2P3 SS2 PTD2 KBI2P2 MISO2 PTE4 PTE2 MISO1 PTA5 IRQ TPM1CLK RESET PTA4 ACMP1O BKGD MS PTA0 KBI1P0 TPM1CH0 ADP0 ACMP1 PTA1 KBI1P1 TPM2CH0 ADP1 ACMP1 PTC7 T...

Page 27: ...M1CH1 SS1 PTC3 TPM3CH3 PTD7 KBI2P7 PTC0 TPM3CH0 PTC1 TPM3CH1 PTD6 KBI2P6 PTD5 KBI2P5 PTB3 KBI1P7 MOSI1 ADP7 PTB2 KBI1P6 SPSCK1 ADP6 PTE5 PTD4 KBI2P4 VDD VSS PTA7 TPM2CH2 ADP9 PTB1 KBI1P5 TxD1 ADP5 PTB0 KBI1P4 RxD1 ADP4 PTA2 KBI1P2 SDA1 ADP2 PTA3 KBI1P3 SCL1 ADP3 PTA6 TPM1CH2 ADP8 PTD3 KBI2P3 SS2 PTD2 KBI2P2 MISO2 PTE4 PTE2 MISO1 PTA5 IRQ TPM1CLK RESET PTA4 ACMP1O BKGD MS PTA0 KBI1P0 TPM1CH0 ADP0 A...

Page 28: ...C3 TPM3CH3 PTA5 IRQ TPM1CLK RESET PTA4 ACMP1O BKGD MS PTD7 KBI2P7 PTC0 TPM3CH0 PTC1 TPM3CH1 VDD VSS PTD6 KBI2P6 PTD5 KBI2P5 PTA0 KBI1P0 TPM1CH0 ADP0 ACMP1 PTA1 KBI1P1 TPM2CH0 ADP1 ACMP1 PTC7 TxD2 ACMP2 PTC5 TPM3CH5 ACMP2O PTC4 TPM3CH4 RSTO PTC6 RxD2 ACMP2 PTA7 TPM2CH2 ADP9 PTB3 KBI1P7 MOSI1 ADP7 PTB2 KBI1P6 SPSCK1 ADP6 PTB1 KBI1P5 TxD1 ADP5 PTB0 KBI1P4 RxD1 ADP4 PTA2 KBI1P2 SDA1 ADP2 PTA3 KBI1P3 S...

Page 29: ...4 ACMP1O BKGD MS PTA7 TPM2CH2 ADP9 PTA0 KBIP0 TPM1CH0 ADP0 ACMP1 PTC0 TPM3CH0 PTB3 KBI1P7 MOSI1 ADP7 PTB2 KBI1P6 SPSCK1 ADP6 PTB1 KBI1P5 TxD1 ADP5 PTB0 KBI1P4 RxD1 ADP4 PTA2 KBIP2 SDA1 ADP2 PTA3 KBIP3 SCL1 ADP3 PTA1 KBIP1 TPM2CH0 ADP1 ACMP1 PTC1 TPM3CH1 PTC2 TPM3CH2 PTB4 TPM2CH1 MISO1 PTC7 TxD2 ACMP2 PTB6 SDA1 XTAL PTB5 TPM1CH1 SS1 PTC5 TPM3CH5 ACMP2O PTC4 TPM3CH4 RSTO PTC3 TPM3CH3 PTD0 KBI2P0 SPS...

Page 30: ... and Connections MC9S08QE128 MCU Series Reference Manual Rev 2 Freescale Semiconductor 31 2 2 Recommended System Connections Figure 2 6 shows pin connections that are common to MC9S08QE128 Series application systems ...

Page 31: ...KBI2P6 PTD7 KBI2P7 PORT E PTE0 TCLK2 SPSCK1 PTE1 MOSI1 PTE2 MISO1 PTE3 SS1 PTE4 PTE5 PTE6 PTE7 TPM3CLK PORT H PTH0 PTH1 PTH2 PTH3 PTH4 PTH5 PTH6 SCL2 PTH7 SDA2 MC9S08QE128 VREFH VREFL CBYAD 0 1 μF VSSA VDDA PTC7 TxD2 ACMP2 VDD VSS CBY 0 1 μF CBLK 10 μF 3 V PORT PTF0 ADP10 PTF1 ADP11 PTF2 ADP12 PTF3 ADP13 PTF4 ADP14 PTF5 ADP15 PTF6 ADP16 PTF7 ADP17 PORT F PTG0 PTG1 PTG2 ADP18 PTG3 ADP19 PTG4 ADP20 ...

Page 32: ...e oscillator that can accommodate a crystal or ceramic resonator Optionally an external clock source can be connected to the EXTAL input pin The oscillator can be configured to run in stop2 or stop3 modes Refer to Figure 2 6 for the following discussion RS when used and RF should be low inductance resistors such as carbon composition resistors Wire wound resistors and some metal film resistors hav...

Page 33: ...utomatically configured as an output only The RSTO pin can be enabled independently of the RESET pin 2 2 4 Background Mode Select BKGD MS During a power on reset POR or background debug force reset see Section 5 8 3 System Background Debug Force Reset Register SBDFR for more information the PTA4 ACMPO BKGD MS pin functions as a mode select pin Immediately after any reset the pin functions as the b...

Page 34: ...tput software can select one of two drive strengths and enable or disable slew rate control When a port pin is configured as a general purpose input or a peripheral uses the port pin as an input software can enable a pull up device Immediately after reset all of these pins are configured as high impedance general purpose inputs with internal pull up devices disabled PTA5 is a special case input pi...

Page 35: ...REFH 11 9 7 7 5 VREFL 12 10 8 8 VSSA 13 11 9 9 6 VSS 14 12 10 10 7 PTB7 SCL11 EXTAL 15 13 11 11 8 PTB6 SDA11 XTAL 16 PTH3 17 PTH2 18 14 PTH1 19 15 PTH0 20 16 12 PTE6 21 17 13 PTE5 22 18 14 12 9 PTB5 TPM1CH1 SS12 23 19 15 13 10 PTB4 TPM2CH1 MISO12 24 20 16 14 11 PTC3 TPM3CH3 25 21 17 15 12 PTC2 TPM3CH2 26 22 18 16 PTD7 KBI2P7 27 23 19 17 PTD6 KBI2P6 28 24 20 18 PTD5 KBI2P5 29 PTJ7 30 PTJ6 31 PTJ5 3...

Page 36: ...1 ADP3 60 48 36 33 24 PTA2 KBI1P2 SDA11 ADP2 61 49 37 34 25 PTA1 KBI1P1 TPM2CH0 ADP13 ACMP1 3 62 50 38 35 26 PTA0 KBI1P0 TPM1CH0 ADP03 ACMP1 3 63 51 39 36 27 PTC7 TxD2 ACMP2 64 52 40 37 28 PTC6 RxD2 ACMP2 65 PTG7 ADP23 66 PTG6 ADP22 67 PTG5 ADP21 68 PTG4 ADP20 69 53 41 PTE3 SS12 70 54 42 38 PTE2 MISO12 71 55 PTG3 ADP19 72 56 PTG2 ADP18 73 57 PTG1 74 58 PTG0 75 59 43 39 PTE1 MOSI12 76 60 44 40 PTE0...

Page 37: ...C1 pins SCL1 and SDA1 can be repositioned using IIC1PS in SOPT2 Default locations are PTA3 and PTA respectively 2 SPI1 pins SS1 MISO1 MOSI1 and SPSCK1 can be repositioned using SPI1PS in SOPT2 Default locations are PTB5 PTB4 PTB3 and PTB2 3 If ADC and ACMP1 are enabled both modules will have access to the pin ...

Page 38: ...r is in standby Stop modes System clocks are stopped and voltage regulator is in standby Stop3 All internal circuits are powered for fast recovery Stop2 Partial power down of internal circuits RAM content is retained I O states are held 3 3 Run Mode This is the normal operating mode for the MC9S08QE128 Series In this mode the CPU executes code from internal memory with execution beginning at the a...

Page 39: ...un at full speed in any clock mode 3 3 1 1 Interrupts in Low Power Run Mode Low power run mode provides the option to return to full regulation if any interrupt occurs This is done by setting the LPWUI bit in the SPMSC2 register The ICS can then be set for full speed immediately in the interrupt service routine If the LPWUI bit is clear interrupts will be serviced in low power run mode If the LPWU...

Page 40: ...gram is running Non intrusive commands can be issued through the BKGD pin while the MCU is in run mode non intrusive commands can also be executed when the MCU is in the active background mode Non intrusive commands include Memory access commands Memory access with status commands BDC register access commands The BACKGROUND command Active background commands which can only be executed while the MC...

Page 41: ...consumption is reduced to a minimum that still allows most modules to maintain functionality Power consumption is reduced the most by disabling the clocks to all unused peripherals by clearing the corresponding bits in the SCGC register The same restrictions from the low power run mode apply to low power wait mode 3 5 1 1 Interrupts in Low Power Wait Mode If the LPWUI bit is set when the WAIT inst...

Page 42: ... gain oscillator XOSCVLP Upon entering stop2 all I O pin control signals are latched so that the pins retain their states during stop2 3 6 1 3 Exit from Stop2 Exit from stop2 is performed by asserting the wake up pin PTA5 IRQ TCLK RESET on the MCU NOTE PTA5 IRQ TPM1CLK RESET functions as an active low wakeup input when the MCU is in stop2 The pullup on this pin is not automatically enabled in stop...

Page 43: ...n PPDACK is written Peripheral I O For pins that were configured as peripheral I O the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit If the peripheral module is not enabled before writing to PPDACK the pins will be controlled by their associated port control registers when the I O latches are opened NOTE The RSTPE bit will be cleared by the...

Page 44: ...ting that the MCU is in either stop or wait mode The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set After entering background debug mode all background commands are available 3 6 4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage If t...

Page 45: ... 1 1 1 x x x on LPWAIT mode Assumes WAIT instruction executed 0 0 x 1 0 CPU clock is off peripheral clocks at low speed ICS in FBELP mode off standby 1 0 STOP3 Assumes STOPE bit is set and STOP instruction executed Note that STOP3 is used in place of STOP2 if the BDM or LVD is enabled 0 0 x x 0 ICS in STOP LPO OSCOUT ICSERCLK and ICSIRCLK optionally on2 2 Configured within the ICS module based on ...

Page 46: ...transitions shown in Figure 3 1 Table 3 3 Triggers for Transitions Shown in Figure 3 1 Transition From To Trigger 1 RUN LPRUN Configure settings shown in Table 3 1 switch LPR 1 last LPRUN RUN Clear LPR Interrupt when LPWUI 1 2 RUN STOP2 Pre configure settings shown in Table 3 1 issue STOP instruction STOP2 RUN Assert zero on PTA5 IRQ TPM1CLK RESET1 reload environment from RAM 3 LPRUN LPWAIT WAIT i...

Page 47: ...3 RUN Interrupt if LPR 0 or LPR 1 and LPWUI 1 or reset RUN STOP3 STOP instruction 1 An analog connection from this pin to the on chip regulator will wake up the regulator which will then initiate a power on reset sequence Table 3 4 Stop and Low Power Mode Behavior Peripheral Mode Stop2 Stop3 LPWait LPRun CPU Off Standby Standby On RAM Standby Standby Standby On Flash Off Standby Standby On Port I ...

Page 48: ...erence 3 If ENBDM is set when entering stop2 the MCU will actually enter stop3 4 If ENBDM is set when entering LPRun or LPWait the MCU will actually stay in run mode or enter wait mode respectively 5 IRCLKEN and IREFSTEN set in ICSC1 else in standby 6 ICS must be configured for FBELP bus frequency limited to 125kHz in LPRUN or LPWAIT 7 If LVDSE is set when entering stop2 the MCU will actually ente...

Page 49: ...Chapter 3 Modes of Operation MC9S08QE128 MCU Series Reference Manual Rev 2 50 Freescale Semiconductor ...

Page 50: ...x08000 0x0BFFF 0x0C000 0x0FFFF When the CPU accesses PPAGE 0 directly RAM and registers when present take priority over flash memory Extended Address CPU Address Extended Address 0xFFFF 0x7FFF 0xC000 0x4000 0xBFFF 0x8000 Paging Window Extended address es formed with PPAGE and A13 A0 of CPU ad dress When PPAGE 0 is accessed through the linear address pointer or through the paging window the flash m...

Page 51: ...x1FFFF DIRECT PAGE RAM 6016 BYTES 0x0000 0x007F 0x0080 0x1800 0x17FF 0x187F 0x0FFFF 128 BYTES HIGH 128 BYTES FLASH 16384 BYTES 0x1880 RAM 2048 BYTES 0x207F 0x3FFF 0x2080 FLASH 8064 BYTES 16384 BYTES 0x07FFF 0x0C000 0x04000 REGISTERS 0x0BFFF 0x08000 PAGE REGISTERS PPAGE 1 FLASH 16384 BYTES PPAGE 0 FLASH FLASH 16384 BYTES PPAGE 3 PPAGE 0 PPAGE 1 PPAGE 2 PPAGE 3 0x00000 0x03FFF 0x00000 0x03FFF 0x0400...

Page 52: ...H 8064 BYTES 16384 BYTES 0x07FFF 0x0C000 0x04000 REGISTERS 0x0BFFF 0x08000 PAGE REGISTERS PPAGE 1 FLASH 16384 BYTES PPAGE 0 FLASH FLASH 16384 BYTES PPAGE 3 PPAGE 0 PPAGE 1 PPAGE 2 PPAGE 3 0x00000 0x03FFF 0x00000 0x03FFF 0x04000 0x07FFF 0x08000 0x0BFFF 0x0C000 0x0FFFF When the CPU accesses PPAGE 0 directly RAM and registers when present take priority over flash memory Extended Address CPU Address E...

Page 53: ...D 16384 BYTES PPAGE 4 PPAGE 5 0x10000 0x13FFF 0x14000 0x17FFF Extended Address RESERVED 16384 BYTES 0x18000 0x1BFFF DIRECT PAGE RAM 4096 BYTES 0x0000 0x007F 0x0080 0x1080 0x107F 0x187F 0x0FFFF 128 BYTES HIGH 128 BYTES FLASH 16384 BYTES 0x1880 RESERVED 2048 BYTES 0x207F 0x3FFF 0x2080 FLASH 8064 BYTES 16384 BYTES 0x07FFF 0x0C000 0x04000 REGISTERS 0x0BFFF 0x08000 PAGE REGISTERS PPAGE 1 FLASH 16384 BY...

Page 54: ...TPM2 Channel 1 Vtpm2ch1 0xFFEE 0xFFEF TPM2 Channel 0 Vtpm2ch0 0xFFF0 0xFFF1 TPM1 Overflow Vtpm1ovf 0xFFF2 0xFFF3 TPM1 Channel 2 Vtpm1ch2 0xFFF4 0xFFF5 TPM1 Channel 1 Vtpm1ch1 0xFFF6 0xFFF7 TPM1 Channel 0 Vtpm1ch0 0xFFF8 0xFFF9 Low Voltage Detect or Low Voltage Warning Vlvd 0xFFFA 0xFFFB IRQ Virq 0xFFFC 0xFFFD SWI Vswi 0xFFFE 0xFFFF Reset Vreset 1 ACMP1 and ACMP2 share this vector if both modules a...

Page 55: ...cations are flash memory they must be erased and programmed like other flash memory locations Direct page registers can be accessed with efficient direct addressing mode instructions Bit manipulation instructions can be used to access any bit in any direct page register Table 4 2 is a summary of all user accessible direct page registers and control bits The direct page registers in Table 4 2 can u...

Page 56: ... 0x0010 ADCSC1 COCO AIEN ADCO ADCH 0x0011 ADCSC2 ADACT ADTRG ACFE ACFGT Reserved Reserved 0x0012 ADCRH 0 0 0 0 ADR11 ADR10 ADR9 ADR8 0x0013 ADCRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0x0014 ADCCVH 0 0 0 0 ADCV11 ADCV10 ADCV9 ADCV8 0x0015 ADCCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 0x0016 ADCCFG ADLPC ADIV ADLSMP MODE ADICLK 0x0017 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC...

Page 57: ...E6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0x003E KBI2ES KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 0x003F Reserved 0x0040 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0041 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0042 TPM1CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0043 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0044 TPM1MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0045 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B E...

Page 58: ...3C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0066 TPM3C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0067 TPM3C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0068 TPM3C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0069 TPM3C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x006A TPM3C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x006B TPM3C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0 0x006C TPM3C2VH Bit 15 14 13 12 11 10 9 Bit 8 0x006D TPM3C2VL Bit 7 6 5 4 3 2 1...

Page 59: ...7 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x1808 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0 BGBE 0x1809 SPMSC2 LPR LPRS LPWUI 0 PPDF PPDACK PPDE PPDC 0x180A Reserved 0x180B SPMSC3 LVWF LVWACK LVDV LVWV LVWIE 0x180C Reserved 0x180D Reserved 0x180E SCGC1 TPM3 TPM2 TPM1 ADC IIC2 IIC1 SCI2 SCI1 0x180F SCGC2 DBG FLS IRQ KBI ACMP RTC SPI2 SPI1 0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8 0x1811 DBGCAL Bit...

Page 60: ...PTAPE3 PTAPE2 PTAPE1 PTAPE0 0x1841 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0x1842 PTADS PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 0x1843 Reserved 0x1844 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0x1845 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 0x1846 PTBDS PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 0x1847 Rese...

Page 61: ...TJSE1 PTJSE0 0x1862 PTJDS PTJDS7 PTJDS6 PTJDS5 PTJDS4 PTJDS3 PTJDS2 PTJDS1 PTJDS0 0x1863 0x1867 Reserved 0x1868 IIC2A AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 0x1869 IIC2F MULT ICR 0x186A IIC2C1 IICEN IICIE MST TX TXAK RSTA 0 0 0x186B IIC2S TCF IAAS BUSY ARBL 0 SRW IICIF RXAK 0x186C IIC2D DATA 0x186D IIC2C2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8 0x186E 0x186F Reserved 0x1870 SCI2BDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR1...

Page 62: ...ded the key enable KEYEN bit is 1 the 8 byte comparison key can be used to temporarily disengage memory security This key mechanism can be accessed only through user code running in secure memory A security key cannot be entered directly through background debug commands This security key can be disabled completely by programming the KEYEN bit to 0 If the security key is disabled the only way to d...

Page 63: ...chitecture supports up to 256 16K pages Extended data space using linear address pointer up to 22 bit linear address pointer linear address pointer and data register provided in direct page allows access of complete flash memory map using direct page instructions optional auto increment of pointer when data accessed supports an 2s compliment addition subtraction to address pointer without using an...

Page 64: ...AP0 make up the extended address of the flash memory location to be addressed When accessing data using LWP the contents of LAP2 LAP0 will increment after the read or write is complete 7 6 5 4 3 2 1 0 R 0 0 0 0 0 XA16 XA15 XA14 W Reset 0 0 0 0 0 0 1 0 Figure 4 4 Program Page Register PPAGE Table 4 5 Program Page Register Field Descriptions Field Description 2 0 XA16 XA14 When the CPU addresses the...

Page 65: ... 0 0 0 0 0 0 0 Figure 4 6 Linear Word Post Increment Register LWP Table 4 7 Linear Word Post Increment Register Field Descriptions Field Description 7 0 D7 D0 Reads of this register will first return the data value pointed to by the linear address pointer LAP2 LAP0 and then will increment LAP2 LAP0 Writes to this register will first write the data value to the memory location specified by the line...

Page 66: ...d at 0x8000 0xBFFF The MMU module also provides a linear address pointer that allows extension of data access up to 4M bytes 7 6 5 4 3 2 1 0 R D7 D6 D5 D4 D3 D2 D1 D0 W Reset 0 0 0 0 0 0 0 0 Figure 4 8 Linear Byte Register LB Table 4 9 Linear Data Register Field Descriptions Field Description 7 0 D7 D0 Reads of this register returns the data value pointed to by the linear address pointer LAP2 LAP0...

Page 67: ... program CALL is similar to a JSR instruction but the subroutine that is called can be located anywhere in the normal 64K byte address space or on any page of program memory During the execution of a CALL instruction the CPU Stacks the return address Pushes the current PPAGE value onto the stack Writes the new instruction supplied PPAGE value into the PPAGE register Transfers control to the subrou...

Page 68: ...The three linear data registers access the memory locations in the same way however the LBP and LWP will also increment LAP2 LAP0 Accessing either the LBP or LWP registers allows a user program to read successive memory locations without re writing the linear address pointer Accessing LBP or LWP does the exact same function However because of the address mapping of the registers with LBP following...

Page 69: ...urity for a detailed description of the security feature 4 6 Flash The flash memory is intended primarily for program storage In circuit programming allows the operating program to be loaded into the flash memory after final assembly of the application product It is possible to program the entire array through the single wire background debug interface Because no special voltages are needed for fl...

Page 70: ... prevent accidental program or erase Security feature to prevent unauthorized access to the flash and RAM Auto power down for low frequency read accesses 4 6 2 Register Descriptions The flash module contains a set of 16 control and status registers Detailed descriptions of each register bit are provided in the following sections 4 6 2 1 Flash Clock Divider Register FCDIV The FCDIV register is used...

Page 71: ...e value of the FDIVLD bit read indicates the following 0 FCDIV register has not been written to since the last reset 1 FCDIV register has been written to since the last reset 6 PRDIV8 Enable Prescaler by 8 0 The bus clock is directly fed into the clock divider 1 The bus clock is divided by 8 before feeding into the clock divider 5 0 FDIV 5 0 Clock Divider Bits The combination of PRDIV8 and FDIV 5 ...

Page 72: ... Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor key access to the flash module as shown in Table 4 14 1 0 SEC 1 0 Flash Security Bits The SEC 1 0 bits define the security state of the MCU as shown in Table 4 15 If the flash module is unsecured using backdoor key access the SEC 1 0 bits are forced to the unsecured state Table 4 1...

Page 73: ...during the reset sequence the flash sector containing NVPROT must be unprotected and erased then NVPROT can be reprogrammed Trying to alter data in any protected area in the flash memory will result in a protection violation error and the FPVIOL flag will be set in the FSTAT register The mass erase of the flash array is not possible if any of the flash sectors contained in the flash array are prot...

Page 74: ...tes 0x38 0x0_0000 0x0_FFFF 0x1_E400 0x1_FFFF 71 Kbytes 0x39 0x0_0000 0x0_FFFF 0x1_E800 0x1_FFFF 70 Kbytes 0x3A 0x0_0000 0x0_FFFF 0x1_EC00 0x1_FFFF 69 Kbytes 0x3B 0x0_0000 0x0_FFFF 0x1_F000 0x1_FFFF 68 Kbytes 0x3C 0x0_0000 0x0_FFFF 0x1_F400 0x1_FFFF 67 Kbytes 0x3D 0x0_0000 0x0_FFFF 0x1_F800 0x1_FFFF 66 Kbytes 0x3E 0x0_0000 0x0_FFFF 0x1_FC00 0x1_FFFF 65 Kbytes 0x3F 0x0_0000 0x0_FFFF 64 Kbytes 0x40 0...

Page 75: ...Writing a 0 to FCBEF outside of a command write sequence will not set the FACCERR flag The FCBEF flag is cleared by writing a 1 to FCBEF 0 Command buffers are full 1 Command buffers are ready to accept a new command 6 FCCF Flash Command Complete Interrupt Flag The FCCF flag indicates that there are no more commands pending The FCCF flag is cleared when FCBEF is cleared and sets automatically upon ...

Page 76: ... sequence 0 No access error detected 1 Access error has occurred 2 FBLANK Flash Flag Indicating the Erase Verify Operation Status When the FCCF flag is set after completion of an erase verify command the FBLANK flag indicates the result of the erase verify operation The FBLANK flag is cleared by the flash module when FCBEF is cleared as part of a new valid command write sequence Writing to the FBL...

Page 77: ... ensure that FACCERR is not set before writing to the FCDIV register One period of the resulting clock 1 fFCLK is used by the command processor to time program and erase pulses An integer number of these timing pulses are used by the command processor to complete a program or erase command Table 4 22 shows program and erase times The bus clock frequency and FCDIV determine the frequency of FCLK fF...

Page 78: ...in the FSTAT register by writing a 1 to FCBEF to launch the command Once a command is launched the completion of the command operation is indicated by the setting of the FCCF flag in the FSTAT register The FCCF flag will set upon completion of all active and buffered burst program commands 4 6 3 2 Flash Commands Table 4 23 summarizes the valid flash commands along with the effects of the commands ...

Page 79: ... FSTAT register by writing a 1 to FCBEF to launch the erase verify command After launching the erase verify command the FCCF flag in the FSTAT register will set after the operation has completed The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in the flash array memory plus several bus cycles as measured from the time the FCBEF flag is cle...

Page 80: ...l be programmed to the address written 2 Write the program command 0x20 to the FCMD register Write Flash Block Address Write FCMD register Write FSTAT register 1 2 3 Write FSTAT register yes no Access Error and no Bit Polling for Read FSTAT register yes Read FSTAT register no START yes FCBEF Set Command FCCF Set FACCERR FPVIOL Set no Erase Verify yes EXIT Flash Block FBLANK Set Write FCDIV registe...

Page 81: ...n embedded algorithm While burst programming two internal data registers operate as a buffer and a register 2 stage FIFO so that a second burst programming command along with the necessary data can be stored to the buffers while the first burst programming command is still in progress This pipelined operation allows a time Write Flash Array Address Write FCMD register Write FSTAT register 1 2 3 Wr...

Page 82: ...incremented internally The burst program procedure can be used to program an entire flash array even while crossing row boundaries within the flash array However the burst program command cannot cross array boundaries The array boundary for this MCU occurs between extended addresses 0x0FFFF and 0x10000 At least two burst commands are required to program the entire 128K of flash memory If data to b...

Page 83: ...ter yes no Access Error and no Bit Polling for Read FSTAT register yes Read FSTAT register no START yes FCBEF Set Command FCCF Set FACCERR FPVIOL Set Write FCDIV register Read FCDIV register yes no Clock Register FDIVLD Set NOTE FCDIV needs to Written Check Protection Violation Check Buffer Empty Check and Program Data Burst Program Command 0x25 Clear FCBEF 0x80 Clear FACCERR FPVIOL 0x30 Command C...

Page 84: ...otected area of the flash block the FPVIOL flag in the FSTAT register will set and the sector erase command will not launch Once the sector erase command has successfully launched the FCCF flag in the FSTAT register will set after the sector erase operation has completed Figure 4 19 Example Sector Erase Command Flow Write Flash Sector Address Write FCMD register Write FSTAT register 1 2 3 Write FS...

Page 85: ...ation is active The operation is aborted immediately and if burst programming any pending burst program command is purged see Section 4 6 4 2 Stop Mode The FACCERR flag will not be set if any flash register is read during a valid command write sequence If the flash memory is read during execution of an algorithm FCCF 0 the read operation will return invalid data and the FACCERR flag will not be se...

Page 86: ... listed in Table 4 23 can be executed 4 6 5 Flash Module Security The MC9S08QE128 Series includes circuitry to prevent unauthorized access to the contents of flash and RAM memory When security is engaged flash and RAM are considered secure resources Direct page registers high page registers and the background debug controller are considered unsecured resources Programs executing within secure memo...

Page 87: ... cycle NOP may be required before clearing the KEYACC bit 4 If all data written match the backdoor keys the MCU is unsecured and the SEC 1 0 bits in the FOPT register are forced to the unsecure state of 1 0 The backdoor key access sequence is monitored by an internal security state machine An illegal operation during the backdoor key access sequence will cause the security state machine to lock le...

Page 88: ...in the flash protection register FPROT It is not possible to unsecure the MCU in special mode by using the backdoor key access sequence in background debug mode BDM 4 6 6 Resets If a reset occurs while any flash command is in progress that command will be immediately aborted The state of the flash array address being programmed or the sector block being erased is not guaranteed ...

Page 89: ...ent reset Separate interrupt vector for most modules reduces polling overhead see Table 5 2 5 3 MCU Reset Resetting the MCU provides a way to start processing from a known set of initial conditions During reset most control and status registers are forced to initial values and the program counter is loaded from the reset vector 0xFFFE 0xFFFF On chip peripheral modules are disabled and I O pins are...

Page 90: ... either the bus clock or an internal 1 kHz clock source With each clock source there is an associated short and long time out controlled by COPT in SOPT1 Table 5 1 summaries the control functions of the COPCLKS and COPT bits The COP watchdog defaults to operation from the 1 kHz clock source and the associated long time out 28 cycles Even if the application will use the reset default settings of CO...

Page 91: ...struction and consists of Saving the CPU registers on the stack Setting the I bit in the CCR to mask further interrupts Fetching the interrupt vector for the highest priority interrupt that is currently pending Filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations While the CPU is responding to the inte...

Page 92: ...he stack in reverse order As part of the RTI sequence the CPU fills the instruction pipeline by reading three bytes of program information starting from the PC address recovered from the stack The status flag corresponding to the interrupt source must be acknowledged cleared before returning from the ISR Typically the flag is cleared at the beginning of the ISR so that if another interrupt is gene...

Page 93: ... this pin are pulled to VDD The RESET pullup should not be used to pullup components external to the MCU 5 5 2 2 Edge and Level Sensitivity The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels In the edge and level detection mode the IRQF status flag becomes set when an edge is detected when the IRQ pin changes from the deasserted to the asserted level b...

Page 94: ...er address When an interrupt condition occurs an associated flag bit becomes set If the associated local interrupt enable is 1 an interrupt request is sent to the CPU Within the CPU if the global interrupt mask I bit in the CCR is 0 the CPU will finish the current instruction stack the PCL PCH X A and CCR CPU registers set the I bit and then fetch the interrupt vector for the highest priority pend...

Page 95: ...f both modules are enabled user should poll each flag to determine pending interrupt KBF KBIE Keyboard x pins 17 0xFFDC 0xFFDD Viicx IICx3 3 IIC1 and IIC2 share this vector if both modules are enabled user should poll each flag to determine pending interrupt IICIS IICIE IICx control 16 0xFFDE 0xFFDF Vsci1tx SCI1 TDRE TC TIE TCIE SCI1 transmit 15 0xFFE0 0xFFE1 Vsci1rx SCI1 IDLE LBKDIF RDRF RXEDGIF ...

Page 96: ...g LVDRE to 1 The low voltage detection threshold is determined by the LVDV bit After an LVD reset has occurred the LVD system will hold the MCU in reset until the supply voltage has risen above the low voltage detection threshold The LVD bit in the SRS register is set following either an LVD reset or POR 5 6 3 Low Voltage Detection LVD Interrupt Operation When a low voltage condition is detected a...

Page 97: ...ely following the write to the Clock Gating Control registers SCGC1 and SCGC2 Any peripheral with a gated clock can not be used unless its clock is enabled Writing to the registers of a peripheral with a disabled clock has no effect NOTE User software should disable the peripheral before disabling the clocks to the peripheral When clocks are re enabled to a peripheral the peripheral registers need...

Page 98: ...ACK Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 5 2 Interrupt Request Status and Control Register IRQSC Table 5 3 IRQSC Register Field Descriptions Field Description 6 IRQPDD Interrupt Request IRQ Pull Device Disable This read write control bit is used to disable the internal pull up pull down device when the IRQ pin is enabled IRQPE 1 allowing for an external device to be used 0 IRQ pu...

Page 99: ...IE IRQ Interrupt Enable This read write control bit determines whether IRQ events generate an interrupt request 0 Interrupt request when IRQF set is disabled use polling 1 Interrupt requested whenever IRQF 1 0 IRQMOD IRQ Detection Mode This read write control bit selects either edge only detection or edge and level detection The IRQEDG control bit determines the polarity of edges and levels that a...

Page 100: ...tive low level on the external reset pin 0 Reset not caused by external reset pin 1 Reset came from external reset pin 5 COP Computer Operating Properly COP Watchdog Reset was caused by the COP watchdog timer timing out This reset source can be blocked by COPE 0 0 Reset not caused by COP timeout 1 Reset caused by COP timeout 4 ILOP Illegal Opcode Reset was caused by an attempt to execute an unimpl...

Page 101: ...TE_BYTE command See the data sheet for more information 7 6 5 4 3 2 1 0 R COPE COPT STOPE 0 0 RSTOPE BKGDPE RSTPE W Reset 1 1 0 0 0 u1 1 u unaffected 1 u1 POR 1 1 0 0 0 0 1 0 LVR 1 1 0 0 0 0 1 0 Unimplemented or Reserved Figure 5 5 System Options Register 1 SOPT1 Table 5 6 SOPT1 Register Field Descriptions Field Description 7 COPE COP Watchdog Enable This write once bit selects whether the COP wat...

Page 102: ...or TCLK 1 PTA5 IRQ TCLK RESET pin functions as RESET 7 6 5 4 3 2 1 0 R COPCLKS1 1 This bit can be written only one time after reset Additional writes are ignored 0 0 0 SPI1PS ACIC2 IIC1PS ACIC1 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 5 6 System Options Register 2 SOPT2 Table 5 7 SOPT2 Register Field Descriptions Field Description 7 COPCLKS COP Watchdog Clock Select This write once...

Page 103: ...CMP1 to TPM1 input channel 0 See Chapter 9 Analog Comparator 3V ACMPVLPV1 and Chapter 16 Timer Pulse Width Modulator S08TPMV3 for more details on this feature 0 ACMP output not connected to TPM1 input channel 0 1 ACMP output connected to TPM1 input channel 0 7 6 5 4 3 2 1 0 R ID11 ID10 ID9 ID8 W Reset 0 0 0 0 Unimplemented or Reserved Table 5 8 SDIDH Register Field Descriptions Field Description 7...

Page 104: ...t 0 0 0 1 1 1 0 0 Stop2 Wakeup u 0 u u u u 0 u Unimplemented or Reserved u Unaffected by reset Figure 5 9 System Power Management Status and Control 1 Register SPMSC1 Table 5 10 SPMSC1 Register Field Descriptions Field Description 7 LVDF Low Voltage Detect Flag Provided LVDE 1 this read only status bit indicates a low voltage detect event 6 LVDACK Low Voltage Detect Acknowledge This write only bit...

Page 105: ...eset 0 0 0 0 0 0 0 0 Stop2 Wakeup 0 0 u 0 1 0 1 1 Unimplemented or Reserved u Unaffected by reset Figure 5 10 System Power Management Status and Control 2 Register SPMSC2 Table 5 11 SPMSC2 Register Field Descriptions Field Description 7 LPR Low Power Regulator Control The LPR bit controls entry into the low power run and wait modes in which the voltage regulator is put into standby This bit cannot...

Page 106: ...PR are set in a single write instruction only PPDC will actually be set PPDE must be set in order for PPDC to be set There are restrictions on LVDE and LVDSE See Table 3 1 for details 0 Stop3 low power mode enabled 1 Stop2 partial power down mode enabled 7 6 5 4 3 2 1 0 R LVWF 0 LVDV LVWV LVWIE 0 0 0 W LVWACK POR 01 1 LVWF will be set in the case when VSupply transitions below the trip point or af...

Page 107: ...rip point voltage VLVD 0 Low trip point selected VLVD VLVDL 1 High trip point selected VLVD VLVDH 4 LVWV Low Voltage Warning Voltage Select The LVWV bit selects the LVW trip point voltage VLVW 0 Low trip point selected VLVW VLVWL 1 High trip point selected VLVW VLVWH 3 LVWIE Low Voltage Warning Interrupt Enable This bit enables hardware interrupt requests for LVWF 0 Hardware interrupt disabled use...

Page 108: ...ed 1 Bus clock to the TPM2 module is enabled 5 TPM1 TPM1 Clock Gate Control This bit controls the clock gate to the TPM1 module 0 Bus clock to the TPM1 module is disabled 1 Bus clock to the TPM1 module is enabled 4 ADC ADC Clock Gate Control This bit controls the clock gate to the ADC module 0 Bus clock to the ADC module is disabled 1 Bus clock to the ADC module is enabled 3 IIC2 IIC2 Clock Gate C...

Page 109: ... IRQ module is disabled 1 Bus clock to the IRQ module is enabled 4 KBI KBI Clock Gate Control This bit controls the clock gate to both of the KBI modules 0 Bus clock to the KBI modules is disabled 1 Bus clock to the KBI modules is enabled 3 ACMP ACMP Clock Gate Control This bit controls the clock gate to both of the ACMP modules 0 Bus clock to the ACMP modules is disabled 1 Bus clock to the ACMP m...

Page 110: ...Chapter 5 Resets Interrupts and General System Control MC9S08QE128 MCU Series Reference Manual Rev 2 110 Freescale Semiconductor ...

Page 111: ...pplication program must either enable on chip pull up devices or change the direction of unconnected pins to outputs so the pins do not float 6 1 Port Data and Data Direction Reading and writing of parallel I Os are performed through the port data registers The direction either input or output is controlled through the port data direction registers The parallel I O port function for an individual ...

Page 112: ...r each port pin by setting the corresponding bit in the pull up enable register PTxPEn The pull up device is disabled if the pin is configured as an output by the parallel I O control logic or any shared peripheral function regardless of the state of the corresponding pull up enable register bit The pull up device is also disabled if the pin is controlled by an analog function 6 2 2 Port Slew Rate...

Page 113: ...d Toggle Data Registers The Port Data Set Clear and Toggle registers provide an alternate method for setting and clearing individual port I O pins within a single port Only port C and port E have data set clear and toggle registers Figure 6 2 should be contrasted with Figure 6 1 to see the effects of adding Set Clear Toggle functionality to the port cell SET_Enable CLR_Enable and Toggle_Enable wil...

Page 114: ... I O latches are maintained in their state as before the STOP instruction was executed CPU register status and the state of I O registers should be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode Upon recovery from stop2 mode before accessing any I O the user should examine the state of the PPDF bit in the SPMSC2 register If the PPDF bit is 0 I O must be initial...

Page 115: ... the pin For port A pins that are configured as outputs reads return the last value written to this register Writes are latched into all bits of this register For port A pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTAD to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high imp...

Page 116: ...bits determines if the internal pull up or pull down device is enabled for the associated PTA pin For port A pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pull up pull down device disabled for port A bit n 1 Internal pull up pull down device enabled for port A bit n 7 6 5 4 3 2 1 0 R PTASE7 PTASE6 PTASE51 1 PTASE5 will have no e...

Page 117: ... PTA5 pin PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 W Reset 0 0 0 0 0 0 0 0 Figure 6 7 Drive Strength Selection for Port A Register PTADS Table 6 5 PTADS Register Field Descriptions Field Description 7 0 PTADS 7 0 Output Drive Strength Selection for Port A Bits Each of these control bits selects between low and high output drive for the associated PTA pin For port A pins that are configured as inputs the...

Page 118: ...ritten to this register Writes are latched into all bits of this register For port B pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTBD to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pull ups pull downs disabled 7 6 5 4 3 2 1 0 R PTBDD7 PTBDD6 PTBDD...

Page 119: ...Reset 0 0 0 0 0 0 0 0 Figure 6 11 Slew Rate Enable for Port B Register PTBSE Table 6 9 PTBSE Register Field Descriptions Field Description 7 0 PTBSE 7 0 Output Slew Rate Enable for Port B Bits Each of these control bits determines if the output slew rate control is enabled for the associated PTB pin For port B pins that are configured as inputs these bits have no effect 0 Output slew rate control ...

Page 120: ...hat are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTCD to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pull ups disabled 7 6 5 4 3 2 1 0 R PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 W Reset 0 0 0 0 0 0 0 0 Figure 6 14 Port C Data Direction Registe...

Page 121: ... C Data Clear Register PTCCLR Table 6 14 PTCCLR Register Field Descriptions Field Description 7 0 PTCCLRn Data Clear for Port C Bits Writing any bit to zero in this location will clear the corresponding bit in the data register to zero Writing a one to any bit in this register has no effect 0 Corresponding PTCDn maintains current value 1 Corresponding PTCDn is cleared 7 6 5 4 3 2 1 0 R W PTCTOG7 P...

Page 122: ...h of these control bits determines if the internal pull up device is enabled for the associated PTC pin For port C pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pull up device disabled for port C bit n 1 Internal pull up device enabled for port C bit n 7 6 5 4 3 2 1 0 R PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 W R...

Page 123: ... PTCDS1 PTCDS0 W Reset 0 0 0 0 0 0 0 0 Figure 6 20 Drive Strength Selection for Port C Register PTCDS Table 6 18 PTCDS Register Field Descriptions Field Description 7 0 PTCDS 7 0 Output Drive Strength Selection for Port C Bits Each of these control bits selects between low and high output drive for the associated PTC pin For port C pins that are configured as inputs these bits have no effect 0 Low...

Page 124: ...ritten to this register Writes are latched into all bits of this register For port D pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTDD to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pull ups pull downs disabled 7 6 5 4 3 2 1 0 R PTDDD7 PTDDD6 PTDDD...

Page 125: ...Reset 0 0 0 0 0 0 0 0 Figure 6 24 Slew Rate Enable for Port D Register PTDSE Table 6 22 PTDSE Register Field Descriptions Field Description 7 0 PTDSE 7 0 Output Slew Rate Enable for Port D Bits Each of these control bits determines if the output slew rate control is enabled for the associated PTD pin For port D pins that are configured as inputs these bits have no effect 0 Output slew rate control...

Page 126: ...hat are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTED to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pull ups disabled 7 6 5 4 3 2 1 0 R PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0 W Reset 0 0 0 0 0 0 0 0 Figure 6 27 Port E Data Direction Registe...

Page 127: ... 6 5 4 3 2 1 0 R W PTECLR7 PTECLR6 PTECLR5 PTECLR4 PTECLR3 PTECLR2 PTECLR1 PTECLR0 Reset 0 0 0 0 0 0 0 0 Figure 6 29 Port E Data Clear Register PTECLR Table 6 27 PTECLR Register Field Descriptions Field Description 7 0 PTECLRn Data Clear for Port E Bits Writing any bit to zero in this location will clear the corresponding bit in the data register to zero Writing a one to any bit in this register h...

Page 128: ...that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pull up device disabled for port E bit n 1 Internal pull up device enabled for port E bit n 7 6 5 4 3 2 1 0 R PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0 W Reset 0 0 0 0 0 0 0 0 Figure 6 32 Slew Rate Enable for Port E Register PTESE Table 6 30 PTESE Register Field Descriptions...

Page 129: ... PTEDS1 PTEDS0 W Reset 0 0 0 0 0 0 0 0 Figure 6 33 Drive Strength Selection for Port E Register PTEDS Table 6 31 PTEDS Register Field Descriptions Field Description 7 0 PTEDS 7 0 Output Drive Strength Selection for Port E Bits Each of these control bits selects between low and high output drive for the associated PTE pin For port E pins that are configured as inputs these bits have no effect 0 Low...

Page 130: ...alue written to this register Writes are latched into all bits of this register For port F pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTFD to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pull ups disabled 7 6 5 4 3 2 1 0 R PTFDD7 PTFDD6 PTFDD5 PTF...

Page 131: ... 0 0 Figure 6 37 Slew Rate Enable for Port F Register PTFSE Table 6 35 PTFSE Register Field Descriptions Field Description 7 0 PTFSE 7 0 Output Slew Rate Enable for Port F Bits Each of these control bits determines if the output slew rate control is enabled for the associated PTF pin For port F pins that are configured as inputs these bits have no effect 0 Output slew rate control disabled for por...

Page 132: ...alue written to this register Writes are latched into all bits of this register For port G pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTGD to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pull ups disabled 7 6 5 4 3 2 1 0 R PTGDD7 PTGDD6 PTGDD5 PTG...

Page 133: ... 0 0 Figure 6 42 Slew Rate Enable for Port G Register PTGSE Table 6 40 PTGSE Register Field Descriptions Field Description 7 0 PTGSE 7 0 Output Slew Rate Enable for Port G Bits Each of these control bits determines if the output slew rate control is enabled for the associated PTG pin For port G pins that are configured as inputs these bits have no effect 0 Output slew rate control disabled for por...

Page 134: ...alue written to this register Writes are latched into all bits of this register For port H pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTHD to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pull ups disabled 7 6 5 4 3 2 1 0 R PTHDD7 PTHDD6 PTHDD5 PTH...

Page 135: ... 0 0 Figure 6 47 Slew Rate Enable for Port H Register PTHSE Table 6 45 PTHSE Register Field Descriptions Field Description 7 0 PTHSE 7 0 Output Slew Rate Enable for Port H Bits Each of these control bits determines if the output slew rate control is enabled for the associated PTH pin For port H pins that are configured as inputs these bits have no effect 0 Output slew rate control disabled for por...

Page 136: ...alue written to this register Writes are latched into all bits of this register For port J pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTJD to all 0s but these 0s are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pull ups disabled 7 6 5 4 3 2 1 0 R PTJDD7 PTJDD6 PTJDD5 PTJ...

Page 137: ... Port J Register PTJSE Table 6 50 PTJSE Register Field Descriptions Field Description 7 0 PTJSE 7 0 Output Slew Rate Enable for Port J Bits Each of these control bits determines if the output slew rate control is enabled for the associated PTJ pin For port J pins that are configured as inputs these bits have no effect 0 Output slew rate control disabled for port J bit n 1 Output slew rate control ...

Page 138: ...Chapter 6 Parallel Input Output Control MC9S08QE128 MCU Series Reference Manual Rev 2 138 Freescale Semiconductor ...

Page 139: ...tures include Up to eight keyboard interrupt pins with individual pin enable bits Each keyboard interrupt pin is programmable as falling edge or rising edge only or both falling edge and low level or both rising edge and high level interrupt sensitivity One software enabled keyboard interrupt Exit from low power modes 7 1 3 Modes of Operation This section defines the KBI operation in wait stop and...

Page 140: ...cription The KBI input pins can be used to detect either falling edges or both falling edge and low level interrupt requests The KBI input pins can also be used to detect either rising edges or both rising edge and high level interrupt requests Table 7 1 KBI1 Pin Mapping Port Pin PTB3 PTB2 PTB1 PTB0 PTA3 PTA2 PTA1 PTA0 KBI1 Pin KBI1P7 KBI1P6 KBI1P5 KBI1P4 KBI1P3 KBI1P2 KBI1P1 KBI1P0 Table 7 2 KBI2...

Page 141: ...t Status and Control Register KBIxSC 7 6 5 4 3 2 1 0 R 0 0 0 0 KBF 0 KBIE KBIMOD W KBACK Reset 0 0 0 0 0 0 0 0 Figure 7 2 KBI Interrupt Status and Control Register KBIxSC Table 7 3 KBIxSC Register Field Descriptions Field Description 3 KBF KBI Interrupt Flag KBF indicates when a KBI interrupt is detected Writes have no effect on KBF 0 No KBI interrupt detected 1 KBI interrupt detected 2 KBACK KBI ...

Page 142: ...t input signal is seen as a logic 1 the deasserted level during one bus cycle and then a logic 0 the asserted level during the next cycle A rising 7 6 5 4 3 2 1 0 R KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 W Reset 0 0 0 0 0 0 0 0 Figure 7 3 KBI Interrupt Pin Select Register KBIxPE Table 7 4 KBIxPE Register Field Descriptions Field Description 7 0 KBIPE 7 0 KBI Interrupt Pin Selects ...

Page 143: ... pin is asserted while attempting to clear by writing a 1 to KBACK 7 4 3 Pull Up Pull Down Resistors The keyboard interrupt pins can be configured to use an internal pull up pull down resistor using the associated I O port pull up enable register If an internal resistor is enabled the KBIxES register is used to select whether the resistor is a pull up KBEDGn 0 or a pull down KBEDGn 1 7 4 4 Keyboar...

Page 144: ...Chapter 7 Keyboard Interrupt S08KBIV2 MC9S08QE128 MCU Series Reference Manual Rev 2 144 Freescale Semiconductor ...

Page 145: ...ment unit for greater than 64 KB 16 bit stack pointer any size stack anywhere in 64 KB CPU address space 16 bit index register H X with powerful indexed addressing modes 8 bit accumulator A Many instructions treat X as a second general purpose 8 bit register Seven addressing modes Inherent Operands in internal registers Relative 8 bit signed offset to branch destination Immediate Operand in next o...

Page 146: ...e 8 bit registers H and X which often work together as a 16 bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address All indexed addressing mode instructions use the full 16 bit value in H X as an index reference pointer however for compatibility with the earlier M68HC05 Family some instructions operate only on the low order 8 bit half X Many instruc...

Page 147: ...y with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low order half of the stack pointer 8 2 4 Program Counter PC The program counter is a 16 bit register that contains the address of the next instruction or operand to be fetched During normal program execution the program counter automatically increments to the next sequential memory location every time a...

Page 148: ...tion of the interrupt service routine is executed Interrupts are not recognized at the instruction boundary after any instruction that clears I CLI or TAP This ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt provided I was set 0 Interrupts enabled 1 Interrupts disabled 2 N Negative Flag The CPU sets the negative flag ...

Page 149: ...dressing mode to specify the source operand and a second addressing mode to specify the destination address Instructions such as BRCLR BRSET CBEQ and DBNZ use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true For BRCLR BRSET CBEQ and DBNZ the addressing mode listed i...

Page 150: ...omplete the instruction 8 3 6 2 Indexed No Offset with Post Increment IX This variation of indexed addressing uses the 16 bit value in the H X index register pair as the address of the operand needed to complete the instruction The index register pair is then incremented H X H X 0x0001 after the operand has been fetched This addressing mode is only used for MOV and CBEQ instructions 8 3 6 3 Indexe...

Page 151: ...on boundary before responding to a reset event For a more detailed discussion about how the MCU recognizes resets and determines the source refer to the Resets Interrupts and System Configuration chapter The reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted At the conclusion of a re...

Page 152: ... power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from wait mode When an interrupt or reset event occurs the CPU clocks will resume and the interrupt or reset event will be processed normally If a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in wait mode CPU clocks will resume and the CPU wi...

Page 153: ...the called subroutine The actual sequence of operations that occur during execution of CALL is 1 CPU calculates the address of the next instruction after the CALL instruction the return address and pushes this 16 bit value onto the stack low byte first 2 CPU reads the old PPAGE value and pushes it onto the stack 3 CPU writes the new instruction supplied page select value to PPAGE This switches the...

Page 154: ...e CALL and RTC instructions behave like JSR and RTS except they have slightly longer execution times Since extra execution cycles are required routinely substituting CALL RTC for JSR RTS is not recommended JSR and RTS can be used to access subroutines that are located outside the program overlay window or on the same memory page However if a subroutine can be called from other pages it must be ter...

Page 155: ... bits X Index register lower order least significant 8 bits PC Program counter PCH Program counter higher order most significant 8 bits PCL Program counter lower order least significant 8 bits SP Stack pointer Memory and addressing M A memory location or absolute data depending on addressing mode M M 0x0001 A 16 bit value in two consecutive memory locations The higher order most significant 8 bits...

Page 156: ...le integer in the range 0 7 opr8i Any label or expression that evaluates to an 8 bit immediate value opr16i Any label or expression that evaluates to a 16 bit immediate value opr8a Any label or expression that evaluates to an 8 bit value The instruction treats this 8 bit value as the low order 8 bits of an address in the direct page of the 64 Kbyte address space 0x00xx opr16a Any label or expressi...

Page 157: ...ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 ADD opr8i ADD opr8a ADD opr16a ADD oprx16 X ADD oprx8 X ADD X ADD oprx16 SP ADD oprx8 SP Add without Carry A A M IMM DIR EXT IX2 IX1 IX SP2 SP1 AB BB CB DB EB FB 9EDB 9EEB ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 AIS opr8i Add Immediate Value Signed to Stack Pointer SP SP M M is sign extended to a 16 bit value IMM A7 ii 2 AIX opr8i Add Immediate Value Sign...

Page 158: ...BIH rel Branch if IRQ Pin High Branch if IRQ pin 1 REL 2F rr 3 BIL rel Branch if IRQ Pin Low Branch if IRQ pin 0 REL 2E rr 3 BIT opr8i BIT opr8a BIT opr16a BIT oprx16 X BIT oprx8 X BIT X BIT oprx16 SP BIT oprx8 SP Bit Test A M CCR Updated but Operands Not Changed 0 IMM DIR EXT IX2 IX1 IX SP2 SP1 A5 B5 C5 D5 E5 F5 9ED5 9EE5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 BLE rel Branch if Less Than o...

Page 159: ...PCL SP SP 0x0001 Push PCH SP SP 0x0001 Push PPAGE SP SP 0x0001 PPAGE page PC Unconditional Address EXT AC pghll 8 CBEQ opr8a rel CBEQA opr8i rel CBEQX opr8i rel CBEQ oprx8 X rel CBEQ X rel CBEQ oprx8 SP rel Compare and Branch if Equal Branch if A M Branch if A M Branch if X M Branch if A M Branch if A M Branch if A M DIR IMM IMM IX1 IX SP1 31 41 51 61 71 9E61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4...

Page 160: ...ects X Not H DIR INH INH IX1 IX SP1 3B 4B 5B 6B 7B 9E6B dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 DEC opr8a DECA DECX DEC oprx8 X DEC X DEC oprx8 SP Decrement M M 0x01 A A 0x01 X X 0x01 M M 0x01 M M 0x01 M M 0x01 DIR INH INH IX1 IX SP1 3A 4A 5A 6A 7A 9E6A dd ff ff 5 1 1 5 4 6 DIV Divide A H A X H Remainder INH 52 6 EOR opr8i EOR opr8a EOR opr16a EOR oprx16 X EOR oprx8 X EOR X EOR oprx16 SP EOR oprx8 ...

Page 161: ...t Right 0 DIR INH INH IX1 IX SP1 34 44 54 64 74 9E64 dd ff ff 5 1 1 5 4 6 MOV opr8a opr8a MOV opr8a X MOV opr8i opr8a MOV X opr8a Move M destination M source H X H X 0x0001 in IX DIR and DIR IX Modes 0 DIR DIR DIR IX IMM DIR IX DIR 4E 5E 6E 7E dd dd dd ii dd dd 5 5 4 5 MUL Unsigned multiply X A X A 0 0 INH 42 5 NEG opr8a NEGA NEGX NEG oprx8 X NEG X NEG oprx8 SP Negate Two s Complement M M 0x00 M A...

Page 162: ...l PCH SP SP 0x0001 Pull PCL INH 81 6 SBC opr8i SBC opr8a SBC opr16a SBC oprx16 X SBC oprx8 X SBC X SBC oprx16 SP SBC oprx8 SP Subtract with Carry A A M C IMM DIR EXT IX2 IX1 IX SP2 SP1 A2 B2 C2 D2 E2 F2 9ED2 9EE2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 SEC Set Carry Bit C 1 1 INH 99 1 SEI Set Interrupt Mask Bit I 1 1 INH 9B 1 STA opr8a STA opr16a STA oprx16 X STA oprx8 X STA X STA oprx16 SP ...

Page 163: ...or to CCR CCR A INH 84 1 TAX Transfer Accumulator to X Index Register Low X A INH 97 1 TPA Transfer CCR to Accumulator A CCR INH 85 1 TST opr8a TSTA TSTX TST oprx8 X TST X TST oprx8 SP Test for Negative or Zero M 0x00 A 0x00 X 0x00 M 0x00 M 0x00 M 0x00 0 DIR INH INH IX1 IX SP1 3D 4D 5D 6D 7D 9E6D dd ff ff 4 1 1 4 3 5 TSX Transfer SP to Index Reg H X SP 0x0001 INH 95 2 TXA Transfer X Index Reg Low ...

Page 164: ...3 DIR 18 5 BSET4 2 DIR 28 3 BHCC 2 REL 38 5 LSL 2 DIR 48 1 LSLA 1 INH 58 1 LSLX 1 INH 68 5 LSL 2 IX1 78 4 LSL 1 IX 88 3 PULX 1 INH 98 1 CLC 1 INH A8 2 EOR 2 IMM B8 3 EOR 2 DIR C8 4 EOR 3 EXT D8 4 EOR 3 IX2 E8 3 EOR 2 IX1 F8 3 EOR 1 IX 09 5 BRCLR4 3 DIR 19 5 BCLR4 2 DIR 29 3 BHCS 2 REL 39 5 ROL 2 DIR 49 1 ROLA 1 INH 59 1 ROLX 1 INH 69 5 ROL 2 IX1 79 4 ROL 1 IX 89 2 PSHX 1 INH 99 1 SEC 1 INH A9 2 AD...

Page 165: ...SP1 9E6A 6 DEC 3 SP1 9EDA 5 ORA 4 SP2 9EEA 4 ORA 3 SP1 9E6B 8 DBNZ 4 SP1 9EDB 5 ADD 4 SP2 9EEB 4 ADD 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 LDHX 2 IX 9EBE 6 LDHX 4 IX2 9ECE 5 LDHX 3 IX1 9EDE 5 LDX 4 SP2 9EEE 4 LDX 3 SP1 9EFE 5 LDHX 3 SP1 9E6F 6 CLR 3 SP1 9EDF 5 STX 4 SP2 9EEF 4 STX 3 SP1 9EFF 5 STHX 3 SP1 INH Inherent REL Relative SP1 Stack Pointer 8 Bit Offset IMM Immediate IX Indexed No ...

Page 166: ...Chapter 8 Central Processor Unit S08CPUV4 MC9S08QE128 MCU Series Reference Manual Rev 2 166 Freescale Semiconductor ...

Page 167: ...mation When using the bandgap reference voltage for input to ACMP1 and or ACMP2 the user must enable the bandgap buffer by setting SPMS BGBE For value of bandgap voltage reference see the data sheet 9 1 2 ACMP TPM Configuration Information The ACMP modules can be configured to connect the output of the analog comparator to a TPM input capture channel 0 by setting the corresponding ACICx bit in SOP...

Page 168: ...VLPV1 9 1 4 Interrupt Vectors ACMP1 and ACMP2 share a single interrupt vector When interrupts are enabled for both ACMPs the ACF bit in ACMP1SC and ACMP2SC must be polled to determine which ACMP caused the interrupt See Section 4 2 Reset and Interrupt Vector Assignments for the ACMP interrupt vector assignment ...

Page 169: ...2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13 PTF4 ADP14 PTF5 ADP15 PTF2 ADP12 PTF1 ADP11 PTF0 ADP10 PORT F PTF6 ADP16 PTF7 ADP17 PTG1 PTG2 ADP18 PTG3 ADP19 PORT G PTG4 ADP20 PTG5 ADP21 PTG0 VSS VDD VSSA VDDA BKP INT INTERFACE SCI2 SERIAL COM...

Page 170: ...re if not required as an interrupt source during wait mode 9 1 6 2 ACMP in Stop Modes The ACMP is disabled in all stop modes regardless of the settings before executing the STOP instruction Therefore the ACMP cannot be used as a wake up source from stop modes During either stop1 or stop2 mode the ACMP module will be fully powered down Upon wake up from stop1 or stop2 mode the ACMP module will be i...

Page 171: ... the ACMPx pin is connected to the comparator non inverting input if ACBGS is a 0 As shown in Figure 9 2 the ACMPxO pin can be enabled to drive an external pin The signal properties of ACMP are shown in Table 9 1 9 3 Register Definition The ACMP includes one register An 8 bit status and control register Table 9 1 Signal Properties Signal Function I O ACMPx Inverting analog input to the ACMP Minus ...

Page 172: ...nput to the non inverting input of the analog comparator 0 External pin ACMPx selected as non inverting input to comparator 1 Internal reference select as non inverting input to comparator 5 ACF Analog Comparator Flag ACF is set when a compare event occurs Compare events are defined by ACMOD ACF is cleared by writing a one to ACF 0 Compare event has not occurred 1 Compare event has occurred 4 ACIE...

Page 173: ...ce voltage or the ACMPx pin as the input to the non inverting input of the analog comparator The comparator output is high when the non inverting input is greater than the inverting input and is low when the non inverting input is less than the inverting input ACMOD is used to select the condition which will cause ACF to be set ACF can be set on a rising edge of the comparator output a falling edg...

Page 174: ...MC9S08QE128 MCU Series Reference Manual Rev 2 174 Freescale Semiconductor Analog Comparator S08ACMPV3 ...

Page 175: ...shows the MC9S08QE128 Series with the ADC module and pins highlighted NOTE Ignore any references to stop1 low power mode in this chapter because the MC9S08QE128 device does not support it 10 1 1 ADC Clock Gating The bus clock to the ADC can be gated on and off using the SCGC1 ADC bit This bit is set after any reset which enables the bus clock to this module To conserve power the ADC bit can be cle...

Page 176: ...I1P4 RxD1 ADP4 PORT B PTB6 SDA1 XTAL PTB7 SCL1 EXTAL PTC3 TPM3CH3 PTC4 TPM3CH4 RSTO PTC5 TPM3CH5 ACMP2O PTC2 TPM3CH2 PTC1 TPM3CH1 PTC0 TPM3CH0 PORT C PTC6 RxD2 ACMP2 PTC7 TxD2 ACMP2 PTD3 KBI2P3 SS2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13 ...

Page 177: ...Series is the ICSERCLK See Chapter 11 Internal Clock Source S08ICSV3 for more information Table 10 1 ADC Channel Assignment ADCH Channel Input Pin Control ADCH Channel Input Pin Control 00000 AD0 PTA0 ADP0 ADPC0 10000 AD16 PTF6 ADP16 N A 00001 AD1 PTA1 ADP1 ADPC1 10001 AD17 PTF7 ADP17 N A 00010 AD2 PTA2 ADP2 ADPC2 10010 AD18 PTG2 ADP18 N A 00011 AD3 PTA3 ADP3 ADPC3 10011 AD19 PTG3 ADP19 N A 00100 ...

Page 178: ...ncludes a temperature sensor whose output is connected to one of the ADC analog channel inputs Equation 10 1 provides an approximate transfer function of the temperature sensor Eqn 10 1 where VTEMP is the voltage of the temperature sensor channel at the ambient temperature VTEMP25 is the voltage of the temperature sensor channel at 25 C m is the hot or cold voltage versus temperature slope in V C ...

Page 179: ...ous conversion automatic return to idle after single conversion Configurable sample time and conversion speed power Conversion complete flag and interrupt Input clock selectable from up to four sources Operation in wait or stop3 modes for lower noise operation Asynchronous clock source for lower noise operation Selectable asynchronous hardware conversion trigger Automatic compare with interrupt fo...

Page 180: ... Function AD27 AD0 Analog Channel inputs VREFH High reference voltage VREFL Low reference voltage VDDAD Analog power supply VSSAD Analog ground AD0 AD27 VREFH VREFL ADVIN ADCH Control Sequencer initialize sample convert transfer abort Clock Divide ADCK 2 Async Clock Gen Bus Clock ALTCLK ADICLK ADIV ADACK ADCO ADLSMP ADLPC MODE complete Data Registers SAR Converter Compare Value Registers Compare V...

Page 181: ...y an external source that is between the minimum VDDAD spec and the VDDAD potential VREFH must never exceed VDDAD 10 2 4 Voltage Reference Low VREFL VREFL is the low reference voltage for the converter In some packages VREFL is connected internally to VSSAD If externally available connect the VREFL pin to the same voltage potential as VSSAD 10 2 5 Analog Channel Inputs ADx The ADC module supports ...

Page 182: ...software triggered operation is selected or one conversion following assertion of ADHWT when hardware triggered operation is selected 1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected 4 0 ADCH Input Channel Select The ADCH bits form a 5 bit...

Page 183: ... 0 0 0 0 0 0 0 Unimplemented or Reserved Table 10 4 ADCSC2 Register Field Descriptions Field Description 7 ADACT Conversion Active ADACT indicates that a conversion is in progress ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted 0 Conversion not in progress 1 Conversion in progress 6 ADTRG Conversion Trigger Select ADTRG is used to select the type o...

Page 184: ...version This register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met In 12 bit and 10 bit mode reading ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read If ADCRL is not read until the after next conversion is completed then the intermediate conversion result...

Page 185: ... 10 3 6 Compare Value Low Register ADCCVL This register holds the lower 8 bits of the 12 bit or 10 bit compare value or all 8 bits of the 8 bit compare value Bits ADCV7 ADCV0 are compared to the lower 8 bits of the result following a conversion in 12 bit 10 bit or 8 bit mode 10 3 7 Configuration Register ADCCFG ADCCFG is used to select the mode of operation clock source clock divide and configure ...

Page 186: ...le clock configurations 4 ADLSMP Long Sample Time Configuration ADLSMP selects between long and short sample time This adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates a...

Page 187: ... 7 ADPC7 ADC Pin Control 7 ADPC7 is used to control the pin associated with channel AD7 0 AD7 pin I O control enabled 1 AD7 pin I O control disabled 6 ADPC6 ADC Pin Control 6 ADPC6 is used to control the pin associated with channel AD6 0 AD6 pin I O control enabled 1 AD6 pin I O control disabled 5 ADPC5 ADC Pin Control 5 ADPC5 is used to control the pin associated with channel AD5 0 AD5 pin I O co...

Page 188: ...d to control the pin associated with channel AD15 0 AD15 pin I O control enabled 1 AD15 pin I O control disabled 6 ADPC14 ADC Pin Control 14 ADPC14 is used to control the pin associated with channel AD14 0 AD14 pin I O control enabled 1 AD14 pin I O control disabled 5 ADPC13 ADC Pin Control 13 ADPC13 is used to control the pin associated with channel AD13 0 AD13 pin I O control enabled 1 AD13 pin ...

Page 189: ...ed to control the pin associated with channel AD23 0 AD23 pin I O control enabled 1 AD23 pin I O control disabled 6 ADPC22 ADC Pin Control 22 ADPC22 is used to control the pin associated with channel AD22 0 AD22 pin I O control enabled 1 AD22 pin I O control disabled 5 ADPC21 ADC Pin Control 21 ADPC21 is used to control the pin associated with channel AD21 0 AD21 pin I O control enabled 1 AD21 pin...

Page 190: ... conjunction with any of the conversion modes and configurations 10 4 1 Clock Select and Divide Control One of four clock sources can be selected as the clock source for the ADC module This clock source is then divided by a configurable value to generate the input clock to the converter ADCK The clock is selected from one of the following sources by means of the ADICLK bits The bus clock which is ...

Page 191: ...n a rising edge occurs the rising edge is ignored In continuous convert configuration only the initial rising edge to launch continuous conversions is observed The hardware trigger function operates in conjunction with any of the conversion modes and configurations 10 4 4 Conversion Control Conversions can be performed in 12 bit mode 10 bit mode or 8 bit mode as determined by the MODE bits Convers...

Page 192: ...ion in progress will be aborted when A write to ADCSC1 occurs the current conversion will be aborted and a new conversion will be initiated if ADCH are not all 1s A write to ADCSC2 ADCCFG ADCCVH or ADCCVL occurs This indicates a mode of operation change has occurred and the current conversion is therefore invalid The MCU is reset The MCU enters stop mode with ADACK not enabled When a conversion is...

Page 193: ...conversion time for a single conversion is NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications Table 10 12 Total Conversion Time vs Control Conditions Conversion Type ADICLK ADLSMP Max Total Conversion Time Single or first continuous 8 bit 0x 10 0 20 ADCK cycles 5 bus clock cycles Single or first continuous 10 bit or 12 bit 0x 10 0 23 ADCK cycles 5 bu...

Page 194: ...MCU Wait Mode Operation The WAIT instruction puts the MCU in a lower power consumption standby mode from which recovery is very fast because the clock sources remain active If a conversion is in progress when the MCU enters wait mode it continues until completion Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger or if continuous conversions are enabled The...

Page 195: ...and continuing ADC conversions 10 4 8 MCU Stop1 and Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters either stop1 or stop2 mode All module registers contain their reset values following exit from stop1 or stop2 Therefore the module must be re enabled and re configured following exit from stop1 or stop2 10 5 Initialization Information This section gives an example w...

Page 196: ...t 4 ADLSMP 1 Configures for long sample time Bit 3 2 MODE 10 Sets mode at 10 bit conversions Bit 1 0 ADICLK 00 Selects bus clock as input clock source ADCSC2 0x00 00000000 Bit 7 ADACT 0 Flag indicates if a conversion is in progress Bit 6 ADTRG 0 Software trigger selected Bit 5 ACFE 0 Compare function disabled Bit 4 ACFGT 0 Not used in this example Bit 3 2 00 Unimplemented or reserved always reads ...

Page 197: ...round supplies VDDAD and VSSAD which are available as separate pins on some devices On other devices VSSAD is shared on the same pin as the MCU digital VSS and on others both VSSAD and VDDAD are shared with the MCU digital supply pins In these cases there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolation ...

Page 198: ... be minimum parasitic only 10 6 1 3 Analog Input Pins The external analog inputs are typically shared with digital I O pins on MCU devices The pin I O control is disabled by setting the appropriate control bit in one of the pin control registers Conversions can be performed on inputs without the associated pin control register bit set It is recommended that the pin control register bit always be s...

Page 199: ...acy of the conversion The ADC accuracy numbers are guaranteed as specified only if the following conditions are met There is a 0 1 μF low ESR capacitor from VREFH to VREFL There is a 0 1 μF low ESR capacitor from VDDAD to VSSAD If inductive isolation is used from the primary supply an additional 1 μF capacitor is placed from VDDAD to VSSAD VSSAD and VREFL if connected is connected to VSS at a quie...

Page 200: ... full code width is present so the quantization error is 1LSB to 0LSB and the code width of each step is 1LSB 10 6 2 5 Linearity Errors The ADC may also exhibit non linearity of several forms Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy These errors are Zero scale error EZS sometimes called offset This error is define...

Page 201: ...versa However even very small amounts of system noise can cause the converter to be indeterminate between two codes for a range of input voltages around the transition voltage This range is normally around 1 2LSB in 8 bit or 10 bit mode or around 2 LSB in 12 bit mode and will increase with noise This error may be reduced by repeatedly sampling the input and averaging the result Additionally the te...

Page 202: ...12 bit Analog to Digital Converter S08ADCV1 MC9S08QE128 MCU Series Reference Manual Rev 2 202 Freescale Semiconductor ...

Page 203: ...e are also signals provided to control a low power oscillator XOSCVLP module to allow the use of an external crystal resonator as the external reference clock Whichever clock source is chosen it is passed through a reduced bus divider BDIV which allows a lower final output clock frequency to be derived 11 1 1 External Oscillator The external oscillator module XOSCVLP provides the external clock op...

Page 204: ...TPM3CH3 PTC4 TPM3CH4 RSTO PTC5 TPM3CH5 ACMP2O PTC2 TPM3CH2 PTC1 TPM3CH1 PTC0 TPM3CH0 PORT C PTC6 RxD2 ACMP2 PTC7 TxD2 ACMP2 PTD3 KBI2P3 SS2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13 PTF4 ADP14 PTF5 ADP15 PTF2 ADP12 PTF1 ADP11 PTF0 ADP10 POR...

Page 205: ...rce for the MCU Whichever clock is selected as the source can be divided down 2 bit select for clock divider is provided Allowable dividers are 1 2 4 8 Control signals for a low power oscillator as the external reference clock are provided HGO RANGE EREFS ERCLKEN EREFSTEN FLL Engaged Internal mode is automatically selected out of reset BDC clock is provided as a constant divide by 2 of the low ran...

Page 206: ...l FEE In FLL engaged external mode the ICS supplies a clock derived from the FLL which is controlled by an external reference clock The BDC clock is supplied from the FLL 11 1 5 3 FLL Bypassed Internal FBI In FLL bypassed internal mode the FLL is enabled and controlled by the internal reference clock but is bypassed The ICS supplies a clock derived from the internal reference clock The BDC clock i...

Page 207: ...L Bypassed External Low Power FBELP In FLL bypassed external low power mode the FLL is disabled and bypassed and the ICS supplies a clock derived from the external reference clock The external reference clock can be an external crystal resonator supplied by an OSC controlled by the ICS or it can be another external clock source The BDC clock is not available 11 1 5 7 Stop STOP In stop mode the FLL...

Page 208: ...al reference clock Resulting frequency must be in the range 31 25 kHz to 39 0625 kHz See Table 11 3 for the divide by factors 2 IREFS Internal Reference Select The IREFS bit selects the reference clock source for the FLL 1 Internal reference clock selected 0 External reference clock selected 1 IRCLKEN Internal Reference Clock Enable The IRCLKEN bit enables the internal reference clock for use as I...

Page 209: ...rols the external oscillator mode of operation 1 Configure external oscillator for high gain operation 0 Configure external oscillator for low power operation 3 LP Low Power Select The LP bit controls whether the FLL is disabled in FLL bypassed modes 1 FLL is disabled in bypass modes unless BDM is active 0 FLL is not disabled in bypass mode 2 EREFS External Reference Select The EREFS bit selects t...

Page 210: ... DRST DRS DCO Range Status The DRST read field indicates the current frequency range for the FLL output DCOOUT See Table 11 7 The DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains Writing the DRS bits to 2 b11 will be ignored and the DRST bits will remain with the current setting DCO Range Select The DRS field selects the fr...

Page 211: ...lization cycles of the external oscillator clock have completed This bit is only cleared when either ERCLKEN or EREFS are cleared 0 FTRIM ICS Fine Trim The FTRIM bit controls the smallest adjustment of the internal reference clock frequency Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible Table 11 7 DCO frequency range1 1 The result...

Page 212: ...OUT clock is derived from the FLL clock which is controlled by the internal reference clock The FLL loop will lock the frequency to the FLL factor times the internal reference frequency The ICSLCLK is available for BDC communications and the internal reference clock is enabled FLL Bypassed Internal Low Power FBILP IREFS 1 CLKS 00 Entered from any state when MCU enters stop FLL Engaged Internal FEI...

Page 213: ...FLL bypassed internal mode the ICSOUT clock is derived from the internal reference clock The FLL clock is controlled by the internal reference clock and the FLL loop will lock the FLL frequency to the FLL factor times the internal reference frequency The ICSLCLK will be available for BDC communications and the internal reference clock is enabled 11 4 1 4 FLL Bypassed Internal Low Power FBILP The F...

Page 214: ... are static except in the following cases ICSIRCLK will be active in stop mode when all the following conditions occur IRCLKEN bit is written to 1 IREFSTEN bit is written to 1 ICSERCLK will be active in stop mode when all the following conditions occur ERCLKEN bit is written to 1EREFSTEN bit is written to 1 11 4 2 Mode Switching The IREF bit can be changed at anytime but the actual switch to the n...

Page 215: ...ock source The ICSIRCLK frequency can be re targeted by trimming the period of the internal reference clock This can be done by writing a new value to the TRIM bits in the ICSTRM register Writing a larger value will slow down the ICSIRCLK frequency and writing a smaller value to the ICSTRM register will speed up the ICSIRCLK frequency The TRIM bits will effect the ICSOUT frequency if the ICS is in...

Page 216: ...he maximum frequency the chip level timing specifications will support see the Device Overview chapter If EREFSTEN is set and the ERCLKEN bit is written to 1 the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop 11 4 8 Fixed Frequency Clock The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock sou...

Page 217: ...in Figure 12 1 NOTE The SDA and SCL should not be driven above VDD These pins are psuedo open drain containing a protection diode to VDD 12 1 1 Module Configuration The IIC1 module pins SDA and SCL can be repositioned under software control using SOPT2 IIC1PS as shown in Table 12 1 This bit selects which general purpose I O ports are associated with IIC1 operation 12 1 2 Interrupt Vectors For MC9S...

Page 218: ...TPM3CH3 PTC4 TPM3CH4 RSTO PTC5 TPM3CH5 ACMP2O PTC2 TPM3CH2 PTC1 TPM3CH1 PTC0 TPM3CH0 PORT C PTC6 RxD2 ACMP2 PTC7 TxD2 ACMP2 PTD3 KBI2P3 SS2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13 PTF4 ADP14 PTF5 ADP15 PTF2 ADP12 PTF1 ADP11 PTF0 ADP10 POR...

Page 219: ...tification interrupt START and STOP signal generation detection Repeated START signal generation Acknowledge bit generation detection Bus busy detection General call recognition 10 bit address extension 12 1 4 Modes of Operation A brief description of the IIC in the various MCU modes is given here Run mode This is the basic mode of operation To conserve power in this mode disable the module Wait m...

Page 220: ...n This section describes each user accessible pin signal 12 2 1 SCL Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system 12 2 2 SDA Serial Data Line The bidirectional SDA is the serial data line of the IIC system INPUT SYNC IN OUT DATA SHIFT REGISTER ADDRESS COMPARE INTERRUPT CLOCK CONTROL START STOP ARBITRATION CONTROL CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG A...

Page 221: ...rs and control bits only by their names A Freescale provided equate or header file is used to translate these names into the appropriate absolute addresses 12 3 1 IIC Address Register IICxA 7 6 5 4 3 2 1 0 R AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 12 3 IIC Address Register IICxA Table 12 2 IICxA Field Descriptions Field Description 7 1 AD 7 1 Slave Ad...

Page 222: ...to determine the IIC baud rate the SDA hold time the SCL Start hold time and the SCL Stop hold time Table 12 4 provides the SCL divider and hold values for corresponding values of the ICR The SCL divider multiplied by multiplier factor mul is used to generate IIC baud rate IIC baud rate bus speed Hz mul SCL divider Eqn 12 1 SDA hold time is the delay from the falling edge of SCL IIC clock to the c...

Page 223: ...2 17 29 384 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38...

Page 224: ...a 1 to a 0 a STOP signal is generated and the mode of operation changes from master to slave 0 Slave mode 1 Master mode 4 TX Transmit Mode Select The TX bit selects the direction of master and slave transfers In master mode this bit should be set according to the type of transfer required Therefore for address cycles this bit will always be high When addressed as a slave this bit should be set by ...

Page 225: ...ess of slave or master mode The BUSY bit is set when a START signal is detected and cleared when a STOP signal is detected 0 Bus is idle 1 Bus is busy 4 ARBL Arbitration Lost This bit is set by hardware when the arbitration procedure is lost The ARBL bit must be cleared by software by writing a 1 to it 0 Standard bus operation 1 Loss of arbitration 2 SRW Slave Read Write When addressed as a slave ...

Page 226: ...ing the IICxD will return the last byte received while the IIC is configured in either master receive or slave receive modes The IICxD does not reflect every byte that is transmitted on the IIC bus nor can software verify that a byte has been written to the IICxD correctly by reading it back In master transmit mode the first byte of data written to IICxD following assertion of MST is used for the ...

Page 227: ... Descriptions Field Description 7 GCAEN General Call Address Enable The GCAEN bit enables or disables general call address 0 General call address is disabled 1 General call address is enabled 6 ADEXT Address Extension The ADEXT bit controls the number of bits used for the slave address 0 7 bit address scheme 1 10 bit address scheme 2 0 AD 10 8 Slave Address The AD 10 8 field contains the upper thr...

Page 228: ...s composed of four parts START signal Slave address transmission Data transfer STOP signal The STOP signal should not be confused with the CPU STOP instruction The IIC bus system communication is described briefly in the following sections and illustrated in Figure 12 9 Figure 12 9 IIC Bus Transmission Signals SCL SDA START SIGNAL ACK BIT 1 2 3 4 5 6 7 8 MSB LSB 1 2 3 4 5 6 7 8 MSB LSB STOP SIGNAL...

Page 229: ...ter and slave at the same time However if arbitration is lost during an address cycle the IIC will revert to slave mode and operate correctly even if it is being addressed by another master 12 4 1 3 Data Transfer Before successful slave addressing is achieved the data transfer can proceed byte by byte in a direction specified by the R W bit sent by the calling master All transfers that come after ...

Page 230: ... shortest one among the masters The relative priority of the contending masters is determined by a data arbitration procedure a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0 The losing masters immediately switch over to slave receive mode and stop driving SDA output In this case the transition from master to slave mode does not generate a STOP conditio...

Page 231: ...ase it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line 12 4 1 9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer After the master has driven SCL low the slave can drive SCL low for the required period and then release it If the slave SCL low period is greater than the master SCL...

Page 232: ...and including acknowledge bit A2 the procedure is the same as that described for a master transmitter addressing a slave receiver After the repeated START condition Sr a matching slave remembers that it was addressed before This slave then checks whether the first seven bits of the first byte of the slave address following Sr are the same as they were after the START condition S and tests whether ...

Page 233: ...he IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine The user can determine the interrupt type by reading the status register 12 6 1 Byte Transfer Interrupt The TCF transfer complete flag bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer 12 6 2 Address Detect Interrupt When the calling address matches the programmed slave ...

Page 234: ...uring an address or data transmit cycle SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle A START cycle is attempted when the bus is busy A repeated START cycle is requested in slave mode A STOP condition is detected when the master did not request it This bit must be cleared by software by writing a 1 to it ...

Page 235: ...les used to achieve the routine shown in Figure 11 3 5 Write IICC1 to enable TX 6 Write IICC1 to enable MST master mode 7 Write IICD with the address of the target slave The LSB of this byte will determine whether the communication is master receive or transmit Module Use The routine shown in Figure 11 3 can handle both master and slave IIC operations For slave operation an incoming IIC message th...

Page 236: ...IICD ACK from Receiver Tx Next Byte Read Data from IICD and Store Switch to Rx Mode Dummy Read from IICD RTI Y N Y Y Y Y Y Y Y Y Y N N N N N N N N N Y TX RX RX TX Write Read N IICIF Address Transfer Data Transfer MST 0 MST 0 See Note 1 NOTES 1 If general call is enabled a check must be done to determine whether the received address was a general call address 0x00 If the received address was a gene...

Page 237: ... to be enabled to trigger the ADC 13 1 2 RTC Clock Sources The RTC module on MC9S08QE128 Series can be clocked from ICSIRCLK OSCOUT or the LPO In this chapter ERCLK is replaced by OSCOUT for this MCU 13 1 3 RTC Modes of Operation All clock sources are available in all modes except stop2 The OSCOUT and LPO can be enabled as the clock source of the RTC in stop2 13 1 3 1 RTC Status after Stop2 Wakeup...

Page 238: ...U Series Reference Manual Rev 2 238 Freescale Semiconductor Chapter 13 Real Time Counter S08RTCV1 13 1 5 Interrupt Vector See Section 4 2 Reset and Interrupt Vector Assignments for the RTC interrupt vector assignment ...

Page 239: ...ADP4 PORT B PTB6 SDA1 XTAL PTB7 SCL1 EXTAL PTC3 TPM3CH3 PTC4 TPM3CH4 RSTO PTC5 TPM3CH5 ACMP2O PTC2 TPM3CH2 PTC1 TPM3CH1 PTC0 TPM3CH0 PORT C PTC6 RxD2 ACMP2 PTC7 TxD2 ACMP2 PTD3 KBI2P3 SS2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13 PTF4 ADP14...

Page 240: ...interrupt is enabled For lowest possible current consumption the RTC should be stopped by software if not needed as an interrupt source during wait mode Stop Modes The RTC continues to run in stop2 or stop3 mode if the RTC is enabled before executing the STOP instruction Therefore the RTC can be used to bring the MCU out of stop modes with no external components if the real time interrupt is enabl...

Page 241: ...summary in the memory section of this data sheet for the absolute address assignments for all RTC registers This section refers to registers and control bits only by their names and relative address offsets Table 13 1 is a summary of RTC registers Table 13 1 RTC Register Summary Name 7 6 5 4 3 2 1 0 RTCSC R RTIF RTCLKS RTIE RTCPS W RTCCNT R RTCCNT W RTCMOD R RTCMOD W CLOCK SOURCE SELECT PRESCALER ...

Page 242: ...ng the clock source clears the prescaler and RTCCNT counters When selecting a clock source ensure that the clock source is properly enabled if applicable to ensure correct operation of the RTC Reset clears RTCLKS to 00 00 Real time clock source is the 1 kHz low power oscillator LPO 01 Real time clock source is the external clock ERCLK 1x Real time clock source is the internal clock IRCLK 4 RTIE Re...

Page 243: ...e current value of the 8 bit counter Writes have no effect to this register Reset writing to RTCMOD or writing different values to RTCLKS and RTCPS clear the count to 0x00 7 6 5 4 3 2 1 0 R RTCMOD W Reset 0 0 0 0 0 0 0 0 Figure 13 5 RTC Modulo Register RTCMOD Table 13 5 RTCMOD Field Descriptions Field Description 7 0 RTCMOD RTC Modulo These eight read write bits contain the modulo value used to re...

Page 244: ...f a different value is written to RTCLKS the prescaler and RTCCNT counters are reset to 0x00 RTCPS and the RTCLKS 0 bit select the desired divide by value If a different value is written to RTCPS the prescaler and RTCCNT counters are reset to 0x00 Table 13 6 shows different prescaler period values Table 13 6 Prescaler Period RTCPS 1 kHz internal clock source prescaler period RTCLKS 00 1 MHz extern...

Page 245: ... Figure 13 6 the selected clock source is the internal clock source The prescaler is set to RTCPS 0010 or divide by 4 The modulo value in the RTCMOD register is set to 0x55 When the counter RTCCNT reaches the modulo value of 0x55 the counter overflows to 0x00 and continues counting The real time interrupt flag RTIF sets when the counter value changes from 0x55 to 0x00 A real time interrupt is gene...

Page 246: ... second from 1 kHz clock source RTCMOD byte 0x00 RTCSC byte 0x1F Function Name RTC_ISR Notes Interrupt service routine for RTC module pragma TRAP_PROC void RTC_ISR void Clear the interrupt flag RTCSC byte RTCSC byte 0x80 RTC interrupts every 1 Second Seconds 60 seconds in a minute if Seconds 59 Minutes Seconds 0 60 minutes in an hour if Minutes 59 Hours Minutes 0 24 hours in a day if Hours 23 Days...

Page 247: ...ock Gating The bus clock to SCI1 and SCI2 can be gated on and off using the SCGC1 SCI1 SCI2 bits respectively These bits are set after any reset which enables the bus clock to these modules To conserve power these bits can be cleared to disable the clock to either of these modules when not in use See Section 5 7 Peripheral Clock Gating for details 14 1 2 Interrupt Vectors Each SCI module contains ...

Page 248: ...BI1P4 RxD1 ADP4 PORT B PTB6 SDA1 XTAL PTB7 SCL1 EXTAL PTC3 TPM3CH3 PTC4 TPM3CH4 RSTO PTC5 TPM3CH5 ACMP2O PTC2 TPM3CH2 PTC1 TPM3CH1 PTC0 TPM3CH0 PORT C PTC6 RxD2 ACMP2 PTC7 TxD2 ACMP2 PTD3 KBI2P3 SS2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13...

Page 249: ...8 ORIE NEIE SCIxD Read Rx data write Tx data R5 T5 R7 T7 R6 T6 Rx Tx pin direction in Local interrupt enables R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 TXINV Tx data path polarity single wire mode Module Initialization Write SCIxBDH SCIxBDL to set baud rate Write SCIxC1 to configure 1 wire 2 wire 9 8 bit data wakeup and parity if used Write SCIxC2 to configure interrupts enable Rx and Tx RWU Enable Rx wakeup ...

Page 250: ...n complete Receive data register full Receive overrun parity error framing error and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and checking Programmable 8 bit or 9 bit character length Receiver wakeup by idle line or address mark Optional 13 bit break character generation 11 bit break character detection Selectable transmitte...

Page 251: ...ock Diagram H 8 7 6 5 4 3 2 1 0 L SCID Tx BUFFER WRITE ONLY INTERNAL BUS STOP 11 BIT TRANSMIT SHIFT REGISTER START SHIFT DIRECTION LSB 1 BAUD RATE CLOCK PARITY GENERATION TRANSMIT CONTROL SHIFT ENABLE PREAMBLE ALL 1s BREAK ALL 0s SCI CONTROLS TxD TxD DIRECTION TO TxD PIN LOGIC LOOP CONTROL TO RECEIVE DATA IN TO TxD PIN Tx INTERRUPT REQUEST LOOPS RSRC TIE TC TDRE M PT PE TCIE TE SBK T8 TXDIR LOAD F...

Page 252: ...D Rx BUFFER READ ONLY INTERNAL BUS STOP 11 BIT RECEIVE SHIFT REGISTER START SHIFT DIRECTION LSB FROM RxD PIN RATE CLOCK Rx INTERRUPT REQUEST DATA RECOVERY DIVIDE 16 BAUD SINGLE WIRE LOOP CONTROL WAKEUP LOGIC ALL 1s MSB FROM TRANSMITTER ERROR INTERRUPT REQUEST PARITY CHECKING BY 16 RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PF LOOPS PEIE PT PE RSRC WAKE ILT RWU M LBKDIF LBKDIE RXEDGIF RXEDGIE ACTIV...

Page 253: ...not change until SCIxBDL is written SCIxBDL is reset to a non zero value so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled RE or TE bits in SCIxC2 are written to 1 7 6 5 4 3 2 1 0 R LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 14 5 SCI Baud Rate Register SCIxBDH Table 14 1 SCI...

Page 254: ...ects between loop back modes and normal 2 pin full duplex modes When LOOPS 1 the transmitter output is internally connected to the receiver input 0 Normal operation RxD and TxD use separate pins 1 Loop mode or single wire mode where transmitter outputs are internally connected to receiver input See RSRC bit RxD pin is not used by SCI 6 SCISWAI SCI Stops in Wait Mode 0 SCI clocks continue to run in...

Page 255: ...ation or checking 1 Parity enabled 0 PT Parity Type Provided parity is enabled PE 1 this bit selects even or odd parity Odd parity means the total number of 1s in the data character including the parity bit is odd Even parity means the total number of 1s in the data character including the parity bit is even 0 Even parity 1 Odd parity 7 6 5 4 3 2 1 0 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 0 0 0...

Page 256: ...g a general purpose I O pin even if RE 1 0 Receiver off 1 Receiver on 1 RWU Receiver Wakeup Control This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition The wakeup condition is either an idle line between messages WAKE 0 idle line wakeup or a logic 1 in the most significant data bit in a character W...

Page 257: ...r is all 1s these bit times and the stop bit time count toward the full character time of logic high 10 or 11 bit times depending on the M control bit needed for the receiver to detect an idle line When ILT 1 the receiver doesn t start counting idle bit times until after the stop bit So the stop bit and any logic high bit times at the end of the previous character do not count toward the full char...

Page 258: ... detect circuitry is enabled and a LIN break character is detected LBKDIF is cleared by writing a 1 to it 0 No LIN break character has been detected 1 LIN break character has been detected 6 RXEDGIF RxD Pin Active Edge Interrupt Flag RXEDGIF is set when an active edge falling if RXINV 0 rising if RXINV 1 on the RxD pin occurs RXEDGIF is cleared by writing a 1 to it 0 No active edge on the receive ...

Page 259: ...waiting for a start bit 1 SCI receiver active RxD input not idle 1 Setting RXINV inverts the RxD input for all cases data bits start and stop bits break and idle 7 6 5 4 3 2 1 0 R R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 14 11 SCI Control Register 3 SCIxC3 Table 14 7 SCIxC3 Field Descriptions Field Description 7 R8 Ninth Data Bit for Receiver W...

Page 260: ... bus rate clock 4 TXINV1 Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable This bit enables the overrun flag OR to generate hardware interrupt requests 0 OR interrupts disabled use polling 1 Hardware interrupt requested when OR 1 2 NEIE Noise Error Interrupt Enable This...

Page 261: ...in Figure 14 3 The transmitter output TxD idle state defaults to logic high TXINV 0 following reset The transmitter output is inverted by setting TXINV 1 The transmitter is enabled by setting the TE bit in SCIxC2 This queues a preamble character that is one full character frame of the idle state The transmitter then remains idle until data is available in the transmit data buffer Programs store da...

Page 262: ...te 0 and then write 1 to the TE bit This action queues an idle character to be sent as soon as the shifter is available As long as the character in the shifter does not finish while TE 0 the SCI transmitter never actually releases control of the TxD pin If there is a possibility of the shifter finishing while TE 0 set the general purpose I O controls so the pin that is shared with TxD is an output...

Page 263: ...n the case of the start bit the bit is assumed to be 0 if at least two of the samples at RT3 RT5 and RT7 are 0 even if one or all of the samples taken at RT8 RT9 and RT10 are 1s If any sample in any bit time including the start and stop bits in a character frame fails to agree with the logic level for that bit the noise flag NF will be set when the received character is transferred to the receive ...

Page 264: ...d automatically when the receiver detects a logic 1 in the most significant bit of a received character eighth bit in M 0 mode and ninth bit in M 1 mode Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames The logic 1 MSB of an address frame clears the RWU bit before the stop bit is received and sets the RDRF flag In this ca...

Page 265: ...was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun OR flag gets set instead the data along with any associated NF FE or PF condition is lost At any time an active edge on the RxD serial data input pin causes the RXEDGIF flag to set The RXEDGIF flag is cleared by writing a 1 to it This function does depend on the receiver ...

Page 266: ...is sometimes used to check software independent of connections in the external system to help isolate system problems In this mode the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI so it reverts to a general purpose port I O pin 14 3 5 4 Single Wire Operation When LOOPS 1 the RSRC bit in the same register chooses between loop mode RSRC 0 or...

Page 267: ...device does not support it 15 1 1 SPI Clock Gating The bus clock to SPI1 and SPI2 can be gated on and off using the SPI1 and SPI2 bits respectively in SCGC2 These bits are set after any reset which enables the bus clock to this module To conserve power these bits can be cleared to disable the clock to either of these modus when not in use See Section 5 7 Peripheral Clock Gating for details 15 1 2 ...

Page 268: ...RxD1 ADP4 PORT B PTB6 SDA1 XTAL PTB7 SCL1 EXTAL PTC3 TPM3CH3 PTC4 TPM3CH4 RSTO PTC5 TPM3CH5 ACMP2O PTC2 TPM3CH2 PTC1 TPM3CH1 PTC0 TPM3CH0 PORT C PTC6 RxD2 ACMP2 PTC7 TxD2 ACMP2 PTD3 KBI2P3 SS2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13 PTF4 ...

Page 269: ...1 SPI System Block Diagram Figure 15 2 shows the SPI modules of two MCUs connected in a master slave arrangement The master device initiates all SPI data transfers During a transfer the master shifts data out on the MOSI pin to the slave while simultaneously shifting data in on the MISO pin from the slave The transfer effectively exchanges the data that was in the SPI shift registers of the two SP...

Page 270: ...s written to the double buffered transmitter write to SPIxD and gets transferred to the SPI shift register at the start of a data transfer After shifting in a byte of data the data is transferred into the double buffered receiver where it can be read read from SPIxD Pin multiplexing logic controls connections between MCU pins and the SPI module When the SPI is configured as a master the clock outp...

Page 271: ...lect bits SPR2 SPR1 SPR0 divide the output of the prescaler stage by 2 4 8 16 32 64 128 or 256 to get the internal SPI master mode bit rate clock SPI SHIFT REGISTER SHIFT CLOCK SHIFT DIRECTION Rx BUFFER FULL Tx BUFFER EMPTY SHIFT OUT SHIFT IN ENABLE SPI SYSTEM CLOCK LOGIC CLOCK GENERATOR BUS RATE CLOCK MASTER SLAVE MODE SELECT MODE FAULT DETECTION MASTER CLOCK SLAVE CLOCK SPI INTERRUPT REQUEST PIN...

Page 272: ... is selected this pin is not used by the SPI and reverts to being a general purpose port I O pin 15 2 3 MISO Master Data In Slave Data Out When the SPI is enabled as a master and SPI pin control zero SPC0 is 0 not bidirectional mode this pin is the serial data input When the SPI is enabled as a slave and SPC0 0 this pin is the serial data output If SPC0 1 to select single wire bidirectional mode a...

Page 273: ...isters and control bits only by their names and a Freescale provided equate or header file is used to translate these names into the appropriate absolute addresses 15 4 1 SPI Control Register 1 SPIxC1 This read write register includes the SPI enable control interrupt enables and configuration options 7 6 5 4 3 2 1 0 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 0 0 0 0 0 1 0 0 Figure 15 5 SPI...

Page 274: ... different kinds of synchronous serial peripheral devices Refer to Section 15 5 1 SPI Clock Formats for more details 0 First edge on SPSCK occurs at the middle of the first cycle of an 8 cycle data transfer 1 First edge on SPSCK occurs at the start of the first cycle of an 8 cycle data transfer 1 SSOE Slave Select Output Enable This bit is used in combination with the mode fault enable MODFEN bit ...

Page 275: ...pin acts as an input 1 SPI I O pin enabled as an output 1 SPISWAI SPI Stop in Wait Mode 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode 0 SPC0 SPI Pin Control 0 The SPC0 bit chooses single wire bidirectional mode If MSTR 0 slave mode the SPI uses the MISO SISO pin for bidirectional SPI data transfers If MSTR 1 master mode the SPI uses the MOSI MOMI pin...

Page 276: ...ad 0 Writes have no meaning or effect Table 15 5 SPI Baud Rate Prescaler Divisor SPPR2 SPPR1 SPPR0 Prescaler Divisor 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 Table 15 6 SPI Baud Rate Divisor SPR2 SPR1 SPR0 Rate Divisor 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 7 6 5 4 3 2 1 0 R SPRF 0 SPTEF MODF 0 0 0 0 W Reset 0 0 1 0 0 0 0 0 Unimplemented or Re...

Page 277: ... writing a data value to the transmit buffer at SPIxD SPIxS must be read with SPTEF 1 before writing data to SPIxD or the SPIxD write will be ignored SPTEF generates an SPTEF CPU interrupt request if the SPTIE bit in the SPIxC1 is also set SPTEF is automatically set when a data byte transfers from the transmit buffer into the transmit shift register For an idle SPI no data in the transmit buffer o...

Page 278: ... details Because the transmitter and receiver are double buffered a second byte in addition to the byte currently being shifted out can be queued into the transmit data buffer and a previously received character can be in the receive data buffer while a new character is being shifted in The SPTEF flag indicates when the transmit buffer has room for a new character The SPRF flag indicates when a re...

Page 279: ... the slave The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs respectively At the third SPSCK edge the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave respectively When CH...

Page 280: ... the transfer The SS IN waveform applies to the slave select input of a slave Figure 15 11 SPI Clock Formats CPHA 0 When CPHA 0 the slave begins to drive its MISO output with the first data bit value MSB or LSB depending on LSBFE when SS goes to active low The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs respectively At the secon...

Page 281: ... mode fault occurs and the mode fault flag MODF becomes set when a master SPI device detects an error on the SS pin provided the SS pin is configured as the mode fault input signal The SS pin is configured to be the mode fault input signal when MSTR 1 mode fault enable is set MODFEN 1 and slave select output enable is clear SSOE 0 The mode fault detection feature can be used in a system where more...

Page 282: ...Serial Peripheral Interface S08SPIV3 MC9S08QE128 MCU Series Reference Manual Rev 2 282 Freescale Semiconductor ...

Page 283: ...PMxCH0 pin is not available externally regardless of the configuration of the TPMx module The ACMP1 output can be connected to TPM1CH0 The ACMP2 output can be connected to TPM2CH0 16 1 2 TPM Clock Gating The bus clock to TPM1 TPM2 and TPM3 can be gated on and off using the SCGC1 TPMx bits These bits are set after any reset which enables the bus clock to this module To conserve power these bits can...

Page 284: ...SDA1 XTAL PTB7 SCL1 EXTAL PTC3 TPM3CH3 PTC4 TPM3CH4 RSTO PTC5 TPM3CH5 ACMP2O PTC2 TPM3CH2 PTC1 TPM3CH1 PTC0 TPM3CH0 PORT C PTC6 RxD2 ACMP2 PTC7 TxD2 ACMP2 PTD3 KBI2P3 SS2 PTD4 KBI2P4 PTD5 KBI2P5 PTD2 KBI2P2 MISO2 PTD1 KBI2P1 MOSI2 PTD0 KBI2P0 SPSCK2 PORT D PTD6 KBI2P6 PTD7 KBI2P7 PTE3 SS1 PTE4 PTE5 PTE2 MISO1 PTE1 MOSI1 TPM2CLK PORT E PTE6 PTE0 TPM2CLK SPSCK1 PTF3 ADP13 PTF4 ADP14 PTF5 ADP15 PTF2 ...

Page 285: ...WM mode is selected input capture output compare and edge aligned PWM functions are not available on any channels of this TPM module When the microcontroller is in active BDM background or BDM foreground mode the TPM temporarily suspends all counting until the microcontroller returns to normal user operating mode During stop mode all system clocks including the main oscillator are stopped therefor...

Page 286: ...his type of PWM signal is called center aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero This type of PWM is required for types of motors used in small appliances This is a high level description only Detailed descriptions of operating modes are in later sections 16 1 6 Block Diagram The TPM uses one input output I O pin per chann...

Page 287: ...UPT LOGIC CPWMS MS0B MS0A COUNTER RESET CLKSB CLKSA 1 2 4 8 16 32 64 BUS CLOCK FIXED SYSTEM CLOCK EXTERNAL CLOCK SYNC 16 BIT COMPARATOR 16 BIT LATCH CHANNEL 1 ELS1B ELS1A CH1IE CH1F INTERNAL BUS PORT LOGIC INTER RUPT LOGIC MS1B MS1A 16 BIT COMPARATOR 16 BIT LATCH CHANNEL 7 ELS7B ELS7A CH7IE CH7F PORT LOGIC INTER RUPT LOGIC MS7B MS7A Up to 8 channels CLOCK SOURCE SELECT OFF BUS FIXED SYSTEM CLOCK E...

Page 288: ...cific chip implementation Refer to documentation for the full chip for details about reset states port connections and whether there is any pullup device on these pins TPM channel pins can be associated with general purpose I O pins and have passive pullup devices which can be enabled with a control bit when the TPM or general purpose I O controls have configured the associated pin as an input Whe...

Page 289: ...I O pin when ELSnB ELSnA 0 0 or when CLKSB CLKSA 0 0 so it normally reverts to general purpose I O control When CPWMS 1 and ELSnB ELSnA not 0 0 all channels within the TPM are configured for center aligned PWM and the TPMxCHn pins are all controlled by the TPM system When CPWMS 0 the MSnB MSnA control bits determine whether the channel is configured for input capture output compare or edge aligned...

Page 290: ...each new period TPMxCNT 0x0000 and the pin is forced low when the channel value register matches the timer counter When ELSnA 1 the TPMxCHn pin is forced low at the start of each new period TPMxCNT 0x0000 and the pin is forced high when the channel value register matches the timer counter Figure 16 3 High True Pulse of an Edge Aligned PWM Figure 16 4 Low True Pulse of an Edge Aligned PWM CHnF BIT ...

Page 291: ...set when the timer counter is counting down and the channel value register matches the timer counter If ELSnA 1 the corresponding TPMxCHn pin is set when the timer counter is counting up and the channel value register matches the timer counter the TPMxCHn pin is cleared when the timer counter is counting down and the channel value register matches the timer counter Figure 16 5 High True Pulse of a...

Page 292: ...lears TOIE 0 TOF interrupts inhibited use for software polling 1 TOF interrupts enabled 5 CPWMS Center aligned PWM select When present this read write bit selects CPWM operating mode By default the TPM operates in up counting mode for input capture output compare and edge aligned PWM functions Setting CPWMS reconfigures the TPM to operate in up down counting mode for CPWM functions Reset clears CP...

Page 293: ...ally restarted by an MCU reset or any write to the timer status control register TPMxSC Reset clears the TPM counter registers Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter TPMxCNTH TPMxCNTL and resets the coherency mechanism regardless of the data involved in the write Table 16 3 TPM Clock Source Selection CLKSB CLKSA TPM Clock Source to Prescaler Input 00 No clock selecte...

Page 294: ...abled Writing to either byte TPMxMODH or TPMxMODL latches the value into a buffer and the registers are updated with the value of their write buffer according to the value of CLKSB CLKSA bits so If CLKSB CLKSA 0 0 then the registers are updated when the second byte is written If CLKSB CLKSA not 0 0 then the registers are updated after both bytes were written and the TPM counter changes from TPMxMO...

Page 295: ...ue registers When channel n is an edge aligned center aligned PWM channel and the duty cycle is set to 0 or 100 CHnF will not be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers A corresponding interrupt is requested when CHnF is set and interrupts are enabled CHnIE 1 Clear CHnF by reading TPMxCnSC while CHnF is set and then writing a logi...

Page 296: ...re event select the level that will be driven in response to an output compare match or select the polarity of the PWM output Setting ELSnB ELSnA to 0 0 configures the related timer pin as a general purpose I O pin not related to any timer functions This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose I O pin when t...

Page 297: ...isters are updated when the second byte is written If CLKSB CLKSA not 0 0 and in output compare mode then the registers are updated after the second byte is written and on the next change of the TPM counter end of the prescaler counting If CLKSB CLKSA not 0 0 and in EPWM or CPWM modes then the registers are updated after the both bytes were written and the TPM counter changes from TPMxMODH TPMxMOD...

Page 298: ...s the way the main counter operates In CPWM mode the counter changes to an up down mode rather than the up counting mode used for general purpose timer functions The following sections describe the main counter and each of the timer operating modes input capture output compare edge aligned PWM and center aligned PWM Because details of pin operation and interrupt activity depend upon the operating ...

Page 299: ...ing used as the timer external clock source It is the user s responsibility to avoid such settings The TPM channel could still be used in output compare mode for software timing functions pin controls set not to affect the TPM channel pin 16 4 1 2 Counter Overflow and Modulo Reset An interrupt flag and enable are associated with the 16 bit main counter The flag TOF is a software accessible indicat...

Page 300: ...rs determine the basic mode of operation for the corresponding channel Choices include input capture output compare and edge aligned PWM 16 4 2 1 Input Capture Mode With the input capture function the TPM can capture the time at which an external event occurs When an active edge occurs on the pin of an input capture channel the TPM latches the contents of the TPM counter into the channel value reg...

Page 301: ...e output compare value in the TPM channel registers determines the pulse width duty cycle of the PWM signal Figure 16 15 The time between the modulus overflow and the output compare is the pulse width If ELSnA 0 the counter overflow forces the PWM signal high and the output compare forces the PWM signal low If ELSnA 1 the counter overflow forces the PWM signal low and the output compare forces the...

Page 302: ...te 100 duty cycle This is not a significant limitation The resulting period would be much longer than required for normal applications TPMxMODH TPMxMODL 0x0000 is a special case that should not be used with center aligned PWM mode When CPWMS 0 this case corresponds to the counter running free from 0x0000 through 0xFFFF but when CPWMS 1 the counter needs a valid match to the modulus register somewh...

Page 303: ...xMODL the TPM can optionally generate a TOF interrupt at the end of this count Writing to TPMxSC cancels any values written to TPMxMODH and or TPMxMODL and resets the coherency mechanism for the modulo registers Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH TPMxCnVL 16 5 Reset Overview 16 5 1 General The TPM is reset w...

Page 304: ...lear the interrupt flag before returning from the interrupt service routine TPM interrupt flags are cleared by a two step process including a read of the flag bit while it is set 1 followed by a write of zero 0 to the bit If a new event is detected between these two steps the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new even...

Page 305: ...ribed in Section 16 6 2 Description of Interrupt Operation 16 6 2 2 2 Output Compare Events When a channel is configured as an output compare channel the interrupt flag is set each time the main timer counter matches the 16 bit value in the channel value register The flag is cleared by the two step sequence described Section 16 6 2 Description of Interrupt Operation 16 6 2 2 3 PWM End of Duty Cycl...

Page 306: ...Timer PWM Module S08TPMV3 MC9S08QE128 MCU Series Reference Manual Rev 2 306 Freescale Semiconductor ...

Page 307: ...ta signals 17 1 1 Forcing Active Background The method for forcing active background mode depends on the specific HCS08 derivative For the MC9S08QE128 Series you can force active background after a power on reset by holding the BKGD pin low as the device exits the reset condition You can also force active background by driving BKGD low immediately after a serial background command that writes a on...

Page 308: ...s allow the CPU registers to be read or written and allow the user to trace one user instruction at a time or GO to the user program from active background mode Non intrusive commands can be executed at any time even while the user s program is running Non intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug contro...

Page 309: ...n speed BKGD is a pseudo open drain pin and there is an on chip pullup so no external pullup resistor is required Unlike typical open drain pins the external RC time constant on this pin which is influenced by external capacitance plays almost no role in signal rise time The custom protocol provides for brief actively driven speedup pulses to force rapid rise times on this pin without risking harm...

Page 310: ... internal BDC clock signal is shown for reference in counting cycles Figure 17 2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU The host is asynchronous to the target so there is a 0 to 1 cycle delay from the host generated falling edge to where the target perceives the beginning of the bit time Ten target BDC clock cycles later the target senses the bit l...

Page 311: ...nough for the target to recognize it at least two target BDC cycles The host must release the low drive before the target MCU drives a brief active high speedup pulse seven cycles after the perceived start of the bit time The host should sample the bit level about 10 cycles after it started the bit time Figure 17 3 BDC Target to Host Serial Bit Timing Logic 1 HOST SAMPLES BKGD PIN 10 CYCLES BDC CL...

Page 312: ...initiates the bit time but the target HCS08 finishes it Because the target wants the host to receive a logic 0 it drives the BKGD pin low for 13 BDC clock cycles then briefly drives it high to speed up the rising edge The host samples the bit level about 10 cycles after starting the bit time Figure 17 4 BDM Target to Host Serial Bit Timing Logic 0 10 CYCLES BDC CLOCK TARGET MCU HOST DRIVE TO BKGD ...

Page 313: ...clature This nomenclature is used in Table 17 1 to describe the coding structure of the BDC commands Commands begin with an 8 bit hexadecimal command code in the host to target direction most significant bit first separates parts of the command d delay 16 target BDC clock cycles AAAA a 16 bit address in the host to target direction RD 8 bits of read data in the target to host direction WD 8 bits o...

Page 314: ... intrusive E2 RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non intrusive C2 WBKP Write BDCBKPT breakpoint register GO Active BDM 08 d Go to execute the user application program starting at the address currently in the PC TRACE1 Active BDM 10 d Trace 1 user instruction at the address in the PC then return to active background mode TAGGO Active BDM 18 d Same as GO but enable external tagging HCS...

Page 315: ...C communications Typically the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent 17 2 4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16 bit match value in the BDCBKPT register This breakpoint...

Page 316: ...s These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU so they do not have addresses and cannot be accessed by user programs Some of the bits in the BDCSCR have write limitations otherwise these registers may be read or written at any time For example the ENBDM control bit may not be written while the MCU is in active background ...

Page 317: ...d mode commands 6 BDMACT Background Mode Active Status This is a read only status bit 0 BDM not active user application program running 1 BDM active and waiting for serial commands 5 BKPTEN BDC Breakpoint Enable If this bit is clear the BDC breakpoint is disabled and the FTS force tag select control bit and BDCBKPT match register are ignored 0 BDC breakpoint disabled 1 BDC breakpoint enabled 4 FTS...

Page 318: ...stop and into active background mode where all BDC commands work Whenever the host forces the target MCU into active background mode the host should issue a READ_STATUS command to check that BDMACT 1 before attempting other BDC commands 0 Target CPU is running user application code or in active background mode was not in wait or stop mode when background became active 1 Target CPU is in wait or st...

Page 319: ... through serial background mode debug commands not from user programs Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 17 3 SBDFR Register Field Description Field Description 0 BDFR Background Debug Force Reset A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset Writing 1 to this bit forces an MCU reset This bit cannot be wri...

Page 320: ...Development Support MC9S08QE128 MCU Series Reference Manual Rev 2 320 Freescale Semiconductor ...

Page 321: ...pace Dual mode Comparators A and B used to compare addresses Full mode Comparator A compares address and Comparator B compares data Can be used as triggers and or breakpoints Comparator C can be used as a normal hardware breakpoint Loop1 capture mode Comparator C is used to track most recent COF event captured into FIFO Tag and Force type breakpoints Nine trigger modes A A Or B A Then B A And B wh...

Page 322: ...nals mmu_ppage_sel1 Comparator A Address Data Control Registers Tag Force Address Bus 16 0 1 match_A control Read Data Bus Read Write store m u x FIFO Data ppage_sel1 MCU in BDM Change of Flow Indicators subtract 2 m u x Read DBGFH Read DBGFL register Instr Lastcycle Bus Clk Comparator B match_B 8 deep FIFO m u x event only Write Data Bus Trigger Break Control Logic c o n t r o FIFO Data DBG Read ...

Page 323: ... Base 0003 Debug Comparator B Low Register DBGCBL Read write Base 0004 Debug Comparator C High Register DBGCCH Read write Base 0005 Debug Comparator C Low Register DBGCCL Read write Base 0006 Debug FIFO High Register DBGFH Read only Base 0007 Debug FIFO Low Register DBGFL Read only Base 0008 Debug Comparator A Extension Register DBGCAX Read write Base 0009 Debug Comparator B Extension Register DBG...

Page 324: ...BGCBL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBGCCH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DBGCCL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBGFH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DBGFL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBGCAX RWAEN RWA PAGSEL 0 0 0 0 bit 16 DBGCBX RWBEN RWB PAGSEL 0 0 0 0 bit 16 DBGCCX RWCEN RWC PAGSEL 0 0 0 0 bit 16...

Page 325: ...BGEN 1 and BEGIN 0 the bits in this register do not change after reset U U U U U U U U Figure 18 2 Debug Comparator A High Register DBGCAH Table 18 3 DBGCAH Field Descriptions Field Description Bits 15 8 Comparator A High Compare Bits The Comparator A High compare bits control whether Comparator A will compare the address bus bits 15 8 to a logic 1 or logic 0 0 Compare corresponding address bit to...

Page 326: ...10 Bit 9 Bit 8 W POR or non end run 0 0 0 0 0 0 0 0 Reset end run1 1 In the case of an end trace to reset where DBGEN 1 and BEGIN 0 the bits in this register do not change after reset U U U U U U U U Figure 18 4 Debug Comparator B High Register DBGCBH Table 18 5 DBGCBH Field Descriptions Field Description Bits 15 8 Comparator B High Compare Bits The Comparator B High compare bits control whether C...

Page 327: ...ares to data if in Full mode 1 Compare corresponding address bit to a logic 1 compares to data if in Full mode Module Base 0x0004 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W POR or non end run 0 0 0 0 0 0 0 0 Reset end run1 1 In the case of an end trace to reset where DBGEN 1 and BEGIN 0 the bits in this register do not change after reset U U U U U U U U Figure 18 6 D...

Page 328: ...rator C Low Register DBGCCL Table 18 8 DBGCCL Field Descriptions Field Description Bits 7 0 Comparator C Low Compare Bits The Comparator C Low compare bits control whether Comparator C will compare the address bus bits 7 0 to a logic 1 or logic 0 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 Module Base 0x0006 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit ...

Page 329: ... non end run 0 0 0 0 0 0 0 0 Reset end run1 1 In the case of an end trace to reset where DBGEN 1 and BEGIN 0 the bits in this register do not change after reset U U U U U U U U Unimplemented or Reserved Figure 18 9 Debug FIFO Low Register DBGFL Table 18 10 DBGFL Field Descriptions Field Description Bits 7 0 FIFO Low Data Bits The FIFO Low data bits contain the least significant byte of data in the...

Page 330: ...0 Write cycle will be matched 1 Read cycle will be matched 5 PAGSEL Comparator A Page Select Bit This PAGSEL bit controls whether Comparator A will be qualified with the internal signal mmu_ppage_sel that indicates an extended access through the PPAGE mechanism When mmu_ppage_sel 1 the 17 bit core address is a paged program access and the 17 bit core address is made up of PPAGE 2 0 addr 13 0 When ...

Page 331: ...0 Write cycle will be matched 1 Read cycle will be matched 5 PAGSEL Comparator B Page Select Bit This PAGSEL bit controls whether Comparator B will be qualified with the internal signal mmu_papge_sel that indicates an extended access through the PPAGE mechanism When mmu_ppage_sel 1 the 17 bit core address is a paged program access and the 17 bit core address is made up of PPAGE 2 0 addr 13 0 When ...

Page 332: ...0 Write cycle will be matched 1 Read cycle will be matched 5 PAGSEL Comparator C Page Select Bit This PAGSEL bit controls whether Comparator C will be qualified with the internal signal mmu_papge_sel that indicates an extended access through the PPAGE mechanism When mmu_ppage_sel 1 the 17 bit core address is a paged program access and the 17 bit core address is made up of PPAGE 2 0 addr 13 0 When ...

Page 333: ...d Descriptions Field Description 7 PPACC PPAGE Access Indicator Bit This bit indicates whether the captured information in the current FIFO word is associated with an extended access through the PPAGE mechanism or not This is indicated by the internal signal mmu_ppage_sel which is 1 when the access is through the PPAGE mechanism 0 The information in the corresponding FIFO word is event only data o...

Page 334: ... 0 Debugger not armed 1 Debugger armed 5 TAG Tag or Force Bit The TAG bit controls whether a debugger or comparator C breakpoint will be requested as a tag or force breakpoint to the CPU The TAG bit is not used if BRKEN 0 0 Force request selected 1 Tag request selected 4 BRKEN Break Enable Bit The BRKEN bit controls whether the debugger will request a breakpoint to the CPU at the end of a trace ru...

Page 335: ...d Description 7 TRGSEL Trigger Selection Bit The TRGSEL bit controls the triggering condition for the comparators See Section 18 4 4 Trigger Break Control TBC for more information 0 Trigger on any compare address access 1 Trigger if opcode at compare address is executed 6 BEGIN Begin End Trigger Bit The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO 0 Trigger at end ...

Page 336: ...eld Description 7 AF Trigger A Match Bit The AF bit indicates if Trigger A match condition was met since arming 0 Comparator A did not match 1 Comparator A match 6 BF Trigger B Match Bit The BF bit indicates if Trigger B match condition was met since arming 0 Comparator B did not match 1 Comparator B match 5 CF Trigger C Match Bit The CF bit indicates if Trigger C match condition was met since arm...

Page 337: ...valid data stored in the FIFO Table 18 20 shows the correlation between the CNT bits and the amount of valid data in FIFO The CNT will stop after a count to eight even if more data is being stored in the FIFO The CNT bits are cleared when the DBG module is armed and the count is incremented each time a new word is captured into the FIFO The host development system is responsible for checking the v...

Page 338: ... not used and will be ignored in Full Modes 18 4 1 2 Comparator C in LOOP1 Capture Mode Normally comparator C is used as a third hardware breakpoint and is not involved in the trigger logic for the on chip ICE system In this mode it compares the core address bus with the address stored in the DBGCCX DBGCCH and DBGCCL registers However in LOOP1 capture mode comparator C is managed by logic in the D...

Page 339: ...s registered into the instruction queue and the CPU will break if when this tag reaches the head of the instruction queue and the tagged instruction is about to be executed 18 4 2 1 Hardware Breakpoints Comparators A B and C can be used as three traditional hardware breakpoints whether the on chip ICE real time capture function is required or not To use any breakpoint or trace run capture function...

Page 340: ... the CPU break occurs at the same place in the application program as the FIFO stopped capturing information If TRGSEL was 0 and TAG was 1 in an end type trace run the FIFO would stop capturing as soon as the comparator address matched but the CPU would continue running until a TAG signal could propagate through the CPUs instruction queue which could take a long time in the case where changes of f...

Page 341: ...ter are set 18 4 4 3 3 A Then B In the A Then B trigger mode the match condition for A must be met before the match condition for B is compared When the match condition for A or B is met the corresponding flag in the DBGS register is set 18 4 4 3 4 Event Only B In the Event Only B trigger mode if the match condition for B is met the BF flag in the DBGS register is set The Event Only B trigger mode...

Page 342: ... Range address A or address B In the Outside Range trigger mode if the match condition for A or B is met the corresponding flag in the DBGS register is set The four control bits BEGIN and TRGSEL in DBGT and BRKEN and TAG in DBGC determine the basic type of debug run as shown in Table 1 21 Some of the 16 possible combinations are not used refer to the notes at the end of the table Table 18 21 Basic...

Page 343: ...l be determined by the change of flow indicators from the core The signal core_cof 1 indicates the current core address is the destination address of an indirect JSR or JMP instruction or a RTS RTC or RTI instruction or interrupt vector and the destination address should be stored The signal core_cof 0 indicates that a conditional branch was taken and that the source address of the conditional bra...

Page 344: ...ending interrupt has higher priority and code execution switches to the interrupt service routine When TRGSEL is clear and the DBG module is armed to trigger on end trigger types the trigger event is detected on a program fetch of the target address even when an interrupt becomes pending on the same cycle In these conditions the pending interrupt has higher priority the exception is processed by t...

Page 345: ...tor A is set to match when the 16 bit CPU address 0xFFFE appears during the reset vector fetch DBGC 0xC0 to enable and arm the DBG module DBGT 0x40 to select a force type trigger a BEGIN trigger and A only trigger mode 18 6 Interrupts The DBG contains no interrupt source 18 7 Electrical Specifications The DBG module contain no electrical specifications ...

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