ROHS MC9S08QE128, Reference Manual

Page: 107 / 345

Chapter 5 Resets, Interrupts, and General System Control
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 107
5.8.10 System Clock Gating Control 1 Register (SCGC1)
This high page register contains control bits to enable or disable the bus clock to the TPMx, ADC, IICx,
and SCIx modules. Gating off the clocks to unused peripherals is used to reduce the MCU’s run and wait
currents. See
Section 5.7, “Peripheral Clock Gating ,” for more information.
NOTE
User software should disable the peripheral before disabling the clocks to
the peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
5
LVDV
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
LVD
).
0 Low trip point selected (V
LVD
= V
LVDL
).
1 High trip point selected (V
LVD
= V
LVDH
).
4
LVWV
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
LVW
).
0 Low trip point selected (V
LVW
= V
LVWL
).
1 High trip point selected (V
LVW
= V
LVWH
).
3
LVWIE
Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF = 1.
Table 5-13. LVD and LVW Trip Point Typical Values
1
1
See the data sheet for minimum and maximum values.
LVDV:LVWV LVW Trip Point LVD Trip Point
0:0 V
LVWL
= 2.15 V V
LVDL
= 1.84 V
0:1 V
LVWH
= 2.48 V
1:0
2
2
This setting is not recommended
V
LVWL
= 2.15 V V
LVDH
= 2.15 V
1:1 V
LVWH
= 2.48 V
7 6 5 4 3 2 1 0
R
TPM3 TPM2 TPM1 ADC IIC2 IIC1 SCI2 SCI1
W
Reset: 1 1 1 1 1 1 1 1
Figure 5-12. System Clock Gating Control 1 Register (SCGC1)
Table 5-12. SPMSC3 Register Field Descriptions (continued)
Field Description