Chapter 4 Memory
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor
71
if PRDIV8 = 0 — f
FCLK
= f
Bus
÷
(DIV + 1)
Eqn. 4-1
if PRDIV8 = 1 — f
FCLK
= f
Bus
÷
(8
×
(DIV + 1))
Eqn. 4-2
shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
4.6.2.2
Flash Options Register (FOPT and NVOPT)
The FOPT register holds all bits associated with the security of the MCU and flash module.
Table 4-11. FCDIV Field Descriptions
Field
Description
7
FDIVLD
Clock Divider Load Control — When writing to the FCDIV register for the first time after a reset, the value of
the FDIVLD bit written controls the future ability to write to the FCDIV register:
0 Writing a 0 to FDIVLD locks the FCDIV register contents; all future writes to FCDIV are ignored.
1 Writing a 1 to FDIVLD keeps the FCDIV register writable; next write to FCDIV is allowed.
When reading the FCDIV register, the value of the FDIVLD bit read indicates the following:
0 FCDIV register has not been written to since the last reset.
1 FCDIV register has been written to since the last reset.
6
PRDIV8
Enable Prescaler by 8
.
0 The bus clock is directly fed into the clock divider
.
1 The bus clock is divided by 8 before feeding into the clock divider.
5:0
FDIV[5:0]
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the bus clock down to a frequency
of 150 kHz–200 kHz. The minimum divide ratio is 2 and the maximum divide ratio is 512. Please refer to
4.6.3.1.1, “Writing the FCDIV Register”
for more information.
Table 4-12. Flash Clock Divider Settings
f
Bus
PRDIV8
(Binary)
DIV
(Decimal)
f
FCLK
Program/Erase Timing Pulse
(5
μ
s Min, 6.7
μ
s Max)
20 MHz
1
12
192.3 kHz
5.2
μ
s
10 MHz
0
49
200 kHz
5
μ
s
8 MHz
0
39
200 kHz
5
μ
s
4 MHz
0
19
200 kHz
5
μ
s
2 MHz
0
9
200 kHz
5
μ
s
1 MHz
0
4
200 kHz
5
μ
s
200 kHz
0
0
200 kHz
5
μ
s
150 kHz
0
0
150 kHz
6.7
μ
s
7
6
5
4
3
2
1
0
R
KEYEN
0
0
0
0
SEC
W
Reset
F
F
0
0
0
0
F
F
= Unimplemented or Reserved
Figure 4-11. Flash Options Register (FOPT)
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