ROHS MC9S08QE128, Reference Manual

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Chapter 18 Debug Module (DBG) (128K)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
336 Freescale Semiconductor
NOTE
The DBG trigger register (DBGT) can not be changed unless ARM=0.
18.3.3.15 Debug Status Register (DBGS)
1001
↓
1111
No Trigger
Module Base + 0x000E
7 6 5 4 3 2 1 0
R AF BF CF 0 0 0 0 ARMF
W
POR
or non-
end-run
0 0 0 0 0 0 0 1
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, ARMF gets cleared by reset but AF, BF, and CF do not
change after reset.
U U U 0 0 0 0 0
= Unimplemented or Reserved
Figure 18-16. Debug Status Register (DBGS)
Table 18-18. DBGS Field Descriptions
Field Description
7
AF
Trigger A Match Bit — The AF bit indicates if Trigger A match condition was met since arming.
0 Comparator A did not match
1 Comparator A match
6
BF
Trigger B Match Bit — The BF bit indicates if Trigger B match condition was met since arming.
0 Comparator B did not match
1 Comparator B match
5
CF
Trigger C Match Bit — The CF bit indicates if Trigger C match condition was met since arming.
0 Comparator C did not match
1 Comparator C match
0
ARMF
Arm Flag Bit — The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill.
While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. See
Section 18.4.4.2, “Arming
the DBG Module” for more information.
0 Debugger not armed
1 Debugger armed
Table 18-17. Trigger Mode Encoding
TRG Value Meaning