ROHS MC9S08QE128, Reference Manual

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Chapter 18 Debug Module (DBG) (128K)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
326 Freescale Semiconductor
18.3.3.3 Debug Comparator B High Register (DBGCBH)
18.3.3.4 Debug Comparator B Low Register (DBGCBL)
Table 18-4. DBGCAL Field Descriptions
Field Description
Bits 7–0 Comparator A Low Compare Bits — The Comparator A Low compare bits control whether Comparator A will
compare the address bus bits [7:0] to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Module Base + 0x0002
7 6 5 4 3 2 1 0
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
POR
or non-
end-run
0 0 0 0 0 0 0 0
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
U U U U U U U U
Figure 18-4. Debug Comparator B High Register (DBGCBH)
Table 18-5. DBGCBH Field Descriptions
Field Description
Bits 15–8 Comparator B High Compare Bits — The Comparator B High compare bits control whether Comparator B will
compare the address bus bits [15:8] to a logic 1 or logic 0. Not used in Full mode.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Module Base + 0x0003
7 6 5 4 3 2 1 0
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
POR
or non-
end-run
0 0 0 0 0 0 0 0
Reset
end-run
1
U U U U U U U U
Figure 18-5. Debug Comparator B Low Register (DBGCBL)