R01UH0823EJ0100 Rev.1.00
Page 93 of 1823
Jul 31, 2019
RX23W Group
2. CPU
?: Conditional operator
Note 1. When the load data is used by the subsequent instruction, the number of cycles described as “latency” is counted as the number
of cycles for the memory load instruction. For the cycles other than the memory load instruction, the number of cycles described
as “throughput” is counted.
Table 2.16
Number of Cycles for Branch Instructions
Instruction
Mnemonic
(indicates the common operation when the size is omitted)
Number of Cycles
Branch instructions
B
Cnd
“pcdsp”
{BRA, BSR} “pcdsp”/“Rs”
{JMP, JSR} “Rs”
Branch taken: 3
Branch not taken: 1
RTE
6
RTFI
3
RTS
5
RTSD “#IMM”
5
RTSD “#IMM, Rd-Rd2”
Throughput: n<5?5:1+n
Latency: n<4?5:2+n
n: Number of registers*
Table 2.17
Number of Cycles for Floating-Point Operation Instructions
Instruction
Mnemonic
(indicates the common operation when the size is omitted)
Number of Cycles
Floating-point operation
instructions
(register-register, immediate-
register)
{FADD, FSUB} “#IMM, Rd”/ “Rs, Rd”/ “Rs, Rs2, Rd”
2
FCMP “#IMM, Rs”/“Rs, Rs2”
1
FDIV “#IMM, Rd”/“Rs, Rd”
16
FMUL “#IMM, Rd”/ “Rs, Rd” / “Rs, Rs2, Rd”
2
FSQRT “Rs, Rd”
16
{FTOI, ROUND, ITOF} “Rs, Rd”
2
{FTOU, UTOF} “Rs, Rd”
2
Floating-point operation
instructions
(memory source operand)
{FADD, FSUB} “[Rs], Rd”/“dsp[Rs], Rd”
4
FCMP “[Rs], Rs2”/“dsp[Rs], Rs2”
3
FDIV “[Rs], Rd”/“dsp[Rs], Rd”
18
FMUL “[Rs], Rd”/“dsp[Rs], Rd”
4
FSQRT “[Rs], Rd”/“dsp[Rs], Rd”
18
{FTOI, ROUND, ITOF} “[Rs], Rd”/“dsp[Rs], Rd”
4
{FTOU, UTOF} “[Rs], Rd”/“dsp[Rs], Rd”
4
Table 2.18
Number of Cycles for DSP Instructions
Instruction
Mnemonic
(indicates the common operation when the size is omitted)
Number of Cycles
DSP instructions
{EMULA, EMACA, EMSBA, MULLH, MULHI, MULLO,
MACLH, MACHI, MACLO, MSBLH, MSBHI, MSBLO}“Rs,
Rs2, Ad”
{MVFACHI, MVFACMI, MVFACLO, MVFACGU} “#IMM, As,
Rd”
{MVTACHI, MVTACLO, MVTACGU} “As, Rd”
{RDACW, RDACL, RACW, RACL} “#IMM, Ad”
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