R01UH0823EJ0100 Rev.1.00
Page 550 of 1823
Jul 31, 2019
RX23W Group
23. Multi-Function Timer Pulse Unit 2 (MTU2a)
Figure 23.37
Block Diagram of MTU3 and MTU4 in Complementary PWM Mode
MTU3.TGRC
TDDR
MTU3.TCNT
MTU3.TGRD
MTU4.TGRD
MTU4.TGRC
TCNTS
MTU4.TCNT
MTU3.TGRA
TCDR
TCBR
Comparator
Comparator
Match
signal
Match
signal
PWM cycle
output
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
POE0#
POE1#
External cutoff
input
External cutoff
interrupt
: Registers that can always be read or written from the CPU
: Registers that can be read or written from the CPU
(but for which access disabling can be set by TRWER)
: Registers that cannot be read or written from the CPU
(except for TCNTS, which can only be read)
Output
p
ro
tectio
n
circuit
O
u
tp
u
t
co
n
tr
o
lle
r
TEMP 1
MT
U
3.
TGR
B
TE
MP
2
TE
MP
3
MT
U
4.
TGR
A
MT
U
4.
TGR
B
M
T
U4.
T
CN
T und
erflow
in
ter
ru
pt
MT
U
3
.T
G
R
A
c
omp
ar
e
-
ma
tc
h in
te
rr
up
t
POE3#