R8C/1A Group, R8C/1B Group
18. Flash Memory
Rev.1.30
Dec 08, 2006
Page 250 of 315
REJ09B0252-0130
18.3.2
ROM Code Protect Function
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the
OFS register in parallel I/O mode. Figure 18.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
Figure 18.4
OFS Register
Option Function Select Register
(1)
Symbol
Address
Before Shipment
OFS
0FFFFh
FFh
(2)
Bit Symbol
Bit Name
Function
RW
Reserved bit
NOTES :
1.
2.
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1
1
—
(b1)
Set to 1.
RW
WDTON
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset.
1 : Watchdog timer is inactive after reset.
RW
ROMCR
ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1enabled
RW
ROMCP1
ROM code protect bit
0 : ROM code protect enabled
1 : ROM code protect disabled
RW
—
(b6-b4)
Reserved bits
Set to 1.
RW
If the block including the OFS register is erased, FFh is set to the OFS register.
The OFS register is on the flash memory. Write to the OFS register w ith a program.
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset.
1 : Count source protect mode disabled after reset.
RW
