Renesas PLSP0020JB-A, User Manual

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R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit
Rev.1.30 Dec 08, 2006 Page 61 of 315
REJ09B0252-0130
Figure 10.3 CM1 Register
System Clock Control Register 1
(1)
Symbol Address After Reset
CM1
0007h 20h
Bit Symbol Bit Name Function RW
NOTES :
1.
2.
3.
4.
5.
6.
7.
8.
When the CM10 bit is set to 1 (stop mode), or the CM05 bit in the CM0 register to 1 (main clock stops) and the CM13
bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin becomes “H”.
When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode.
In count source protect mode (refer to 13.2 Count Source Protect Mode ), the value remains unchanged even if
bits CM10 and CM14 are set.
When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
When the OCD2 bit is set to 0 (main clock selected), the CM14 bit is set to 1 (low -speed
on-chip oscillator stopped). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0
(low -speed on-chip oscillator on). And remains unchanged even if 1 is w ritten to it.
When using the voltage detection interrupt, set the CM14 bit to 0 (low -speed on-chip oscillator on).
CM17 RW
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode System clock division select bits 1
(3)
CM16 RW
CM15
XIN-XOUT drive capacity select bit
(2)
0 : Low
1 : High
RW
CM14
Low -speed on-chip oscillation stop
bit
(5,6,8)
0 : Low -speed on-chip oscillator on
1 : Low -speed on-chip oscillator off
RW
CM13
Port XIN-XOUT sw itch bit
(7)
0 : Input port P4_6, P4_7
1 : XIN-XOUT Pin
RW
—
(b2)
Reserved bit Set to 0.
RW
—
(b1)
Reserved bit Set to 0.
RW
CM10
All clock stop control bit
(4,7,8)
0 : Clock operates.
1 : Stops all clocks (stop mode).
RW
0 0
When entering stop mode from high or medium speed mode, this bit is set to 1 (drive capacity high).
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
b7 b6 b5 b4 b3 b2 b1 b0