R8C/1A Group, R8C/1B Group
10. Clock Generation Circuit
Rev.1.30
Dec 08, 2006
Page 62 of 315
REJ09B0252-0130
Figure 10.4
OCD Register
Oscillation Stop Detection Register
(1)
Symbol
Address
After Reset
OCD
000Ch
04h
Bit Symbol
Bit Name
Function
RW
NOTES :
1.
2.
3.
4.
5.
6.
7.
The OCD3 bit remains 0 (main clock oscillates) if bits OCD1 to OCD0 are set to 00b.
The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
Refer to
Figure 10.8 Sw itching Clock Source from Low -speed On-Chip Oscillator to Main Clock
for the
sw itching procedure w hen the main clock re-oscillates after detecting an oscillation stop.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to this register.
The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a main clock oscillation stop is detected
w hile bits OCD1 to OCD0 are set to 11b (oscillation stop detection function enabled). If the OCD3 bit is set to 1 (main
clock stops), the OCD2 bit remains unchanged even w hen set to 0 (main clock selected).
The OCD3 bit is enabled w hen bits OCD1 to OCD0 are set to 11b (oscillation stop detection function
enabled).
Set bits OCD1 to OCD0 to 00b (oscillation stop detection function disabled) before entering stop or
on-chip oscillator mode (main clock stops).
—
(b7-b4)
Reserved bits
Set to 0.
RW
OCD3
Clock monitor bit
(3,5)
0 : Main clock oscillates.
1 : Main clock stops.
RO
OCD2
System clock select bit
(6)
0 : Selects main clock.
(7)
1 : Selects on-chip oscillator clock.
(2)
RW
OCD1
RW
Oscillation stop detection enable
bits
b1 b0
0 0 : Oscillation stop detection function
disabled
0 1 : Do not set.
1 0 : Do not set.
1 1 : Oscillation stop detection function
enabled
(4,7)
OCD0
RW
0 0 0 0
b3 b2 b1 b0
b7 b6 b5 b4
