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R8C/1A Group, R8C/1B Group

18. Flash Memory

Rev.1.30

Dec 08, 2006

Page 266 of 315

REJ09B0252-0130

18.4.4

Status Register

The status register indicates the operating status of the flash memory and whether an erase or program operation
has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and
FMR07 in the FMR0 register.
Table 18.5 lists the Status Register Bits.
In EW0 mode, the status register can be read in the following cases:

•

When a given address in the user ROM area is read after writing the read status register command

•

When a given address in the user ROM area is read after executing program or block erase command but
before executing the read array command.

18.4.4.1

Sequencer Status (Bits SR7 and FMR00)

The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy) during
auto-programming and auto-erasure, and is set to 1 (ready) at the same time the operation completes.

18.4.4.2

Erase Status (Bits SR5 and FMR07)

Refer to

18.4.5 Full Status Check

.

18.4.4.3

Program Status (Bits SR4 and FMR06)

Refer to

18.4.5 Full Status Check

.

D0 to D7: Indicate the data bus which is read when the read status register command is executed.
Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands cannot
be accepted.

Table 18.5

Status Register Bits

Status

Register

Bit

FMR0

Register

Bit

Status Name

Description

Value

after

Reset

0

1

SR0 (D0)

−

Reserved

−

−

−

SR1 (D1)

−

Reserved

−

−

−

SR2 (D2)

−

Reserved

−

−

−

SR3 (D3)

−

Reserved

−

−

−

SR4 (D4)

FMR06

Program status Completed

normally

Error

0

SR5 (D5)

FMR07

Erase status

Completed
normally

Error

0

SR6 (D6)

−

Reserved

−

−

−

SR7 (D7)

FMR00

Sequencer
status

Busy

Ready

1

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Summary of Contents for PLSP0020JB-A

Page 1: ...ok over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electron...

Page 2: ...t for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas...

Page 3: ...ed in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice...

Page 4: ...such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are co...

Page 5: ...supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is sup...

Page 6: ...tails The following documents apply to the R8C 1A Group R8C 1B Group Make sure to refer to the latest versions of these documents The newest versions of the documents listed may be obtained from the R...

Page 7: ...panied by the word register bit or pin to distinguish the three categories Examples the PM03 bit in the PM0 register P3_5 pin VCC pin 2 Notation of Numbers The indication b is appended to numeric valu...

Page 8: ...ue Operation is not guaranteed when a value is set Function varies according to the operating mode The function of the bit varies with the peripheral function mode Refer to the register diagram for in...

Page 9: ...ontroller GSM Global System for Mobile Communications Hi Z High Impedance IEBus Inter Equipment bus I O Input Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit N...

Page 10: ...Table Register INTB 16 2 5 Program Counter PC 16 2 6 User Stack Pointer USP and Interrupt Stack Pointer ISP 16 2 7 Static Base Register SB 16 2 8 Flag Register FLG 16 2 8 1 Carry Flag C 16 2 8 2 Debug...

Page 11: ...2 6 3 Voltage Monitor 1 Reset 43 6 4 Voltage Monitor 2 Reset 43 6 5 Watchdog Timer Reset 43 6 6 Software Reset 43 7 Voltage Detection Circuit 44 7 1 VCC Input Voltage 50 7 1 1 Monitoring Vdet1 50 7 1...

Page 12: ...es on Clock Generation Circuit 76 10 6 1 Stop Mode 76 10 6 2 Wait Mode 76 10 6 3 Oscillation Stop Detection Function 76 10 6 4 Oscillation Circuit Constants 76 10 6 5 High Speed On Chip Oscillator Clo...

Page 13: ...Timer Mode 112 14 1 2 Pulse Output Mode 113 14 1 3 Event Counter Mode 115 14 1 4 Pulse Width Measurement Mode 116 14 1 5 Pulse Period Measurement Mode 119 14 1 6 Notes on Timer X 122 14 2 Timer Z 123...

Page 14: ...ation Mode 191 16 2 7 SCS Pin Control and Arbitration 197 16 2 8 Notes on Clock Synchronous Serial I O with Chip Select 198 16 3 I2C bus Interface 199 16 3 1 Transfer Clock 209 16 3 2 Interrupt Reques...

Page 15: ...rotect Function 273 18 7 Notes on Flash Memory 274 18 7 1 CPU Rewrite Mode 274 19 Electrical Characteristics 276 20 Usage Notes 296 20 1 Notes on Clock Generation Circuit 296 20 1 1 Stop Mode 296 20 1...

Page 16: ...erter 305 20 7 Notes on Flash Memory 306 20 7 1 CPU Rewrite Mode 306 20 8 Notes on Noise 308 20 8 1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch Up...

Page 17: ...1 VCA1 47 0032h Voltage Detection Register 2 VCA2 47 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register VW1C 48 0037h Voltage Monitor 2 Circuit Control Register VW2C 49 0038h 0039h 00...

Page 18: ...ive Control Register 2 UCON 157 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h SS Control Register H IIC bus Control Register 1 SSCRH ICCR1 172 202 00B9h SS Control Register L IIC bus Control Registe...

Page 19: ...ctions for a high level of instruction efficiency With 1 Mbyte of address space they are capable of executing instructions at high speed Furthermore the R8C 1B Group has on chip data flash ROM 1 KB 2...

Page 20: ...Clock synchronous serial interface 1 channel I2C bus Interface 1 Clock synchronous serial I O with chip select SSU A D converter 10 bit A D converter 1 circuit 4 channels Watchdog timer 15 bits 1 cha...

Page 21: ...ip select SSU A D converter 10 bit A D converter 1 circuit 4 channels Watchdog timer 15 bits 1 channel with prescaler Reset start selectable count source protection mode Interrupts Internal 11 sources...

Page 22: ...ny Series CPU core 8 4 1 3 Timers Timer X 8 bits Timer Z 8 bits Timer C 16 bits System clock generator XIN XOUT High speed on chip oscillator Low speed on chip oscillator Memory Watchdog timer 15 bits...

Page 23: ...8 Kbytes 512 bytes PRDP0020BA A R5F211A3DD 12 Kbytes 768 bytes PRDP0020BA A R5F211A4DD 16 Kbytes 1 Kbyte PRDP0020BA A R5F211A2NP 8 Kbytes 512 bytes PWQN0028KA B R5F211A3NP 12 Kbytes 768 bytes PWQN0028...

Page 24: ...RDP0020BA A NP PWQN0028KA B ROM number Classification D Operating ambient temperature 40 C to 85 C No Symbol Operating ambient temperature 20 C to 85 C Y Operating ambient temperature 20 C to 105 C No...

Page 25: ...s 1 Kbyte 2 1 Kbyte PRDP0020BA A R5F211B2NP 8 Kbytes 1 Kbyte 2 512 bytes PWQN0028KA B R5F211B3NP 12 Kbytes 1 Kbyte 2 768 bytes PWQN0028KA B R5F211B4NP 16 Kbytes 1 Kbyte 2 1 Kbyte PWQN0028KA B R5F211B1...

Page 26: ...RDP0020BA A NP PWQN0028KA B ROM number Classification D Operating ambient temperature 40 C to 85 C No Symbol Operating ambient temperature 20 C to 85 C Y Operating ambient temperature 20 C to 105 C No...

Page 27: ...in Assignments for PLSP0020JB A Package Top View 1 2 3 4 5 6 7 8 9 10 20 P3_4 SCS SDA CMP1_1 19 P3_3 TCIN INT3 SSI00 CMP1_0 18 P1_0 KI0 AN8 CMP0_0 17 P1_1 KI1 AN9 CMP0_1 16 P4_2 VREF 15 P1_2 KI2 AN10...

Page 28: ...SSI00 CMP1_0 18 P1_0 KI0 AN8 CMP0_0 17 P1_1 KI1 AN9 CMP0_1 16 P4_2 VREF 15 P1_2 KI2 AN10 CMP0_2 14 P1_3 KI3 AN11 TZOUT 13 P1_4 TXD0 12 P1_5 RXD0 CNTR01 INT11 11 P1_6 CLK0 SSI01 P3_5 SSCK SCL CMP1_2 P3...

Page 29: ...CC AVCC P1_1 AN9 KI1 CMP0_1 P1_0 AN8 KI0 CMP0_0 PIN Assignment top view Package PWQN0028KA B 28PJW B R8C 1A Group R8C 1B Group 14 13 12 11 10 9 8 22 23 24 25 26 27 28 P3_3 TCIN INT3 SSI00 CMP1_0 P3_4...

Page 30: ...lock Output XOUT O INT Interrupt INT0 INT1 INT3 I INT interrupt input pins Key Input Interrupt KI0 to KI3 I Key input interrupt input pins Timer X CNTR0 I O Timer X I O pin CNTR0 O Timer X output pin...

Page 31: ...Serial Interface Clock Synchronous Serial I O with Chip Select I2C bus Interface A D Converter 1 P3_5 CMP1_2 SSCK SCL 2 P3_7 CNTR0 TXD1 SSO 3 RESET 4 XOUT P4_7 5 VSS AVSS 6 XIN P4_6 7 VCC AVCC 8 MODE...

Page 32: ...nous Serial I O with Chip Select I2C bus Interface A D Converter 1 NC 2 XOUT P4_7 3 VSS AVSS 4 NC 5 NC 6 XIN P4_6 7 NC 8 VCC AVCC 9 MODE 10 P4_5 INT0 RXD1 11 P1_7 INT10 CNTR00 12 P1_6 CLK0 SSI01 13 P1...

Page 33: ...NTBL FB Frame base register 1 The 4 high order bits of INTB are INTBH and the 16 low bits of INTB are INTBL Interrupt table register b19 b0 USP Program counter ISP SB User stack pointer Interrupt stac...

Page 34: ...ndicates the start address of an interrupt vector table 2 5 Program Counter PC PC is 20 bits wide indicates the address of the next instruction to be executed 2 6 User Stack Pointer USP and Interrupt...

Page 35: ...ck Pointer Select Flag U ISP is selected when the U flag is set to 0 USP is selected when the U flag is set to 1 The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT ins...

Page 36: ...ted here All addresses within the SFR which have nothing allocated are reserved for future use and cannot be accessed by users Figure 3 1 Memory Map of R8C 1A Group Undefined instruction Overflow BRK...

Page 37: ...sses within the SFR which have nothing allocated are reserved for future use and cannot be accessed by users Figure 3 2 Memory Map of R8C 1B Group Undefined instruction Overflow BRK instruction Addres...

Page 38: ...nterrupt Enable Register AIER 00h 000Ah Protect Register PRCR 00h 000Bh 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh 000Eh Watchdog Timer Start...

Page 39: ...RT0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Recei...

Page 40: ...Fh FFh 00A0h UART0 Transmit Receive Mode Register U0MR 00h 00A1h UART0 Bit Rate Generator U0BRG XXh 00A2h UART0 Transmit Buffer Register U0TB XXh 00A3h XXh 00A4h UART0 Transmit Receive Control Registe...

Page 41: ...ister 1 ADCON1 00h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h Port P1 Register P1 XXh 00E2h 00E3h Port P1 Direction Register PD1 00h 00E4h 00E5h Port P3 Register P3 XXh 00E6h 00E7h Po...

Page 42: ...6 and PD4_7 5 2 Effect on Peripheral Functions Programmable I O ports function as I O ports for peripheral functions Refer to Table 1 6 Pin Name Information by Pin Number of PLSP0020JB A PRDP0020BA A...

Page 43: ...tion Input to individual peripheral function Drive capacity selection P1_4 1 Port latch Direction register Data bus Pull up selection P1_5 Port latch Direction register Data bus Pull up selection Inpu...

Page 44: ...up selection Digital filter P3_4 P3_5 P3_7 1 Port latch Direction register Data bus Pull up selection 1 Output from individual peripheral function 1 Output from individual peripheral function Output...

Page 45: ...ull up selection Digital filter P4_6 XIN Data bus Clocked inverter 1 P4_7 XOUT Data bus Note 2 Note 3 NOTES 1 When CM05 1 CM10 1 or CM13 0 the clocked inverter is cut off 2 When CM10 1 or CM13 0 the f...

Page 46: ...ts Rev 1 30 Dec 08 2006 Page 28 of 315 REJ09B0252 0130 Figure 5 4 Configuration of I O Pins MODE MODE signal input Note 1 RESET RESET signal input Note 1 NOTE 1 symbolizes a parasitic diode Ensure the...

Page 47: ...mode When read the content is 0 PDi_7 Port Pi7 direction bit RW Bits PD3_0 to PD3_2 and PD3_6 in the PD3 register are unavailable on this MCU If it is necessary to set bits PD3_0 to PD3_2 and PD3_6 s...

Page 48: ...orresponding bit in this register The pin level of any I O port w hich is set to output mode can be controlled by w riting to the corresponding bit in this register 0 L level 1 H level RW Port P4_6 bi...

Page 49: ...defined 0 Not pulled up 1 Pulled up Set to 0 Pull Up Control Register 1 Symbol Address After Reset PUR1 00FDh XXXXXX0Xb Bit Symbol Bit Name Function RW NOTE 1 PU11 P4_5 pull up 1 0 Not pulled up 1 Pul...

Page 50: ...PUR0 DRR KIEN ADCON0 TCOUT P1 Function Bit PD1_1 PU02 DRR1 KI1EN CH2 CH1 CH0 ADGSEL0 TCOUT1 P1_1 Setting Value 0 0 X X XXXXb 0 X Input port not pulled up 0 1 X X XXXXb 0 X Input port pulled up 0 0 X 1...

Page 51: ...rt X X 1 X XXXXb 01b 1 Output port high drive X X X X XXXXb 01b 0 TZOUT output X X X X XXXXb 1Xb X TZOUT output Table 5 8 Port P1_4 TXD0 Register PD1 PUR0 U0MR U0C0 Function Bit PD1_4 PU03 SMD2 SMD1 S...

Page 52: ...XXXXb 1 0 1 SSI01 output Table 5 11 Port P1_7 CNTR00 INT10 Register PD1 PUR0 TXMR UCON Function Bit PD1_7 PU03 TXMOD1 TXMOD0 CNTRSEL Setting Value 0 0 Other than 01b X Input port not pulled up 0 1 Oth...

Page 53: ...0 0 1 0 X 0 SCS input X X 0 0 X X 1 SDA input output 1 X 0 0 0 X 0 Output port X X 0 0 1 0 0 Output port X X 0 0 1 1 0 CMP1_1 output X X 1 0 X X 0 SCS output Table 5 14 Port P3_5 SSCK SCL CMP1_2 Regi...

Page 54: ...000b 0 0 1 XXb CNTR0 output pin X X XXXb 0 1 X XXb SSO input pin X X XXXb 1 0 X XXb SSO output pin Table 5 16 Port XIN P4_6 XOUT P4_7 Register CM1 CM1 CM0 Circuit Specification Function Bit CM13 CM10...

Page 55: ...e program should periodically repeat the setting of the direction registers 2 Connect these unassigned pins to the MCU using the shortest wire length 2 cm or less possible 3 When the power on reset fu...

Page 56: ...t VCC falls monitor voltage Vdet1 Voltage monitor 2 reset VCC falls monitor voltage Vdet2 Watchdog timer reset Underflow of watchdog timer Software reset Write 1 to PM03 bit in PM0 register RESET Powe...

Page 57: ...able register INTB Program counter PC User stack pointer USP Interrupt stack pointer ISP Static base register SB Content of addresses 0FFFEh to 0FFFCh Flag register FLG C IPL D Z S B O I U b15 b0 b15...

Page 58: ...n Registers SFRs for the state of the SFRs after reset The internal RAM is not reset If the RESET pin is pulled L while writing to the internal RAM is in progress the contents of internal RAM will be...

Page 59: ...ardware Reset Circuit Usage Example of External Supply Voltage Detection Circuit and Operation RESET VCC VCC RESET 2 7 V 0V 0 2 VCC or below td P R 500 s or more 0V NOTE 1 Refer to 19 Electrical Chara...

Page 60: ...by 8 is automatically selected as the CPU after reset Refer to 4 Special Function Registers SFRs for the status of the SFR after power on reset The voltage monitor 1 reset is enabled after power on re...

Page 61: ...the program beginning with the address indicated by the reset vector is executed After reset the low speed on chip oscillator clock divided by 8 is automatically selected as the CPU clock The voltage...

Page 62: ...etection 1 Voltage Detection 2 VCC monitor Voltage to monitor Vdet1 Vdet2 Detection target Passing through Vdet1 by rising or falling Passing through Vdet2 by rising or falling Monitor None VCA13 bit...

Page 63: ...oltage detection 2 signal Voltage detection 1 signal Internal reference voltage 1 2 1 2 1 2 Voltage detection 1 circuit VCA26 VCC Internal reference voltage Voltage detection 1 signal is held H when V...

Page 64: ...1b 10b 11b VW2C1 VW2C2 bit is set to 0 not detected by writing 0 by a program When VCA27 bit is set to 0 voltage detection 2 circuit disabled VW2C2 bit is set to 0 VW2C2 VW2C7 VW2C3 Watchdog timer blo...

Page 65: ...er Reset 4 Symbol Address Hardw are reset 00h VCA2 0032h Pow er on reset voltage monitor 1 reset 01000000b Bit Symbol Bit Name Function RW NOTES 1 2 3 4 Set the PRC3 bit in the PRCR register to 1 w ri...

Page 66: ...set to 1 voltage detection 1 circuit enabled Set the VW1C0 bit to 0 disable w hen the VCA26 bit is set to 0 voltage detection 1 circuit disabled VW1C7 Voltage monitor 1 reset generation condition sele...

Page 67: ...ed by 8 VW2F0 RW VW2C6 Voltage monitor 2 circuit mode select bit 5 0 Voltage monitor 2 interrupt mode 1 Voltage monitor 2 reset mode RW VW2C7 Voltage monitor 2 interrupt reset generation condition sel...

Page 68: ...gital Filter A digital filter can be used for monitoring the VCC input voltage When the VW1C1 bit in the VW1C register is set to 0 digital filter enabled for the voltage monitor 1 circuit and the VW2C...

Page 69: ...set to 0 digital filter enabled Vdet1 Voltage monitor 1 reset VCC Sampling timing VW2C2 bit in VW2C register Vdet2 Voltage monitor 2 interrupt Voltage monitor 2 interrupt request 1 Set to 0 by a progr...

Page 70: ...in the VW1C register to 1 digital filter disabled 5 1 Set the VW1C6 bit in the VW1C register to 1 voltage monitor 1 reset mode 6 Set the VW1C2 bit in the VW1C register to 0 7 Set the CM14 bit in the C...

Page 71: ...age Monitor 2 Reset Voltage Monitor 2 Interrupt Voltage Monitor 2 Reset 1 Set the VCA27 bit in the VCA2 register to 1 voltage detection 2 circuit enabled 2 Wait for td E A 3 2 Select the sampling cloc...

Page 72: ...4 cycles VW2C2 bit 0 1 When the VW2C1 bit is set to 0 digital filter enabled VW2C2 bit 0 1 When the VW2C1 bit is set to 1 digital filter disabled and the VW2C7 bit is set to 0 Vdet2 or above VCA13 Bit...

Page 73: ...sible Areas Pins Assignable as I O Port Pins Single chip mode SFR internal RAM internal ROM All pins are I O ports or peripheral function I O pins Processor Mode Register 0 1 Symbol Address After Rese...

Page 74: ...bit in the CSPR register is set to 1 count source protect mode enabled the PM12 bit is automatically set to 1 Reserved bit Set to 0 Nothing is assigned If necessary set to 0 When read the content is u...

Page 75: ...1 Bus Cycles by Access Space of the R8C 1A Group Access Area Bus Cycle SFR 2 cycles of CPU clock ROM RAM 1 cycle of CPU clock Table 9 2 Bus Cycles by Access Space of the R8C 1B Group Access Area Bus...

Page 76: ...ications of Clock Generation Circuit Item Main Clock Oscillation Circuit On Chip Oscillator High Speed On Chip Oscillator Low Speed On Chip Oscillator Applications CPU clock source Peripheral function...

Page 77: ...ock Forcible discharge when OCD0 1 0 Charge discharge circuit Oscillation Stop Detection Interrupt Generation Circuit Detection Watchdog Timer Interrupt OCD2 bit switch signal CM14 bit switch signal O...

Page 78: ...bled 1 Divide by 8 mode RW b7 Reserved bit Set to 0 RW When entering stop mode from high or medium speed mode the CM06 bit is set to 1 divide by 8 mode Set the PRC0 bit in the PRCR register to 1 w rit...

Page 79: ...et to 1 low speed on chip oscillator stopped When the OCD2 bit is set to 1 on chip oscillator clock selected the CM14 bit is set to 0 low speed on chip oscillator on And remains unchanged even if 1 is...

Page 80: ...matically set to 1 on chip oscillator clock selected if a main clock oscillation stop is detected w hile bits OCD1 to OCD0 are set to 11b oscillation stop detection function enabled If the OCD3 bit is...

Page 81: ...gh speed on chip oscillation The CM14 bit in the CM1 register 0 low speed on chip oscillator on When setting the HRA01 bit to 0 low speed on chip oscillator selected do not set the HRA00 bit to 0 high...

Page 82: ...A1 register to a higher value maximum value FFh results in a low er frequency High Speed On Chip Oscillator Control Register 2 1 Symbol Address After Reset HRA2 0022h 00h Bit Symbol Bit Name Function...

Page 83: ...clock source set the OCD2 bit in the OCD register to 0 selects main clock after the main clock is oscillating stably The power consumption can be reduced by setting the CM05 bit in the CM0 register to...

Page 84: ...lying the necessary clock for the MCU The frequency of the low speed on chip oscillator varies depending on the supply voltage and the operating ambient temperature Application products must be design...

Page 85: ...clock fi i 1 2 4 8 and 32 is generated by the system clock divided by i The clock fi is used for timers X Y Z and C the serial interface and the A D converter When the WAIT instruction is executed af...

Page 86: ...hed over the new clock source needs to be oscillating and stable If the new clock source is the main clock allow sufficient wait time in a program until oscillation is stabilized before exiting NOTE 1...

Page 87: ...on fRING S can be used for the watchdog timer and voltage detection circuit 10 4 1 3 High Speed and Low Speed On Chip Oscillator Modes The on chip oscillator clock divided by 1 no division 2 4 8 or 1...

Page 88: ...the peripheral functions using the peripheral function clock stop operating and the peripheral functions operated by external signals can be used to exit wait mode Table 10 3 lists Interrupts to Exit...

Page 89: ...ipheral function interrupt the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply is started The CPU clock when exiting wait mode by a peripheral function i...

Page 90: ...or peripheral function interrupt Figure 10 9 shows the Time from Stop Mode to Interrupt Routine Execution When using a hardware reset to exit stop mode set bits ILVL2 to ILVL0 for the peripheral func...

Page 91: ...nce Oscillation time of CPU clock source used immediately before stop mode Stop mode T3 T4 Internal power stability time T1 T0 150 s max Interrupt request generated 0 flash memory operates 1 flash mem...

Page 92: ...the Procedure for Switching Clock Source from Low Speed On Chip Oscillator to Main Clock To enter wait mode while using the oscillation stop detection function set the CM02 bit to 0 peripheral functio...

Page 93: ...Bit Showing Interrupt Cause Oscillation stop detection a or b a OCD3 bit in OCD register 1 b Bits OCD1 to OCD0 in OCD register 11b and OCD2 bit 1 Watchdog timer VW2C3 bit in VW2C register 1 Voltage m...

Page 94: ...WAIT instruction Program example to execute the WAIT instruction BCLR 1 FMR0 CPU rewrite mode disabled FSET I Enable interrupt WAIT Wait mode NOP NOP NOP NOP 10 6 3 Oscillation Stop Detection Function...

Page 95: ...gisters protected by PRC3 bit Registers VCA2 VW1C and VW2C Figure 11 1 PRCR Register Protect Register Symbol Address After Reset PRCR 000Ah 00h Bit Symbol Bit Name Function RW b7 b6 Reserved bits When...

Page 96: ...interrupt enable flag I flag does not enable or disable interrupts The interrupt priority order cannot be changed based on interrupt priority level Interrupt non maskable interrupt Hardware Software...

Page 97: ...enerated when the BRK instruction is executed 12 1 2 4 INT Instruction Interrupt An INT instruction interrupt is generated when the INT instruction is executed The INT instruction can select software...

Page 98: ...details of the voltage detection circuit refer to 7 Voltage Detection Circuit 12 1 3 4 Single Step Interrupt and Address Break Interrupt Do not use these interrupts They are for use by development to...

Page 99: ...these interrupts They are for use by development support tools only Table 12 1 Fixed Vector Tables Interrupt Source Vector Addresses Address L to H Remarks Reference Undefined instruction 0FFDCh to 0...

Page 100: ...sion 56 to 59 0038h to 003Bh 14 17 A D Converter Clock synchronous serial I O with chip select I2C bus interface 3 60 to 63 003Ch to 003Fh 15 16 2 Clock Synchronous Serial I O with Chip Select SSU 16...

Page 101: ...3 004Fh XXXXX000b CMP1IC 0050h XXXXX000b S0TIC S1TIC 0051h 0053h XXXXX000b S0RIC S1RIC 0052h 0054h XXXXX000b TXIC 0056h XXXXX000b TZIC 0058h XXXXX000b INT1IC 0059h XXXXX000b INT3IC 005Ah XXXXX000b TC...

Page 102: ...rrupt request bit 0 Requests no interrupt 1 Requests interrupt RW 1 ILVL0 RW Interrupt priority level select bits b2 b1 b0 0 0 0 Level 0 interrupt disable 0 0 1 Level 1 0 1 0 Level 2 0 1 1 Level 3 1 0...

Page 103: ...tings of Interrupt Priority Levels and Table 12 4 lists the Interrupt Priority Levels Enabled by IPL The following are conditions under which an interrupt is acknowledged I flag 1 IR bit 1 Interrupt p...

Page 104: ...nterrupt sequence 3 The I D and U flags in the FLG register are set as follows The I flag is set to 0 interrupts disabled The D flag is set to 0 single step interrupt disabled The U flag is set to 0 I...

Page 105: ...interrupt is set in the IPL When a software interrupt or special interrupt request is acknowledged the level listed in Table 12 5 is set in the IPL Table 12 5 lists the IPL Value When a Software or S...

Page 106: ...on Stack SP SP value before interrupt is generated Previous stack contents LSB MSB Address Previous stack contents m 4 m 3 m 2 m 1 m m 1 Stack state before interrupt request is acknowledged SP New SP...

Page 107: ...xecuted the interrupt with the higher priority is acknowledged Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts peripheral functions However if two or more maskable...

Page 108: ...NT3 Timer Z Timer X INT0 Timer C INT1 UART1 receive Compare 1 A D conversion UART1 transmit Key input IPL Priority level of each interrupt Level 0 default value Lowest Highest Priority of peripheral f...

Page 109: ...filter select bits b7 b3 b2 Set to 0 0 RW Reserved bit Nothing is assigned If necessary set to 0 When read the content is 0 b1 b0 0 0 No filter 0 1 Filter w ith f1 sampling 1 0 Filter w ith f8 samplin...

Page 110: ...re 12 13 shows an Operating Example of INT0 Input Filter Figure 12 12 Configuration of INT0 Input Filter Figure 12 13 Operating Example of INT0 Input Filter INT0F0 INT0F1 Bits in INT0F register INT0EN...

Page 111: ...R0 ________ select bit NOTES 1 2 3 R0EDG RW 0 Rising edge 1 Falling edge TXUND RW RW TXMOD2 Operating mode select bit 2 0 Other than pulse period measurement mode 1 Pulse period measurement mode RW TX...

Page 112: ...G128 clock cycle Figure 12 15 shows the TCC0 Register and Figure 12 16 shows the TCC1 Register Figure 12 15 TCC0 Register Timer C Control Register 0 Symbol Address After Reset TCC0 009Ah 00h Bit Symbo...

Page 113: ...three times continuously the input is determined Compare 1 output mode select bits 3 b7 b6 0 0 CMPoutput remains unchanged even w hen compare 1 is matched 0 1 CMPoutput is reversed w hen compare 1 sig...

Page 114: ...0 to K13 is not detected as interrupts Also when H is input to the KIi pin which sets the KIiPL bit to 1 rising edge input to the other pins K10 to K13 is not detected as interrupts Figure 12 17 shows...

Page 115: ...2 RW KI2EN RW KI1PL KI1 input polarity select bit 0 Falling edge 1 Rising edge KI2 input enable bit 0 Disable 1 Enable b7 b6 b5 b4 b1 b0 The IR bit in the KUPIC register may be set to 1 requests inter...

Page 116: ...efore the interrupt request was acknowledged Then use a jump instruction Table 12 6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged Figure 12 19 shows Registers AIER...

Page 117: ...1 Enable RW b2 b1 b0 Address match interrupt 0 enable bit b7 b2 Nothing is assigned If necessary set to 0 When read the content is 0 b7 b6 b5 b4 0 Disable 1 Enable RW b3 Address Match Interrupt Regist...

Page 118: ...ich has the highest priority among the enabled interrupts is set to 0 This may cause the interrupt to be canceled or an unexpected interrupt to be generated 12 5 2 SP Setting Set any value in the SP b...

Page 119: ...t Sources Figure 12 20 Example of Procedure for Changing Interrupt Sources NOTES 1 Execute the above settings individually Do not execute two or more settings at once by one instruction 2 Use the I fl...

Page 120: ...rupt not requested it may not be set to 0 depending on the instruction used Therefore use the MOV instruction to set the IR bit to 0 c When disabling interrupts using the I flag set the I flag as show...

Page 121: ...de Item Count Source Protection Mode Disabled Count Source Protection Mode Enabled Count source CPU clock Low speed on chip oscillator clock Count operation Decrement Reset condition of watchdog timer...

Page 122: ...mbol Bit Name Function RW NOTES 1 2 CSPROINI Count source protection mode after reset select bit 0 Count source protect mode enabled after reset 1 Count source protect mode disabled after reset RW b6...

Page 123: ...nt source protection mode is disabled and 0FFFh w hen count source protection mode is enabled 2 Watchdog Timer Start Register Symbol Address After Reset WDTS 000Eh Undefined RW WO Function The w atchd...

Page 124: ...ue of watchdog timer 32768 1 CPU clock n 16 or 128 selected by WDC7 bit in WDC register Example When the CPU clock frequency is 16 MHz and prescaler divides by 16 the period is approximately 32 8 ms C...

Page 125: ...he OFS register 0FFFFh selects the operation of the watchdog timer after a reset When the WDTON bit is set to 1 watchdog timer is in stop state after reset The watchdog timer and prescaler stop after...

Page 126: ...apture and output compare Count Decrement Decrement Increment Count sources f1 f2 f8 fRING f1 f2 f8 Timer X underflow f1 f8 f32 fRING fast Function Timer mode Provided Provided Not provided Pulse outp...

Page 127: ...t source and outputs pulses which inverts the polarity by underflow of the timer Event counter mode The timer counts external pulses Pulse width measurement mode The timer measures the pulse width of...

Page 128: ...se period measurement mode 1 Pulse period measurement mode TXEDG RW Active edge judgment flag Function varies depending on operating mode b3 b2 Function varies depending on operating mode TXS Timer X...

Page 129: ...ounts internal count source 00h to FFh Event counter mode Counts input pulses from external clock 00h to FFh RW Timer X Register Symbol Address After Reset TX 008Dh FFh Setting Range RW RW 00h to FFh...

Page 130: ...rs TX and PREX are written while the count is stopped values are written to both the reload register and counter When registers TX and PREX are written during the count the value is written to each re...

Page 131: ...he TXMR register Count stop condition 0 count stops is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X underflows timer X interrupt INT10 CNTR00 pin functi...

Page 132: ...Timer X for precautions regarding the TXS bit RW TXUND RW TXEDG The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the R0EDG bit is rew ritten Refer to 12 5 5 Changing Interru...

Page 133: ...rs TX and PREX are written while the count is stopped values are written to both the reload register and counter When registers TX and PREX are written during the count the value is written to each re...

Page 134: ...is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X underflows timer X interrupt Rising or falling of the CNTR0 input end of measurement period INT1 interr...

Page 135: ...upt w hen the R0EDG bit is rew ritten Refer to 12 5 5 Changing Interrupt Sources R0EDG RW TXOCNT RW TXMOD2 Set to 0 in pulse w idth measurement mode TXMOD0 RW Operating mode select bits 0 1 b1 b0 1 1...

Page 136: ...he contents of PREX register Count start Count stop Underflow Count stop Count start Period TXS bit in TXMR register 1 0 Measured pulse CNTR0i pin input 1 0 IR bit in INT1IC register 1 0 IR bit in TXI...

Page 137: ...dition 1 count starts is written to the TXS bit in the TXMR register Count stop condition 0 count stops is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X...

Page 138: ...dge not received 1 Active edge received Timer X underflow flag 0 No underflow 1 Underflow RW The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the R0EDG bit is rew ritten Refe...

Page 139: ...e same time write 1 to the TXUND bit 5 To set to 0 by a program use a MOV instruction to write 0 to the TXUND in the TXMR register At the same time write 1 to the TXEDG bit 6 Bits TXUND and TXEDG are...

Page 140: ...Write 0 to bits TXEDG and TXUND before the count starts The TXEDG bit may be set to 1 by the prescaler X underflow generated after the count starts When using the pulse period measurement mode leave t...

Page 141: ...of a given width successively Programmable one shot generation mode The timer outputs a one shot pulse Programmable wait one shot generation mode The timer outputs a delayed one shot pulse Figure 14...

Page 142: ...mode NOTE 1 Refer to 14 2 5 Notes on Timer Z for precautions regarding the TZS bit TZS RW TZWC Timer Z w rite control bit Timer Z count start flag 1 0 Stops counting 1 Starts counting 0 RW b3 b2 b1 b0...

Page 143: ...w of prescaler Z counts one shot w idth 00h to FFh WO Programmable one shot generation mode Disabled Programmable w aveform generation mode WO 2 Counts underflow of prescaler Z 1 00h to FFh Disabled b...

Page 144: ...en the output of a one shot w aveform is completed If the TZS bit in the TZMR register w as set to 0 count stops to stop the w aveform output during one shot w aveform output set the TZOS bit to 0 Thi...

Page 145: ...tion RW NOTE 1 Reserved bits Set to 0 0 b1 b0 0 0 f1 0 1 f8 1 0 fRING 1 1 f2 TXCK0 0 TXCK1 TZCK0 b2 b1 b0 RW b3 b2 Reserved bits Set to 0 RW b7 b6 b5 b4 0 0 b3 b7 b6 Timer X count source select bits 1...

Page 146: ...1 fi Count source frequency n Value set in PREZ register m value set in TZPR register Count start condition 1 count starts is written to the TZS bit in the TZMR register Count stop condition 0 count...

Page 147: ...ion RW NOTES 1 2 Refer to 14 2 5 Notes on Timer Z for precautions regarding the TZS bit RW TZMOD0 RW b3 b0 Reserved bits Timer Z count start flag 2 0 Stops counting 1 Starts counting 0 RW RW 0 Set to...

Page 148: ...Count operations Decrement When the timer underflows it reloads the contents of the primary reload and secondary reload registers alternately before the count is continued Width and period of output...

Page 149: ...puts H w hen the timer is stopped RW INOSEG RW Set to 0 in programmable w aveform generation mode Set to 0 in programmable w aveform generation mode Timer Z Mode Register Symbol Address After Reset TZ...

Page 150: ...r Z TZOUT pin output IR bit in TZIC register Set to 1 by program Set to 0 by program Set to 0 when interrupt request is acknowledged or set by program Waveform output starts Prescaler Z underflow sign...

Page 151: ...pletes and the TZOS bit is set to 0 one shot stops When the count stops the timer reloads the contents of the reload register before it stops One shot pulse output time n 1 m 1 fi fi Count source freq...

Page 152: ...The INOSEG bit is enabled only w hen the INT0PL bit in the INTEN register is set to 0 one edge INT0F1 bits in the INT0F register Set the INOSTG bit to 0 INT0 _____ pin one shot trigger disabled after...

Page 153: ...OPL bit in PUM register 0 INOSTG bit 1 INT0 one shot trigger enabled INOSEG bit 1 rising edge trigger Prescaler Z underflow signal Count starts Timer Z primary reloads Waveform output ends TZS bit in...

Page 154: ...refer to Table 14 10 Programmable Wait One Shot Generation Mode Specifications When a trigger is generated from that point the timer outputs a pulse only once for a given length of time equal to the...

Page 155: ...t in PREZ register p value set in TZSC register Count start conditions Set the TZOS bit in the TZOC register to 1 one shot starts 1 Input active trigger to the INT0 pin 2 Count stop conditions When re...

Page 156: ...ly w hen the INT0PL bit in the INTEN register is set to 0 one edge RW INOSEG RW RW TZOPL RW 0 Falling edge trigger 1 Rising edge trigger Reserved bits Set to 0 Timer Z output level latch 0 Outputs one...

Page 157: ...ies under the following conditions PREZ 01h TZPR 01h TZSC 02h PUM register TZOPL bit 0 INOSTG bit 1 INT0 one shot trigger enabled INOSEG bit 1 edge trigger at rising edge Prescaler Z underflow signal...

Page 158: ...ion mode read the timer count value before the timer stops The TZS bit in the TZMR register has a function to instruct timer Z to start or stop counting and a function to indicate that the count has s...

Page 159: ...Diagram of Timer C 01b 10b f8 f1 11b f32 TCC11 to TCC10 Digital filter TM0 register Data Bus INT3 interrupt Other than 00b 00b Edge detection TCC07 0 TCC07 1 fRING128 Lower 8 bits Capture and compare...

Page 160: ...1b TCC15 to TCC14 T TCC15 Compare 0 interrupt signal TCC16 TCC17 R Reset Compare 1 interrupt signal Reverse Register TCOUT P1 TCOUT Bit TCOUT0 P1_0 TCOUT6 Setting Value 1 1 0 CMP0_0 waveform output 1...

Page 161: ...RW Store the value compared w ith timer C b0 b7 Mode Output compare mode b8 b0 b15 b7 Capture and Compare 0 Register Symbol Address After Reset TM0 009Dh 009Ch 0000h 2 RW Function Setting Range RW NOT...

Page 162: ...1 0 Both edges 1 1 Do not set RW TCC06 RW TCC04 RW TCC03 Set to 0 b7 b6 b5 b4 0 b3 b2 b1 b0 TCC01 RW Timer C count start bit 0 Stops counting 1 Starts counting Timer C count source select bits 1 b2 b...

Page 163: ...l is matched 1 1 CMPoutput is set to H w hen compare 1 signal is matched When the same value is sampled from the INT3 _____ pin three times continuously the input is determined b3 b2 0 No reload 1 Set...

Page 164: ...1_0 to CMP1_2 1 Inverts CMP output from CMP1_0 to CMP1_2 b3 b2 0 Disables CMP output from CMP0_2 1 Enables CMP output from CMP0_2 b1 b0 TCOUT1 TCOUT0 b7 b6 b5 b4 RW TCOUT2 RW RW CMP output enable bit...

Page 165: ...when the count stops Count start condition The TCC00 bit in the TCC0 register is set to 1 count starts Count stop condition The TCC00 bit in the TCC0 register is set to 0 count stops Interrupt request...

Page 166: ...3 bits 01b capture input polarity is set for falling edge TCC07 0 INT3 TCIN input as capture input trigger Measurement value1 Measurement value 2 Set to 1 by program Transmit measured value 1 The dela...

Page 167: ...pt When a match occurs in compare circuit 1 compare 1 interrupt When time C overflows timer C interrupt INT3 TCIN pin function Programmable I O port or INT3 interrupt input P1_0 to P1_2 pins and P3_3...

Page 168: ...high at compare 0 match occurrence TCC17 to TCC16 bits in TCC1 register 10b CMP output level is set to low at compare 1 match occurrence TCOUT6 bit in TCOUT register 0 not inverted TCOUT7 bit in TCOUT...

Page 169: ...3 3 Notes on Timer C Access registers TC TM0 and TM1 in 16 bit units The TC register can be read in 16 bit units This prevents the timer value from being updated between when the low order bytes and...

Page 170: ...ARTi Figure 15 1 UARTi i 0 or 1 Block Diagram 01b f8 f1 10b CLK1 to CLK0 00b RXD0 f32 1 16 1 16 1 2 1 n0 1 UART reception UART transmission Clock synchronous type when internal clock is selected Clock...

Page 171: ...Data bus low order bits D7 D6 D5 D4 D3 D2 D1 D0 UiTB register D8 TXDi 1SP 2SP SP SP PAR UARTi transmit register 0 i 0 or 1 SP Stop bit PAR Parity bit Note Clock synchronous type is implemented in UART...

Page 172: ...eceive disabled The SUM bit is set to 0 no error w hen bits PER FER and OER are set to 0 no error Bits PER and FER are set to 0 even w hen the higher byte of the UiRB register is read out Also bits PE...

Page 173: ...5 b4 RW Serial interface mode select bits 2 b2 b1 b0 0 0 0 Serial interface disabled 0 0 1 Clock synchronous serial I O mode 1 0 0 UART mode transfer data 7 bits long 1 0 1 UART mode transfer data 8 b...

Page 174: ...arity select bit 0 Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 Transmit data is output at rising edge of transfer clock and receive data is inp...

Page 175: ...gister UART Transmit Receive Control Register 2 Symbol Address After Reset UCON 00B0h 00h Bit Symbol Bit Name Function RW 0 P1_5 RXD0 P1_7 CNTR00 INT10 ______ 1 P1_5 RXD0 CNTR01 INT11 ______ P1_7 NOTE...

Page 176: ...lowing requirements must be met 1 The TE bit in the U0C1 register is set to 1 transmission enabled The TI bit in the U0C1 register is set to 0 data in the U0TB register Receive start conditions Before...

Page 177: ...ck U0C0 CLK1 to CLK0 Select the count source in the U0BRG register TXEPT Transmit register empty flag NCH Select TXD0 pin output mode CKPOL Select the transfer clock polarity UFORM Select the LSB firs...

Page 178: ...terrupt request is acknowledged or set by a program Write dummy data to U0TB register 1 fEXT D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Receive data is taken in Read out from U0RB register Transfer from U...

Page 179: ...rising edge of the transfer clock D1 D2 NOTES 1 When not transferring the CLK0 pin level is H 2 When not transferring the CLK0 pin level is L D3 D4 D5 D6 D7 D0 RXD0 D1 D2 D3 D4 D5 D6 D7 CLK0 2 D0 TXD...

Page 180: ...ve Mode Continuous receive mode is selected by setting the U0RRM bit in the UCON register to 1 enables continuous receive mode In this mode reading the U0RB register sets the TI bit in the U0C1 regist...

Page 181: ...ng are required TE bit in UiC1 register is set to 1 transmission enabled TI bit in UiC1 register is set to 0 data in UiTB register Receive start conditions Before reception starts the following are re...

Page 182: ...er odd or even UiC0 CLK0 CLK1 Select the count source for the UiBRG register TXEPT Transmit register empty flag NCH Select TXDi pin output mode CKPOL Set to 0 UFORM LSB first or MSB first can be selec...

Page 183: ...upt request is generated when transmit completes Start bit Parity bit Stop pulsing because the TE bit is set to 0 TXDi Write data to UiTB register Transfer from UiTB register to UARTi transmit registe...

Page 184: ...INT11 pin UiBRG output Set to 0 when interrupt request is accepted or set by a program Example of receive timing when transfer data is 8 bits long parity disabled one stop bit The above timing diagra...

Page 185: ...92 0 16 2400 f8 64 40h 2403 85 0 16 25 19h 2403 85 0 16 4800 f8 32 20h 4734 85 1 36 12 0Ch 4807 69 0 16 9600 f1 129 81h 9615 38 0 16 51 33h 9615 38 0 16 14400 f1 86 56h 14367 82 0 22 34 22h 14285 71...

Page 186: ...the UiRB register and the RI bit in the UiC1 register are set to 0 To check receive errors read the UiRB register and then use the read data Example when reading receive buffer register MOV W 00A6H R0...

Page 187: ...output format and data output format 16 1 Mode Selection The clock synchronous serial interface has four modes Table 16 1lists the Mode Selections Refer to 16 2 Clock Synchronous Serial I O with Chip...

Page 188: ...ce external clock is selected input from SSCK pin When the MSS bit in the SSCRH register is set to 1 operates as master device internal clock selectable among f1 256 f1 128 f1 64 f1 32 f1 16 f1 8 and...

Page 189: ...erial I O with Chip Select SSMR register Data bus Transmit receive control circuit SSCRL register SSCRH register SSER register SSSR register SSMR2 register SSTDR register SSTRSR register SSRDR registe...

Page 190: ...CKS2 Transfer clock rate select bits 1 b2 b1 b0 0 0 0 f1 256 0 0 1 f1 128 0 1 0 f1 64 0 1 1 f1 32 1 0 0 f1 16 1 0 1 f1 8 1 1 0 f1 4 1 1 1 Do not set CKS0 Master slave device select bit 2 0 Operates a...

Page 191: ...serial data output is set to L 1 The serial data output is set to H When w ritten 2 3 0 The data output is L after the serial data output 1 The data output is H after the serial data output RW b6 Noth...

Page 192: ...0 Transfers data MSB first 1 Transfers data LSB first Refer to 16 2 1 1 Association between Transfer Clock Polarity Phase and Data for the settings of bits CPHS and CPOS R BC1 BC2 Bit counter 2 to 0...

Page 193: ...l and overrun error interrupt request 1 Enables receive data full and overrun error interrupt request Receive interrupt enable bit RW RE TE TEIE Transmit end interrupt enable bit RW RIE TIE Transmit i...

Page 194: ...MSS bit in the SSCRH register is set to 0 operates as slave device and the SCS pin input changes the level from L to H during transfer the CEbit is set to 1 The TDREbit is set to 1 w hen the TEbit in...

Page 195: ...KS SSCK pin select bit 0 Functions as port 1 Functions as serial clock pin RW b3 b2 b1 b7 b6 b5 b4 SOOS SCKOS SSUMS CSOS 0 Clock synchronous communication mode 1 Four w ire bus communication mode SSCK...

Page 196: ...Register 2 Symbol Address After Reset SSRDR 00BFh FFh RW NOTES 1 2 The SSRDR register retains the data received before an overrun error occurs ORER bit in the SSSR register set to 1 overrun error When...

Page 197: ...er rate selected by bits CKS0 to CKS2 in the SSCRH register When the MSS bit in the SSCRH register is set to 0 operates as slave device an external clock can be selected and the SSCK pin functions as...

Page 198: ...ge at odd edge and CPOS bit 0 H when clock stops b1 b2 b3 b4 b5 b6 b7 SSCK CPOS 0 H when clock stops b0 SSO SSI SSUMS 1 4 wire bus communication mode and CPHS 0 data change at odd edge b1 b2 b3 b4 b5...

Page 199: ...gister The connection between the data I O pins and SSTRSR register SS shift register changes according to a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register Th...

Page 200: ...us serial I O with chip select interrupt request is generated Set each interrupt source to 0 by a clock synchronous serial I O with chip select interrupt routine However the TDRE and TEND bits are aut...

Page 201: ...1 in 4 wire bus bidirectional communication mode SSUMS and BIDE Bits in SSMR2 register MSS Bit in SSCRH register TE and RE Bits in SSER register Table 16 4 Association between Communication Modes and...

Page 202: ...TE bit to 0 and the RE bit to 0 before changing the communication mode or format Setting the RE bit to 0 does not change the contents of flags RDRF and ORER and the contents of the SSRDR register Figu...

Page 203: ...en one frame of data is transferred while the TDRE bit is set to 0 data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started If the 8th bit is transmitted while...

Page 204: ...ontinues Read TEND bit in SSSR register TEND 1 No Yes Yes No No Yes SSER register TE bit 0 1 2 3 1 After reading the SSSR register and confirming that the TDRE bit is set to 1 write the transmit data...

Page 205: ...in the SSCRH register to 1 after receiving 1 byte of data the receive operation is completed Clock synchronous serial I O with chip select outputs a clock for receiving 8 bits of data and stops After...

Page 206: ...r 6 Processing after reading the ORER bit Then set the ORER bit to 0 Transmission reception cannot be restarted while the ORER bit is set to 1 4 Confirm that the RDRF bit is set to 1 If the RDRF bit i...

Page 207: ...TDRE bit is set to 1 data is transferred from registers SSTDR to SSTRSR the transmit receive operation is stopped When switching from transmit mode TE 1 or receive mode RE 1 to transmit receive mode...

Page 208: ...the SSTDR register When the transmit data is written to the SSTDR register the TDRE bit is automatically set to 0 5 Set the TEND bit to 0 6 and bits RE and TE in the SSER register to 0 before ending...

Page 209: ...utput When clock synchronous serial I O with chip select is set as a slave device the chip select line controls input When it is set as the master device the chip select line controls output of the SC...

Page 210: ...bit 1 transmit Set bits RIE TEIE and TIE End SSER register RE bit 0 TE bit 0 SSCRH register Set RSSTP bit 2 Set the BIDE bit to 1 in bidirectional mode and set the I O of the SCS pin by bits CSS0 to C...

Page 211: ...is set to 0 the data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started If the 8th bit is transmitted while TDRE is set to 1 TEND in the SSSR register is set...

Page 212: ...at odd edges and CPOS bit 0 H when clock stops b7 SCS output SSCK CPHS bit 1 data change at even edges and CPOS bit 0 H when clock stops CPHS CPOS Bits in SSMR register 1 frame TDRE bit in SSSR regis...

Page 213: ...register Read the receive data after setting the RSSTP bit in the SSCRH register to 1 after receiving 1 byte data the receive operation is completed Clock synchronous serial I O with chip select outp...

Page 214: ...in SSSR register 0 1 RSSTP bit in SSCRH register 0 1 Dummy read in SSRDR register Processing by program 1 frame High impedance b0 b7 High impedance SCS output b7 b0 Data read in SSRDR register RXI in...

Page 215: ...us serial I O with chip select detects that the synchronized internal SCS signal is held L in this period the CE bit in the SSSR register is set to 1 conflict error and the MSS bit is automatically se...

Page 216: ...p select 00B8h to 00BFh or four cycles or more after writing to them read the registers An example of waiting three instructions or more Program example MOV B 00h 00BBh Set the SSER register to 00h NO...

Page 217: ...ssible yet the SCL signal goes L and the interface stands by Support for direct drive of pins SCL and SDA NMOS open drain output Clock synchronous serial format Continuous transmit receive operation B...

Page 218: ...ister ICMR register ICDRT register SAR register ICSR register Address comparison circuit Output control SCL Interrupt request TXI TEI RXI STPI NAKI Transfer clock generation circuit ICDRS register ICD...

Page 219: ...age 201 of 315 REJ09B0252 0130 Figure 16 23 External Circuit Connection Example of Pins SCL and SDA SCL SDA SCL input SCL output SDA input SDA output Master VCC VCC SCL SDA SCL input SCL output SDA in...

Page 220: ...0 0 0 1 0 f1 48 0 0 1 1 f1 64 0 1 0 0 f1 80 0 1 0 1 f1 100 0 1 1 0 f1 112 0 1 1 1 f1 128 1 0 0 0 f1 56 1 0 0 1 f1 80 1 0 1 0 f1 96 1 0 1 1 f1 128 1 1 0 0 f1 160 1 1 0 1 f1 200 1 1 1 0 f1 224 1 1 1 1 f...

Page 221: ...BBSY bit w rite 0 to the SCP bit using the MOV instruction simultaneously Execute the same w ay w hen the start condition is regenerating When w riting to the SDAO bit w rite 0 to the SDAOPbit using t...

Page 222: ...bit b7 b6 b5 b4 b3 b2 b1 b0 When rew riting bits BC0 to BC2 w rite 0 simultaneously 2 4 When read the content is 1 RW The setting value is enabled in master mode of the I2 C bus format It is disabled...

Page 223: ...ect bit 0 Value of receive acknow ledge bit is ignored and continuous transfer is performed 1 When receive acknow ledge bit is set to 1 continuous transfer is halted RW Stop condition detection interr...

Page 224: ...s flag is set to 1 TEND Transmit end 1 6 RW RW General call address recognition flag 1 2 When the general call address is detected this flag is set to 1 Arbitration lost flag overrun error flag 1 When...

Page 225: ...g condition match bits SVA0 to SVA6 in slave mode of the I2 C bus format the MCU operates as a slave device RW RW RW RW SVA2 SVA0 RW SVA3 SVA6 SVA5 SVA4 RW IIC bus Transmit Data Register 1 Symbol Addr...

Page 226: ...nabled RO Function IIC bus Shift Register Symbol ICDRS RW b7 b6 b5 b4 b3 b2 b1 b0 This register is used to transmit and receive data The transmit data is transferred from registers ICRDT to ICDRS and...

Page 227: ...0 0 0 0 f1 28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 f1 40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 1 0 f1 48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 f1 64 78 1 kHz 125 kHz 156 kHz 250 kHz 313 kHz...

Page 228: ...ver bits TDRE and TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is automatically set to 0 by reading the ICDRR register When writing transmit data to...

Page 229: ...ondition is retransmitted FS 0 Upper Transfer bit count n1 n2 1 to 8 Lower Transfer frame count m1 m2 1 or more SLA SLA A A 1 S 1 R W A DATA 7 1 1 n2 SLA 1 m2 SDA SCL S SLA R W A DATA A DATA A P 1 to...

Page 230: ...d in the 1st byte At this time the TDRE bit is automatically set to 0 data is transferred from registers ICDRT to ICDRS and the TDRE bit is set to 1 again 4 When transmission of 1 byte of data is comp...

Page 231: ...egister 1 0 ICDRT register ICDRS register R W Slave address Address R W Processing by program 2 Instruction of start condition generation 3 Data write to ICDRT register 1st byte A 4 Data write to ICDR...

Page 232: ...register to the SDA pin at the 9th clock cycle of the receive clock 3 The 1 frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the 9th clock cycle At thi...

Page 233: ...L master output 1 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 1 2 SDA slave output TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 ICDRR register ICDRS register Data 1 Processing by program 1...

Page 234: ...aster output SCL master output 1 2 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 SDA slave output 1 0 RCVD bit in ICCR1 register 1 0 ICDRR register ICDRS register Data n 1 Processing by program 6 Stop conditi...

Page 235: ...s matches in slave receive mode 2 When the slave address matches at the 1st frame after detecting the start condition the slave device outputs the level set by the ACKBT bit in the ICIER register to t...

Page 236: ...1 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 1 2 SDA slave output TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 ICDRR register ICDRS register Data 1 Processing by program A Data 2 9 TRS bi...

Page 237: ...t SCL master output 1 2 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 SDA master output TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 ICDRT register ICDRS register Data n Processing by program 3...

Page 238: ...0 and wait until the slave address matches in slave receive mode 2 When the slave address matches at the 1st frame after detecting the start condition the slave device outputs the level set in the AC...

Page 239: ...5 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 1 2 SDA slave output ICDRR register ICDRS register Data 1 Processing by program A 2 Dummy read of ICDRR register Data 1 9 RDRF bit in ICSR register 1 0 A 2 Read ICDRR r...

Page 240: ...n the ICCR1 register is set to 1 the transfer clock is output from the SCL pin and when the MST bit is set to 0 the external clock is input The transfer data is output between successive falling edges...

Page 241: ...gister is set to 1 by selecting transmit mode after setting the TRS bit in the ICCR1 register to 1 3 Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1 by wri...

Page 242: ...receive operation is completed Since the next byte of data is enabled when the MST bit is set to 1 the clock is output continuously Continuous reception is enabled by reading the ICDRR register every...

Page 243: ...e Canceller The noise canceller consists of two cascaded latch and match detector circuits When the SCL pin input signal or SDA pin input signal is sampled on f1 and two latch outputs match the level...

Page 244: ...esistor on the SCL line Therefore the SCL signal is monitored and communication is synchronized bit by bit Figure 16 45 shows the Timing of Bit Synchronization Circuit and Table 16 8 lists the Time be...

Page 245: ...pt the last byte 8 Wait until the ICRDT register is empty 9 Set the transmit data of the last byte 10 Wait for end of transmission of the last byte 11 Set the TEND bit to 0 12 Set the STOP bit to 0 13...

Page 246: ...he stop condition 12 Wait until the stop condition is generated 13 Read the receive data of the last byte 14 Set the RCVD bit to 0 15 Set to slave receive mode ICCR1 register TRS bit 0 Dummy read in I...

Page 247: ...3 Wait until the ICRDT register is empty 4 Set the transmit data of the last byte 5 Wait until the last byte is transmitted 6 Set the TEND bit to 0 7 Set to slave receive mode 8 Dummy read the ICDRR r...

Page 248: ...the receive data 7 Set the ACKBT bit of the last byte 1 8 Read the receive data of last byte 1 9 Wait until the last byte is received 10 Read the receive data of the last byte Dummy read in ICDRR reg...

Page 249: ...Interface Wait for three instructions or more or four cycles or more after writing to the same register among the registers associated with the I2C bus Interface 00B8h to 00BFh before reading it An ex...

Page 250: ...sult will be 3FFh in 10 bit mode and FFh in 8 bit mode 2 The frequency of AD must be 10 MHz or below Without a sample and hold function the AD frequency should be 250 kHz or above With a sample and ho...

Page 251: ...gister AD register ADCON0 Decoder Vcom VIN P1_0 AN8 CH2 to CH0 100b P1_1 AN9 CH2 to CH0 101b P1_2 AN10 CH2 to CH0 110b P1_3 AN11 CH2 to CH0 111b ADGSEL0 1 ADGSEL0 0 ADCAP 1 Software trigger ADCAP 0 Tr...

Page 252: ...s at capture timer Z interrupt request RW 0 One shot mode 1 Repeat mode RW RW ADGSEL0 RW A D input group select bit 0 Disabled 1 Enabled AN8 to AN11 CH1 RW CH0 CH2 RW Analog input pin select bits 2 b2...

Page 253: ...D conversion method select bit Nothing is assigned If necessary set to 0 When read the content is 0 b7 b4 b3 b1 RW Reserved bits Set to 0 b7 b6 b5 b4 0 b3 b2 b1 b0 0 0 A D Register Symbol Address Afte...

Page 254: ...he input voltage of one pin selected by bits CH2 to CH0 is A D converted once Start conditions When the ADCAP bit is set to 0 software trigger set the ADST bit to 1 A D conversion starts When the ADCA...

Page 255: ...tart bit 0 Starts at softw are trigger ADST bit 1 Starts at capture timer Z interrupt RW 0 One shot mode RW RW ADGSEL0 RW A D input group select bit 0 Disabled 1 Enabled AN8 to AN11 CH1 RW CH0 CH2 RW...

Page 256: ...ode Specifications Item Specification Function The Input voltage of one pin selected by bits CH2 to CH0 is A D converted repeatedly Start conditions When the ADCAP bit is set to 0 software trigger set...

Page 257: ...g input pin again Set AD frequency to 10 MHz or below CKS0 Frequency select bit 0 When CKS1 in ADCON1 register 0 0 Selects f4 1 Selects f2 When CKS1 in ADCON1 register 1 0 Selects f1 4 1 fRING fast RW...

Page 258: ...A D Conversion Cycles Figure 17 7 A D Conversion Cycles Sampling time 4 AD cycles Sample and Hold disabled Conversion time of 1st bit 2nd bit Comparison time Sampling time 2 5 AD cycles Comparison tim...

Page 259: ...rox 0 6 k ON resistor approx 2 k Wiring resistor approx 0 2 k i ladder type switches A D control register 0 ON resistor approx 0 6 k f Analog input voltage Sampling control signal ON resistor approx 5...

Page 260: ...ied Figure 17 9 Configuration of Inflow Current Bypass Circuit Figure 17 10 Example of Inflow Current Bypass Circuit where VCC or More is Applied To the internal logic of the A D Converter Unselected...

Page 261: ...etween pins VC changes from 0 to VIN 0 1 1024 VIN in time T 0 1 1024 means that A D precision drop due to insufficient capacitor charge is held to 0 1LSB at time of A D conversion in the 10 bit mode A...

Page 262: ...ing the A D operating mode select an analog input pin again When using the one shot mode ensure that A D conversion is completed before reading the AD register The IR bit in the ADIC register or the A...

Page 263: ...blank areas are used before performing an erase operation Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks It is also advisable to reta...

Page 264: ...ten by executing software commands from the CPU EW0 mode Rewritable in any area other than flash memory EW1 mode Rewritable in flash memory User ROM area is rewritten by a dedicated serial programmer...

Page 265: ...to is set 0 rewrite enabled block 1 is rewritable The rewrite control program for standard serial I O mode is stored in the boot ROM area before shipment The boot ROM area and the user ROM area share...

Page 266: ...is rewritable only for CPU rewrite mode 2 This area is for storing the boot program provided by Renesas Technology 02400h 02BFFh 0D000h User ROM area 0DFFFh 0E000h 0FFFFh 02400h 02BFFh Block 1 8 Kbyt...

Page 267: ...8 bits of data each the areas of which beginning with the first byte are 00FFDFh 00FFE3h 00FFEBh 00FFEFh 00FFF3h 00FFF7h and 00FFFBh Write programs in which the ID codes are set at these addresses an...

Page 268: ...ndard serial I O mode Figure 18 4 OFS Register Option Function Select Register 1 Symbol Address Before Shipment OFS 0FFFFh FFh 2 Bit Symbol Bit Name Function RW Reserved bit NOTES 1 2 b7 b6 b5 b4 b3 b...

Page 269: ...chip mode Single chip mode Areas in which a rewrite control program can be located User ROM area User ROM area Areas in which a rewrite control program can be executed Necessary to transfer to any are...

Page 270: ...rewrite mode enabled The FMR0 register can be used to determine when program and erase operations complete Do not execute software commands that use the read status register in EW1 mode To enable the...

Page 271: ...amming in EW0 mode FMR00 bit not reset to 1 ready When entering on chip oscillator mode main clock stops Figure 18 11 shows a flowchart of the steps to be followed before and after entering on chip os...

Page 272: ...n the MCU enters program suspend mode Set the FMR42 bit to 0 program restart when the auto program operation restarts 18 4 2 13 FMR43 Bit When the auto erase operation starts the FMR43 bit is set to 1...

Page 273: ...o not generate an interrupt betw een setting the bit to 0 and setting it to 1 Enter read array mode and set this bit to 0 Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit...

Page 274: ...rite 1 Disables rew rite When the FMR01 bit is set to 1 CPU rew rite mode enabled bits FMR15 and FMR16 can be w ritten to To set this bit to 0 set it to 0 immediately after setting it first to 1 To s...

Page 275: ...R40 FMR42 FMR44 b7 b6 b5 b4 RW RW Erase suspend function enable bit 1 0 Disables reading 1 Enables reading Reserved bits 0 Disable 1 Enable Erase suspend request bit 2 0 Erase restart 1 Erase suspend...

Page 276: ...e Duringprogramming Duringprogramming Erasure restarts Erasure ends During erasure Check that the FMR43 bit is set to 1 during erase execution and that the erase operation has not ended Check that the...

Page 277: ...he read array command 3 Execute software commands Write 0 to the FMR01 bit CPU rewrite mode disabled Jump to a specified address in the flash memory Rewrite control program NOTES 1 Select 5 MHz or bel...

Page 278: ...clock source for the CPU clock Turn XIN off Process in on chip oscillator mode main clock stops Write 0 to the FMR01 bit CPU rewrite mode disabled Jump to a specified address in the flash memory On ch...

Page 279: ...sses can be read continuously In addition the MCU enters read array mode after a reset 18 4 3 2 Read Status Register Command The read status register command is used to read the status register When 7...

Page 280: ...MR02 bit in the FMR0 register is set to 0 rewriting disabled or the FMR02 bit is set to 1 rewrite enabled and the FMR15 bit in the FMR1 register is set to 1 rewriting disabled program commands targeti...

Page 281: ...Mode FMR40 1 Maskable interrupt 2 REIT Access flash memory FMR42 0 NOTES 1 In EW0 mode the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area 2...

Page 282: ...erase commands targeting block 0 are not acknowledged When the FMR16 bit is set to 1 rewriting disabled the block erase commands targeting block 1 are not acknowledged Do not use the block erase comm...

Page 283: ...Yes EW1 Mode I 1 enable interrupt Maskable interrupt 2 REIT Access flash memory FMR41 0 NOTES 1 In EW0 mode the interrupt vector table and interrupt routine for interrupts to be used should be allocat...

Page 284: ...bits indicate the operating status of the flash memory SR7 is set to 0 busy during auto programming and auto erasure and is set to 1 ready at the same time the operation completes 18 4 4 2 Erase Stat...

Page 285: ...R07 SR5 FMR06 SR4 1 1 Command sequence error When a command is not written correctly When invalid data other than that which can be written in the second bus cycle of the block erase command is writte...

Page 286: ...No Yes Yes No Yes No Command sequence error Erase error Program error Command sequence error Execute the clear status register command set these status flags to 0 Check if command is properly input Re...

Page 287: ...the Pin Functions Flash Memory Standard Serial I O Mode 3 Figure 18 17 shows Pin Connections for Standard Serial I O Mode 3 After processing the pins shown in Table 18 8 and rewriting the flash memory...

Page 288: ...mic resonator or crystal oscillator between pins XIN and XOUT when connecting external oscillator Apply H and L or leave the pin open when using as input port P4_7 XOUT P4_7 input clock output I O AVC...

Page 289: ...Serial I O Mode 3 NOTE 1 It is not necessary to connect an oscillating circuit when operating with the on chip oscillator clock VSS MODE Connect oscillator circuit 1 Package PLSP0020JB A Mode Setting...

Page 290: ...1 In this example modes are switched between single chip mode and standard serial I O mode by controlling the MODE input with a switch 2 Connecting an oscillator is necessary Set the main clock frequ...

Page 291: ...se a parallel programmer which supports this MCU Contact the manufacturer of the parallel programmer for more information and refer to the user s manual of the parallel programmer for details on how t...

Page 292: ...n ROM 2 Do not use a non maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0 Table 18 9 EW0 Mode Interrupts Mode Status When Maskable Interr...

Page 293: ...e is suspended after td SR SUS and interrupt handling is executed Auto erasure can be restarted by setting the FMR41 bit in the FMR4 register to 0 erase restart after interrupt handling completes Once...

Page 294: ...ly voltage 0 V AVSS Analog supply voltage 0 V VIH Input H voltage 0 8VCC VCC V VIL Input L voltage 0 0 2VCC V IOH sum Peak sum output H current Sum of all pins IOH peak 60 mA IOH peak Peak output H cu...

Page 295: ...and FFh in 8 bit mode Figure 19 1 Port P1 P3 and P4 Measurement Circuit Table 19 3 A D Converter Characteristics Symbol Parameter Conditions Standard Unit Min Typ Max Resolution Vref VCC 10 Bits Absol...

Page 296: ...e performing an erase operation For example when programming groups of 16 bytes the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operati...

Page 297: ...peration For example when programming groups of 16 bytes the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation It is also advisable...

Page 298: ...gister to 0 4 Ensure that Vdet2 Vdet1 Table 19 6 Voltage Detection 1 Circuit Electrical Characteristics Symbol Parameter Condition Standard Unit Min Typ Max Vdet1 Voltage detection level 3 2 70 2 85 3...

Page 299: ...C tw por2 0s 3 100 ms Table 19 9 Reset Circuit Electrical Characteristics When Not Using Voltage Monitor 1 Reset Symbol Parameter Condition Standard Unit Min Typ Max Vpor1 Power on reset valid voltag...

Page 300: ...s during power on 3 Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode Table 19 10 High Speed On Chip Oscillator Circuit Electrical Characteristics Symbol Paramet...

Page 301: ...Unit Min Typ Max tSUCYC SSCK clock cycle time 4 tCYC 2 tHI SSCK clock H width 0 4 0 6 tSUCYC tLO SSCK clock L width 0 4 0 6 tSUCYC tRISE SSCK clock rising time Master 1 tCYC 2 Slave 1 s tFALL SSCK cl...

Page 302: ...or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tOD tH tSU SCS output SSCK output CPOS 1 SSCK output CPOS 0 SSO output SSI input 4 Wire Bus Communication Mode Master CPHS 1 VIH or VOH VIH or VOH...

Page 303: ...OH SCS input SSCK input CPOS 1 SSCK input CPOS 0 SSO input SSI output 4 Wire Bus Communication Mode Slave CPHS 1 VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tH tSU SCS input SSCK input CP...

Page 304: ...teristics Rev 1 30 Dec 08 2006 Page 286 of 315 REJ09B0252 0130 Figure 19 6 I O Timing of Clock Synchronous Serial I O with Chip Select Clock Synchronous Communication Mode VIH or VOH tHI tLO tSUCYC tO...

Page 305: ...tSCLH SCL input H width 3tCYC 300 2 ns tSCLL SCL input L width 5tCYC 300 2 ns tsf SCL SDA input fall time 300 ns tSP SCL SDA input spike pulse rejection time 1tCYC 2 ns tBUF SDA input bus free time 5...

Page 306: ...OW IOH 500 A VCC 2 0 VCC V VOL Output L voltage Except P1_0 to P1_3 XOUT IOL 5 mA 2 0 V IOL 200 A 0 45 V P1_0 to P1_3 Drive capacity HIGH IOL 15 mA 2 0 V Drive capacity LOW IOL 5 mA 2 0 V Drive capaci...

Page 307: ...scillator off Low speed on chip oscillator on 125 kHz Divide by 8 3 mA XIN 10 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 2 mA High speed on c...

Page 308: ...ove Figure 19 10 TCIN Input INT3 Input Timing Diagram when VCC 5 V Table 19 16 XIN Input Symbol Parameter Standard Unit Min Max tc XIN XIN input cycle time 50 ns tWH XIN XIN input H width 25 ns tWL XI...

Page 309: ...clock frequency x 3 or the minimum value of standard whichever is greater Figure 19 12 External Interrupt INT0 Input Timing Diagram when VCC 5 V Table 19 19 Serial Interface Symbol Parameter Standard...

Page 310: ...rive capacity LOW IOH 50 A VCC 0 5 VCC V VOL Output L voltage Except P1_0 to P1_3 XOUT IOL 1 mA 0 5 V P1_0 to P1_3 Drive capacity HIGH IOL 2 mA 0 5 V Drive capacity LOW IOL 1 mA 0 5 V XOUT Drive capac...

Page 311: ...lator off Low speed on chip oscillator on 125 kHz Divide by 8 2 5 mA XIN 10 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 1 6 mA High speed on c...

Page 312: ...ve Figure 19 15 TCIN Input INT3 Input Timing Diagram when VCC 3 V Table 19 23 XIN Input Symbol Parameter Standard Unit Min Max tc XIN XIN input cycle time 100 ns tWH XIN XIN input H width 40 ns tWL XI...

Page 313: ...clock frequency x 3 or the minimum value of standard whichever is greater Figure 19 17 External Interrupt INT0 Input Timing Diagram when VCC 3 V Table 19 26 Serial Interface Symbol Parameter Standard...

Page 314: ...WAIT instruction Program example to execute the WAIT instruction BCLR 1 FMR0 CPU rewrite mode disabled FSET I Enable interrupt WAIT Wait mode NOP NOP NOP NOP 20 1 3 Oscillation Stop Detection Functio...

Page 315: ...ich has the highest priority among the enabled interrupts is set to 0 This may cause the interrupt to be canceled or an unexpected interrupt to be generated 20 2 2 SP Setting Set any value in the SP b...

Page 316: ...t Sources Figure 20 1 Example of Procedure for Changing Interrupt Sources NOTES 1 Execute the above settings individually Do not execute two or more settings at once by one instruction 2 Use the I fla...

Page 317: ...rrupt not requested it may not be set to 0 depending on the instruction used Therefore use the MOV instruction to set the IR bit to 0 c When disabling interrupts using the I flag set the I flag as sho...

Page 318: ...er the TXS bit is set to 1 Also after writing 0 count stops to the TXS bit during the count timer X stops counting at the following count source 1 count starts can be read by reading the TXS bit until...

Page 319: ...20 3 3 Notes on Timer C Access registers TC TM0 and TM1 in 16 bit units The TC register can be read in 16 bit units This prevents the timer value from being updated between when the low order bytes a...

Page 320: ...U0RB register and the RI bit in the U0C1 register are set to 0 To check receive errors read the UiRB register and then use the read data Example when reading receive buffer register MOV W 00A6H R0 Re...

Page 321: ...ial I O with chip select 00B8h to 00BFh or four cycles or more after writing to them read the registers An example of waiting three instructions or more Program example MOV B 00h 00BBh Set the SSER re...

Page 322: ...ait for three instructions or more or four cycles or more after writing to the same register among the registers associated with the I2C bus Interface 00B8h to 00BFh before reading it An example of wa...

Page 323: ...ng the A D operating mode select an analog input pin again When using the one shot mode ensure that A D conversion is completed before reading the AD register The IR bit in the ADIC register or the AD...

Page 324: ...ROM 2 Do not use a non maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0 Table 20 1 EW0 Mode Interrupts Mode Status When Maskable Interru...

Page 325: ...is suspended after td SR SUS and interrupt handling is executed Auto erasure can be restarted by setting the FMR41 bit in the FMR4 register to 0 erase restart after interrupt handling completes Once...

Page 326: ...Control Registers During rigorous noise testing or the like external noise mainly power supply system noise can exceed the capacity of the MCU s internal noise control circuitry In such cases the cont...

Page 327: ...registers 2 Some of the user flash memory and RAM areas are used by the on ship debugger These areas cannot be accessed by the user Refer to the on chip debugger manual for which areas are used 3 Do n...

Page 328: ...e PLSP0020JB A 20P2F A MASS Typ 0 1g P LSSOP20 4 4x6 5 0 65 0 2 0 15 0 13 Max Nom Min Dimension in Millimeters Symbol Reference 6 6 6 5 6 4 D 4 5 4 4 4 3 E 1 15 A2 6 6 6 4 6 2 1 45 A 0 2 0 1 0 0 7 0 5...

Page 329: ...0 D2 0 05 y bp A1 x 0 05 e 0 5 Lp E1 2 0 0 0 0 05 A 0 8 A2 0 75 E 4 9 5 0 5 1 D 4 9 5 0 5 1 Reference Symbol Dimension in Millimeters Min Nom Max 0 15 0 2 0 25 0 5 0 6 0 7 P HWQFN28 5x5 0 50 0 05g MAS...

Page 330: ...2 Connection Example with E8 Emulator R0E000080KCE00 VSS VCC RXD 4 7 VSS 1 VCC 10 M16C flash starter M3A 0806 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 R8C 1A R8C 1B Group RXD TXD TXD RESET M...

Page 331: ...ix 3 Example of Oscillation Evaluation Circuit Appendix Figure 3 1 shows an Example of Oscillation Evaluation Circuit Appendix Figure 3 1 Example of Oscillation Evaluation Circuit VSS Connect oscillat...

Page 332: ...HRA2 64 I ICCR1 202 ICCR2 203 ICDRR 208 ICDRS 208 ICDRT 207 ICIER 205 ICMR 204 ICSR 206 INT0F 91 INT0IC 84 INT1IC 83 INT3IC 83 INTEN 91 K KIEN 97 KUPIC 83 O OCD 62 OFS 104 250 P P1 29 P3 29 P4 30 PD1...

Page 333: ...44 TCC1 145 TCIC 83 TCOUT 146 TCSS 111 127 TM0 143 TM1 143 TX 111 TXIC 83 TXMR 110 TZIC 83 TZMR 124 TZOC 126 TZPR 125 TZSC 125 U U0BRG 154 U0C0 156 U0C1 157 U0MR 155 U0RB 154 U0TB 154 U1BRG 154 U1C0 1...

Page 334: ...sed Analog Power Supply Input added 11 Figure 2 1 CPU Register Reserved Area Reserved Bit revised 13 2 8 10 Reserved Area Reserved Area Reserved Bit revised 15 3 2 R8C 1B Group Figure 3 2 Memory Map o...

Page 335: ...tion Stop Detection Function Since the oscillation frequency is 2MHz or below Since the oscillation frequency is below 2MHz revised 10 6 4 High Speed On Ship Oscillator Clock added 85 Figure 12 10 Jud...

Page 336: ...3 A D Converter Characteristics Vref and VIA Standard value NOTE4 revised 271 Table 19 4 Flash Memory Program ROM Electrical Characteristics NOTES3 and 5 revised NOTE8 deleted 272 Table 19 5 Flash Me...

Page 337: ...12 NOTE 1 revised 151 Figure 15 3 NOTE 3 added 153 Figure 15 5 NOTE 1 added 166 Table 16 1 revised 167 Table 16 2 NOTE 1 deleted 175 Figure 16 8 SS Transmit Data Register The last NOTE 1 deleted 182...

Page 338: ...Reset When read the content is undefined added 120 Figure 14 10 pulled up added NOTE 6 In this case of the read out buffer deleted NOTE 7 deleted 164 Figure 15 10 revised 172 Figure 16 3 SSCRL NOTE 2...

Page 339: ...o check receive errors read the UiRB register and then use the read data added 202 Figure 16 24 NOTE 1 revised 234 Figure 17 2 ADCON0 NOTE 2 revised 236 Table 17 2 Stop conditions when the ADCAP bit i...

Page 340: ...1B Group Hardware Manual Publication Date Rev 0 10 Jun 30 2005 Rev 1 30 Dec 08 2006 Published by Sales Strategic Planning Div Renesas Technology Corp 2006 Renesas Technology Corp All rights reserved...

Page 341: ...1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan R8C 1A Group R8C 1B Group REJ09B0252 0130 Hardware Manual...

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