R8C/1A Group, R8C/1B Group
16. Clock Synchronous Serial Interface
Rev.1.30
Dec 08, 2006
Page 225 of 315
REJ09B0252-0130
16.3.5
Noise Canceller
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.44 shows a Block Diagram of Noise Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
Figure 16.44
Block Diagram of Noise Canceller
C
D
Q
Latch
C
D
Q
Latch
Match
detection
circuit
SCL or SDA
input signal
Internal SCL
or SDA signal
f1 (sampling clock)
Period of f1
f1 (sampling clock)
