R8C/1A Group, R8C/1B Group
12. Interrupts
Rev.1.30
Dec 08, 2006
Page 89 of 315
REJ09B0252-0130
12.1.6.8
Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved to the stack, are automatically restored. The program, that was running before the interrupt request
was acknowledged, starts running again.
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before
executing the REIT instruction.
12.1.6.9
Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).
However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by
hardware, and the higher priority interrupts acknowledged.
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set
by hardware. Figure 12.9 shows the Priority Levels of Hardware Interrupts.
The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the
instruction is executed.
Figure 12.9
Priority Levels of Hardware Interrupts
Reset
Watchdog timer
Oscillation stop detection
Voltage monitor 2
Peripheral function
Single step
Address match
High
Low
Address break
