R8C/1A Group, R8C/1B Group
16. Clock Synchronous Serial Interface
Rev.1.30
Dec 08, 2006
Page 206 of 315
REJ09B0252-0130
Figure 16.28
ICSR Register
IIC bus Status Register
(7)
Symbol
Address
After Reset
ICSR
00BCh
0000X000b
Bit Symbol
Bit Name
Function
RW
NOTES :
1.
2.
3.
4.
5.
6.
7.
STOP
Stop condition detection
flag
(1)
When the stop condition is detected after the frame
is transferred, this flag is set to 1.
RW
The RDRF bit is set to 0 when reading data f rom the ICDRR register.
Bits TEND and TDRE are set to 0 when writing data to the ICDRT register.
When two or more master dev ices attempt to occupy the bus at nearly the same time, if the I2C bus Interf ace monitors the SDA pin
and the data which the I2C bus Interf ace transmits is dif f erent, the AL f lag is set to 1 and the bus is occupied by another master.
RW
RDRF
Receive data register
full
(1,5)
When the 9th clock cycle of the SCL signal in the I
2
C
bus format occurs w hile the TDRE bit is set to 1, this
flag is set to 1.
This flag is set to 1 w hen the final bit of the transmit
frame is transmitted in the clock synchronous format.
No acknow ledge detection
flag
(1,4)
This f lag is enabled in slav e receiv e mode of the I
2
C bus f ormat.
Each bit is set to 0 by reading 1 bef ore writing 0.
NACKF
When no ACKnow ledge is detected from receive
device after transmission, this flag is set to 1.
RW
RW
When receive data is transferred from registers
ICDRS to ICDRR, this flag is set to 1.
TEND
Transmit end
(1,6)
RW
RW
General call address
recognition flag
(1,2)
When the general call address is detected , this flag
is set to 1.
Arbitration lost flag /
overrun error flag
(1)
When the I2C bus format is used, this flag indicates
that arbitration has been lost in master mode. In the
follow ing cases, this flag is set to 1
(3)
.
• When the internal SDA signal and SDA pin
level do not match at the rise of the SCL signal
in master transmit mode.
• When the start condition is detected and the
SDA pin is held “H” in master transmit/receive
mode.
This flag indicates an overrun error w hen the clock
synchronous format is used.
In the follow ing case, this flag is set to 1.
• When the last bit of the next data item is
received w hile the RDRF bit is set to 1.
Slave address recognition
flag
(1)
This flag is set to 1 w hen the first frame follow ing
start condition matches bits SVA0 to SVA6 in the
SAR register in slave receive mode. (Detect the
slave address and generate call address.)
RW
AAS
AL
ADZ
b2 b1
b7 b6 b5 b4
Ref er to
16.3.8.1 Accessing of Registers Associated with I
2
C bus Interface
f or more inf ormation.
b0
The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receiv e acknowledge bit is set to 1, transf er is
halted).
TDRE
Transmit data empty
(1,6)
In the follow ing cases, this flag is set to 1.
• Data is transferred from registers ICDRT to ICDRS
and the ICDRT register is empty.
• When setting the TRS bit in the ICCR1
register to 1 (transmit mode).
• When generating the start condition
(including retransmit).
• When changing from slave receive mode to
slave transmit mode.
RW
b3
