R8C/1A Group, R8C/1B Group
16. Clock Synchronous Serial Interface
Rev.1.30
Dec 08, 2006
Page 218 of 315
REJ09B0252-0130
Figure 16.37
Operating Timing in Slave Transmit Mode (I
2
C bus Interface Mode) (1)
SDA
(master output)
SCL
(master output)
1
8
9
6
7
4
5
3
b7
b6
b5
b4
b3
b2
b1
b0
b7
1
2
SDA
(slave output)
TDRE bit in
ICSR register
1
0
TEND bit in
ICSR register
1
0
ICDRR register
ICDRS register
Data 1
Processing
by program
A
Data 2
9
TRS bit in
ICCR1 register
1
0
A
Slave transmit mode
Slave receive mode
SCL
(slave output)
ICDRT register
Data 1
(1) Data write to ICDRT
register (data 1)
(2) Data write to ICDRT
register (data 2)
Data 2
(2) Data write to ICDRT
register (data 3)
Data 3
