PAC25140 Users Guide Preview
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Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
47 of 77
SOC.HIBENTER
Register 8-7
. SOC.HIBENTER (Hibernate Enter, SOC 0x06)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7:1
RFU
R
0
Reserved, write as 0.
0
HIB
R/W
0x0
Hibernate
Write to 1 to enter
Hibernate. This bit is
automatically cleared
upon wakeup.
SOC.RSTSTAT
Register 8-8
. SOC.RSTSTAT (Reset Status, SOC 0x07)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7:5
RFU
R
0x0
Reserved
4
PBRST
W1C
0x0
Push Button Reset Flag
This flag will be set when the Push Button is
enabled and has been active for 8 seconds.
3
HIBRST
W1C
0x0
Hibernate Reset Flag
This flag will be set when the device has
been reset following a hibernate wake-up.
Read the HIBCTL.WAKESRC bits to
determine the source of the hibernate wake-
up.
2
WDTRST
W1C
0x0
AFE Watchdog Timer Reset Flag
This flag will be set when the device has
been reset by the AFE Watchdog Timer
1
SOFTRST
W1C
0x0
Soft Reset Flag
This flag will be set when an AFE Soft Reset
has been performed by writing a 1 to
SOC.AFECTL1.SRST.
0
FLTRST
W1C
0x0
Fault Reset Flag
This flag will be set when a power or
temperature fault occurs that causes a
device reset. The following faults may cause
a Fault Reset.
Power Faults: VPFLT,
VSYSFLT,VDDIOFLT,VDDAFLT,VCOREFLT
Temp Faults: TMPFLT
Following a Fault Reset, read the
PWRFAULT and TEMPFAULT registers to
determine which faults caused the reset.
