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PAC25140 Users Guide Preview
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Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
43 of 77
SOC.AFECTL1
Register 8-1
. SOC.AFECTL1 (AFE Control 1, SOC 0x00)
BIT
NAME
ACCESS
RESET
DIFFAMP MODE
7
SRST
RW
0
Soft Reset
Write to 1 to reset the device. The majority of AFE registers will be
reset also unless noted.
This bit is self clearing and will always be read as 0.
6
MCUALIVE
RW
0
MCU Alive
This bit should be written to 1 by the MCU after it comes out of
reset. Prior to setting this bit, the AFE will only respond to SPI
transactions.
5:3
RFU
R
0
Reserved, write as 0.
3
LOADDETEN
RW
0x0
Load Detect Enable
0: Disabled
1: Enabled
When enabled, measure PACK+ to determine if a load is present.
2
HVCPEN
RW
0x0
High Voltage Charge Pump Enable
0: Disabled
1: Enabled
0
SIGEN
RW
0x0
Signal Manager Tile Enable
0: disabled
1: enabled
SOC.AFECTL2
Register 8-2
. SOC.AFECTL2 (AFE Control 2, SOC 0x01)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7:3
RFU
R
0x0
Reserved
2:1
BK_FREQ
R/W
0x1
High Voltage Buck
Switching Frequency:
0: 50kHz
1: 100kHz
2: 200kHz
3: 400KHz
0
VP_PD_DIS
R/W
0
VP Pull Down Disable