PAC25140 Users Guide Preview
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Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
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6.5.3 SOC.MISC
Register 6-3 SOC.MISC (SOC Miscellaneous Configuration, 02h)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7
HIB
R/W
0x0
Hibernate Mode. This bit is automatically cleared when the
power up sequence is initiated, after wake-up timer delay or
external event.
0b: Normal
1b: Shutdown mode
6
PBEN
R/W
0x0
AIO6 Push-button Enable.
0b: Push-button not enabled
1b: Push-button enabled
5
VREFSET
R/W
0x0
ADC Reference Voltage Setting.
0b: 2.5V
1b: 3.0V
4
CLKOUTEN
R/W
0x0
Low-speed clock output (CLKOUT) enable.
0b: Not enabled
1b: Enabled
3
MCUALIVE
R/W
0x0
MCU Alive. Set by the MCU to indicate that it is alive. Before
this bit is set, ignore all MCU commands (EMUX, gate driver)
except SPI register commands. This bit will automatically be
cleared when the reset signal to the MCU is asserted.
0b: MCU not alive
1b: MCU alive
2
TPBD
R/W
0x0
Push-button deglitch time:
0b: 32ms
1b: 1ms
1
RFU
R
0x0
Reserved
0
SMEN
R/W
0x0
Signal Manager Enable. This bit is automatically cleared
when the reset signal to the MCU is asserted.
0b: Not enabled
1b: Enabled
