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PAC25140 Users Guide Preview

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SOC.VADCCTL

. SOC.VADCCTL (Voltage ADC Control, SOC 0x22)

BIT

NAME

ACCESS

RESET

DESCRIPTION

VADCSTART

R/W

0x0

Cell Voltage ADC
Start Conversion

VADCBUSY

0x0

Cell Voltage ADC
Busy
- This bit is set to 1
during conversion and
set to 0 when
complete.

RFU

Reserved

4:0

VBMUXSEL

R/W

0x0

Voltage ADC
MUX Select:

0: VB1
1: VB2
2: VB3
3: VB4
4: VB5
5: VB6
6: VB7
7: VB8
8: VB9
9: VB10
10: VB11
11: VB12
12: VB13
13: VB14
14: VB15
15: VB16
16: VB17
17: VB18
18: VB19
19: VB20
20: BATOVDAC
21 - 31: RFU

SOC.VADCRESHI

. SOC.VADCRESHI (Voltage ADC Result High, SOC 0x23)

BIT

NAME

ACCESS

RESET

DESCRIPTION

7:0

VADCRES[15:8]

Voltage ADC Result
MSByte

Summary of Contents for PAC25140

Page 1: ...attery Management PRODUCT USER GUIDE 1 of 77 PAC25140 User Guide Preview PAC Battery Management System Multi Mode Power ManagerTM Configurable Analog Front EndTM Application Specific Power DriversTM A...

Page 2: ...unctional Description 11 4 3 USART Configuration 12 4 4 Protocol 12 4 5 Write Register Example 12 4 6 Read Register Example 14 5 PAC25140 IO 15 5 1 Overview 15 5 2 ADC Channels 16 5 3 Digital Peripher...

Page 3: ...arge Protection 35 7 4 8 Battery Over Voltage Protection 35 7 4 9 Voltage Sensing 36 7 4 10 Measuring Independent Cell Voltages 36 7 4 11 AFE MUX 37 7 4 12 Enabling the CAFE 37 7 4 13 Push Button PB I...

Page 4: ...ter Access 11 Figure 4 2 Analog Peripheral Register Write Timing 12 Figure 4 3 Analog Peripheral Register Read Timing 14 Figure 5 1 GPIO and DPM Block Diagram 15 Figure 6 1 Power Manager System Block...

Page 5: ...written consent www qorvo com Rev 1 0 0 28 February 2023 2023 Qorvo US Inc 5 of 77 LIST OF TABLES Table 5 1 PAC25140 ADC Input Pins 16 Table 5 2 PAC25140 Digital Peripheral Pins 17 Table 6 1 CPM Regi...

Page 6: ...IGMGRCTL1 Signal Manager Control 1 SOC 0x11 50 Register 8 13 SOC SIGMGRCTL2 Signal Manager Control 2 SOC 0x12 50 Register 8 14 SOC PROTEN Reset Status SOC 0x13 50 Register 8 15 SOC FUSE Fuse Driver Co...

Page 7: ...e 3 SOC 0x32 61 Register 8 40 SOC CFGCB1 Configure Cell Balance 1 SOC 0x33 62 Register 8 41 SOC CFGCB2 Configure Cell Balance 2 SOC 0x34 62 Register 8 42 SOC CFGCB3 Configure Cell Balance 3 SOC 0x35 6...

Page 8: ...written consent www qorvo com Rev 1 0 0 28 February 2023 2023 Qorvo US Inc 8 of 77 1 OVERVIEW This document is the PAC25140 Device User Guide It details the operation of the analog peripherals in the...

Page 9: ...as a postfix For example 1011b binary Bh hexadecimal 11 decimal 2 2 Formatting Styles TYPE EXAMPLE DESCRIPTION Register Name RTCCTL Register names use a capital letter and boldface type Register Bit...

Page 10: ...140 Power Application Controller PX Y DEBUG ETM ARM CORTEX M4F CORE TIMERS 4 DEAD TIME 16 PWM CC 32 PWM ENGINE PX Y PX Y PX Y PX Y PX Y BRIDGE WWDT DTSE DATA ACQUISITION AND SEQUENCER 12 BIT ADC MUX 1...

Page 11: ...two register buses the AHB bus and the APB bus The AHB bus allows the MCU and Debug Port access to FLASH and SRAM via the Memory Controller To access other digital peripheral connected to the APB bus...

Page 12: ...e high CPH is sample setup SS active low When communicating with the Analog Peripherals the maximum SCLK frequency is 25MHz 4 4 Protocol The protocol for communicating with the Analog Peripherals is a...

Page 13: ...AC25140 Users Guide Preview No portion of this document may be reproduced or reused in any form without Qorvo s prior written consent www qorvo com Rev 1 0 0 28 February 2023 2023 Qorvo US Inc 13 of 7...

Page 14: ...ssue the following transactions to USART A Write SSPADAT with the value 22h 11h 1 0b for read transaction Write SSPADAT with a dummy character Read last data from MISO from SSPADAT this is the registe...

Page 15: ...pins Each member of the family has a different set of IO pins that are available It is important during application design that the designer consider the available IO pins to make sure the necessary p...

Page 16: ...ev 1 0 0 28 February 2023 2023 Qorvo US Inc 16 of 77 5 2 ADC Channels The ADC channels that are available on the PAC25140 are shown in the table below Table 5 1 PAC25140 ADC Input Pins ADC Channel MCU...

Page 17: ...TAPWM5 TBPWM5 P6 GPIOB6 TAPWM6 TBPWM6 GPIOC P4 GPIOC4 TBPWM4 TCPWM4 TCIDX USBMOSI USCSCLK CANRXD I2CSCL P5 GPIOC5 TBPWM5 TCPWM5 TCPHA USBMISO USCSS CANTXD I2CSDA GPIOD P0 GPIOD0 TBPWM0 TCPWM0 TDIDX US...

Page 18: ...ument may be reproduced or reused in any form without Qorvo s prior written consent www qorvo com Rev 1 0 0 28 February 2023 2023 Qorvo US Inc 18 of 77 For more information on how to configure the DPM...

Page 19: ...lock Diagram Figure 6 1 Power Manager System Block Diagram POWER MANAGER VP VOLTAGE SETTING POWER OK OVP LINEAR REG VSYS HIBERNATE 2 5V VREF POWER TEMP MON VMON VTEMP HIGH VOLTAGE BUCK CONTROLLER HV B...

Page 20: ...not running To enter hibernate mode configure the SOC HIBCTL register settings and the set SOC HIBENTER HIB to 1b This bit will be automatically cleared when exiting hibernate To wake up from hiberna...

Page 21: ...mperature sensor that is used for temperature warnings and faults and can also be sampled by the MCU ADC through the AFE MUX using the VPTAT MUX channel This value has a compensation coefficient avail...

Page 22: ...itten consent www qorvo com Rev 1 0 0 28 February 2023 2023 Qorvo US Inc 22 of 77 There is not interrupt for this condition When the device falls below the hysteresis value then the DC DC will be re e...

Page 23: ...Register Summary ADDRESS REGISTER DESCRIPTION RESET 00h SOC FAULT Fault condition indication register 00h 01h SOC STATUS Hardware status condition register 00h 02h SOC MISC Miscellaneous features regi...

Page 24: ...d and the SOC FAULTENABLE nTMPWARN is not masked this bit is set and nIRQ1 is asserted Write 1b to clear when not masked 0b No temperature warning 1b Temperature warning 5 TMPFLT R 0x0 Temperature fau...

Page 25: ...When enabled this bit is set on Watchdog Timer Reset and cleared when written to 1b 0b No WDT reset 1b WDT Reset 4 RFU R 0x0 Reserved 3 VPLOW R 0x0 Real time VP Low Status 0b No VP low 1b VP low 2 VPL...

Page 26: ...button Enable 0b Push button not enabled 1b Push button enabled 5 VREFSET R W 0x0 ADC Reference Voltage Setting 0b 2 5V 1b 3 0V 4 CLKOUTEN R W 0x0 Low speed clock output CLKOUT enable 0b Not enabled 1...

Page 27: ...S RESET DESCRIPTION 7 6 CLKOUTFREQ R W 0x0 Low Speed Clock Output Frequency Setting CLKOUT 00b 250Hz 01b 500Hz 10b 1kHz 11b 2kHz 5 3 PWRMON R W 0x0 Power Monitor Signal This field selects the signal t...

Page 28: ...ed for writing when UNLOCK 1b BIT NAME ACCESS1 RESET DESCRIPTION 7 RFU R W 0x0 Reserved 6 nTMPWARN R W 0x0 Temperature Warning Mask 0b Masked 1b Not masked asserts nIRQ1 5 nVPFLT R W 0x0 VP Fault Mask...

Page 29: ...DESCRIPTION 7 SRST R W 0x0 Soft Reset This bit can be set to issue a system soft reset This bit is always read as 0b When set the STATUS SRST bit will be latched to a 1b so the MCU knows the system i...

Page 30: ...ev 1 0 0 28 February 2023 2023 Qorvo US Inc 30 of 77 6 5 7 SOC SYSCONF Register 6 7 SOC SYSCONF System Configuration 2Bh BIT NAME ACCESS RESET DESCRIPTION 7 4 RFU R 0x0 Reserved 3 VPSET R W 0x1 VP Set...

Page 31: ...also sense cell voltages via a 16 bit Sigma Delta ADC and MUX which contains inputs for each of the cell balance channels Internal power supply rails temperature and other signals can be selected usi...

Page 32: ...is document may be reproduced or reused in any form without Qorvo s prior written consent www qorvo com Rev 1 0 0 28 February 2023 2023 Qorvo US Inc 32 of 77 7 3 System Block Diagram Figure 7 1 Config...

Page 33: ...16 bit Sigma Delta ADC for current sensing and also to over current protection comparators 7 4 3 IADC 16 bit Sigma Delta ADC The IADC is a 16 bit Sigma Delta ADC and has an input range of 500mV to 500...

Page 34: ...te drivers if the battery pack suddenly is discharging a large amount of current The SCP is implemented with the SCP DAC 0 5V Vref and SCP comparator 0 5V Vref to compare the DAC setting to the ISNSN...

Page 35: ...5V Vref to compare the DAC setting to the differential amplifier output signal If the comparator threshold is met the comparator will set the SOC SIGFAULT OCDFLT bit An active OCD Fault can be configu...

Page 36: ...ts each of the individual cell balance nodes VB1 to VB20 so that they may be sampled by the 16 bit ADC The SOC bus is used for the MUX select as well as the ADC operation and fetching of the 16 bit re...

Page 37: ...em Supply VP DC DC Output AIO0A AIO0 Analog Output BAT Battery Stack Input PACK Charger Supply Input VCP Charge Pump Output VREF 2 5V Voltage reference FUSE FUSE output CHG CHG FET gate driver signal...

Page 38: ...the PAC25140 from hibernate mode When enabled the push button may also be used as a hardware reset when held active for longer than 8s during normal operation Once the push button is enabled the pola...

Page 39: ...t of the gain amplifier AIO0A routed to the AFE Mux for input to the MCU ADC Or the AIO0 pin can be configured to output internal signals of the AFE The following signals are available for output on t...

Page 40: ...8 Miscellaneous 8 1 General Purpose Register The device contains an 8 bit general purpose register in the analog sub system that is available for user applications This register may be used to synchro...

Page 41: ...Push Button 0x09 AIO0CFG AIO 0 Configuration 0x10 PROTKEY Protection Key 0x11 SIGMGRCTL1 Signal Manager Control 1 0x12 SIGMGRCTL2 Signal Manager Control 2 0x13 PROTEN Protection Enable 0x14 FUSE Fuse...

Page 42: ...ction DAC 0x2B OCCCFG Over Current Charge Protection Configuration 0x2C OCCDAC Over Current Charge Protection DAC 0x2D OCDCFG Over Current Discharge Protection Configuraiton 0x30 CELLEN1 Cell Enable 1...

Page 43: ...MCU Alive This bit should be written to 1 by the MCU after it comes out of reset Prior to setting this bit the AFE will only respond to SPI transactions 5 3 RFU R 0 Reserved write as 0 3 LOADDETEN RW...

Page 44: ...ive SOC AFEMUXCTL Register 8 4 SOC AFEMUXCTL AFE Mux Control SOC 0x03 BIT NAME ACCESS RESET DESCRIPTION 7 2 RFU R 0 Reserved 1 BUFFEN RW 0x0 ADC Buffer Enable 0 Disabled 1 Enabled Enables the buffer a...

Page 45: ...f 77 4 0 AFEMUXSEL R W 0x0 AFE MUX Channel Selector 0 VCORE 1 VCORE 2 5 2 VDDA 2 5 3 VCCIO 2 5 4 VSYS 2 5 5 ISENSE 6 VPTAT 7 VP 10 8 VREF 2 9 FUSE 10 10 CHG 50 11 DSG 50 12 BAT 50 13 AIO0A 14 LOADDET...

Page 46: ...p Timer Duration 0 Disabled 1 125ms 2 250ms 3 500ms 4 1s 5 2s 6 4s 7 8s 4 3 WAKESRC R W 0x0 Wake Up Source 0 PB 1 PACK 2 WUTIMER 3 RFU 2 PACKWAKEVREF R W 0x0 PACK Wake Up Voltage Reference Threshold 0...

Page 47: ...and has been active for 8 seconds 3 HIBRST W1C 0x0 Hibernate Reset Flag This flag will be set when the device has been reset following a hibernate wake up Read the HIBCTL WAKESRC bits to determine the...

Page 48: ...terrupt Flag 5 PBINTEN R W 0x0 Push Button Interrupt Enable The interrupt is level sensitive 4 PBPOL R W 0x0 Push Button Polarity 0 Active Low 1 Active High Depending on other bit settings an active s...

Page 49: ...MUXOUT 2 IMUXOUT 3 VBMUXOUT 15 4 RFU 4 RFU R W 0x0 Reserved 3 2 SWAP R W 0x0 Swaps the offset of the buffer 0 No swap 1 Swap 1 MODE R W 0x0 AIO0 Buffer Mode 0 Input Buffer Mode 1 Output Buffer mode 2m...

Page 50: ...SIGMGRCTL2 Register 8 13 SOC SIGMGRCTL2 Signal Manager Control 2 SOC 0x12 BIT NAME ACCESS RESET DESCRIPTION 7 3 RFU R 0x0 Reserved 2 PBPTEN R W 0x0 Push Button Pass Through Enable 1 IADCEN R W 0x0 Cu...

Page 51: ...then when protection is activated the DSG FET will be disabled Note This register requires a write of PROT_KEY before register can be written SOC FUSE Register 8 15 SOC FUSE Fuse Driver Control SOC 0...

Page 52: ...C 0x15 BIT NAME ACCESS RESET DESCRIPTION 7 RFU R 0x0 Reserved 6 DRVFLTEN R W 0x0 Driver Fault Interrupt Enable 5 VCCIOFLTEN R W 0x0 VCCIO Fault Interrupt Enable 4 VDDAFLTEN R W 0x0 VDDA Fault Interrup...

Page 53: ...t to 1 then when TWARN2 occurs Cell Balancing will be disabled 4 TWARN1CBDEN R W 0x0 TWARN1 Cell Balance Disable If set to 1 then when TWARN1 occurs Cell Balancing will be disabled 3 RFU R 0x0 Reserve...

Page 54: ...2023 2023 Qorvo US Inc 54 of 77 3 SCPFLTEN R W 0x0 Short Circuit Protection Fault Interrupt Enable 2 OCCFLTEN R W 0x0 Over Current Charge Fault Interrupt Enable 1 OCDFLTEN R W 0x0 Over Current Discha...

Page 55: ...e protections trips and disables the CHG FET This bit must be written with a 1 to clear it before the CHG FET can be enabled again 5 DSGFLT W1C 0x0 DSG Fault Flag This flag will be set if a DSG Protec...

Page 56: ...Status SOC BATOVCFG Register 8 23 SOC BATOVCFG Battery Over Voltage Comparator Configuration SOC 0x20 BIT NAME ACCESS RESET DESCRIPTION 7 4 BLANKSF R W 0x0 Blanking Scale Factor 0 1 1 2 2 3 14 15 15 1...

Page 57: ...Cell Voltage ADC Start Conversion 6 VADCBUSY R 0x0 Cell Voltage ADC Busy This bit is set to 1 during conversion and set to 0 when complete 5 RFU R 0 Reserved 4 0 VBMUXSEL R W 0x0 Voltage ADC MUX Sele...

Page 58: ...SY R 0x0 Current ADC Busy This bit is set to 1 during conversion and set to 0 when complete 5 RFU R 0 Reserved 4 3 IMUXSEL 1 0 R W 0x0 0 Isense Diff Amp Output 1 SCP DAC 2 OCC DAC 3 OCD DAC 2 0 DAGAIN...

Page 59: ...CCESS RESET DESCRIPTION 7 4 BLANKSF R W 0x0 Blanking Scale Factor 0 1 1 2 2 3 14 15 15 16 3 0 TIMEBASE R W 0x0 Time Base 0 1uS 1 2uS 2 4uS 3 256uS 15 32768 uS Notes This register requires a write of P...

Page 60: ...SF 2 So Blanking Time 2uS 3 6uS OCD Comparator Hysteresis is fixed at 25mV SOC OCCDAC Register 8 35 SOC OCCDAC OCC DAC SOC 0x2C BIT NAME ACCESS RESET DESCRIPTION 7 0 OCCDAC RW 0 OCC DAC Setting This i...

Page 61: ...0 Cell 3 Enable 1 CEN2 R W 0x0 Cell 2 Enable 0 CEN1 R W 0x0 Cell 1 Enable SOC CELLEN2 Register 8 38 SOC CELLEN2 Cell Enable 2 SOC 0x31 BIT NAME ACCESS RESET DESCRIPTION 7 CEN16 R W 0x0 Cell 16 Enable...

Page 62: ...CFGCB2 Configure Cell Balance 2 SOC 0x34 BIT NAME ACCESS RESET DESCRIPTION 7 VB16 R W 0x0 Cell 16 Cell Balance Enable 6 VB15 R W 0x0 Cell 15 Cell Balance Enable 5 VB14 R W 0x0 Cell 14 Cell Balance En...

Page 63: ...Low Speed Clock Output Enable Note Used during clock test that can help meet Class B Safety SOC WWDTCTL Register 8 45 SOC WWDTCTL Windowed Watchdog Timer Control SOC 0x42 BIT NAME ACCESS RESET DESCRI...

Page 64: ...N Windowed Watchdog Timer Window SOC 0x45 BIT NAME ACCESS RESET DESCRIPTION 7 0 WINDOW 7 0 RW 0x0 WWDT Window Value If WWDTRST is written when CTR WINDOW then the WWDT will issue a device reset SOC WW...

Page 65: ...G and DSG FETs and external protection fuse FET for the battery pack The CHG and DSG FET gates are driven from the CHG and DSG pins The gate drive voltage for the CHG and DSG FETs is VCP BAT 9V The FU...

Page 66: ...for discharge of individual cells Voltage ADC for sensing the voltage of each cell 8 4 1 Block Diagram SOC BUS VB20 CFGCB3 VB20 VB MUX CFGCB3 VB19 VB20_SCL VB19 VB18 VB19_SCL VB18_SCL CFGCB3 VB18 CFG...

Page 67: ...mpling from the 16 bit ADC Adjacent cells should not be balanced at the same time In the event that too many cells are being balanced at the same time and Thermal protection occurs then the cell balan...

Page 68: ...AD4 PC4 Package pin AD5 PC5 Package pin AD6 PC6 Package pin The AD0 channel is always used for analog input from the AFE and is connected to the AFE MUX on MCU internal pin PC0 ADC channels AD 6 2 are...

Page 69: ...Analog Input Output 0 Amp Output LOADDET 14 Load Detection Voltage SCPDAC 15 SCP DAC Voltage OCCDAC 16 OCC DAC Voltage OCDDAC 17 OCD DAC Voltage BATOVDAC 18 BAT Over Voltage DAC VIN 19 VIN 50 PACK 20...

Page 70: ...er 8 50 EMUX Packet Structure BIT NAME DESCRIPTION 7 BIT7 Bit 7 should be set to 0b 6 BIT6 Bit 6 should be set to 1b 5 BIT5 Bit 5 should be set to 0b 4 0 AFEMUXSEL AFE MUX Channel Selector 0 VCORE 1 V...

Page 71: ...77 8 5 2 1 The EMUX data is written on this bus MSb first from the ADC sequencer See the timing diagram below Figure 9 1 EMUX Timing Diagram Bits 7 5 should contain 010b so that the EMUX controller w...

Page 72: ...p Interrupt Controller WIC included Sleep Mode power saving included Little Endian configuration 24 bit SysTick timer included Embedded Trace Module ETM included o Instruction trace only ARM provides...

Page 73: ...of 77 9 1 PAC25xxx Architecture Figure 9 1 Top Level Block Diagram PAC SOC BUS Power Application Controller 128kB FLASH 32kB SRAM CLOCK CONTROL RTC Calendar GPIO USART 3 I2C CAN SYSTEM CONTROL APB AH...

Page 74: ...ces 9 2 2 Features Clock Control System CCS o 4 clock sources 4MHz internally generated 2 RC oscillator 16MHz Ring Oscillator External clock input for up to 20MHz external clock sources Crystal driver...

Page 75: ...Preview No portion of this document may be reproduced or reused in any form without Qorvo s prior written consent www qorvo com Rev 1 0 0 28 February 2023 2023 Qorvo US Inc 75 of 77 Figure 9 2 Clock C...

Page 76: ...iew No portion of this document may be reproduced or reused in any form without Qorvo s prior written consent www qorvo com Rev 1 0 0 28 February 2023 2023 Qorvo US Inc 76 of 77 9 3 MCU MEMORY MAP Fig...

Page 77: ...h regard to such Users Guide Information itself or anything described by such information USERS GUIDE INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN AND QORVO...

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