Qorvo PAC25140, User Manual

Page: 44 / 77

PAC25140 Users Guide Preview
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Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
44 of 77
SOC.DRVCTL
Register 8-3
. SOC.DRVCTL (Driver Control, SOC 0x02)
BIT NAME ACCESS RESET DESCRIPTION
7:2 RFU R 0 Reserved
1:0 DRVMODE RW 0x0
Driver Mode
0: Drivers Disabled
1: Drivers Enabled -
MCU signals control
CHG/DSG on off.
2: Source Follower
Mode
3: Reserved
Driver Mode is set to 0
if SEGEN = 0 or if
nRST is active
SOC.AFEMUXCTL
Register 8-4
. SOC.AFEMUXCTL (AFE Mux Control, SOC 0x03)
BIT NAME ACCESS RESET DESCRIPTION
7:2 RFU R 0 Reserved
1 BUFFEN RW 0x0
ADC Buffer Enable
0: Disabled
1: Enabled
Enables the buffer
after the AFE Mux that
drives the signal
feeding channel 0 of
the ADC Mux.
0 EMUX_EN RW 0x0
EMUX Enable –
Enables the AFE
EMUX Module
0: Disabled
1: Enabled
When the EMUX is
enabled, writes to the
AFEMUXSEL will be
performed by the
EMUX logic. The
AFEMUXSEL cannot
be written by the SOC
Bridge SPI I/F, but can
be read over the SOC
Bridge SPI I/F.
Setting EMUX_EN = 0
will reset the AFE
EMUX module.
SOC.AFEMUXSEL
Register 8-5
. SOC.AFEMUXSEL (AFE Mux Select, SOC 0x04)
BIT NAME ACCESS RESET DESCRIPTION
7:5 RFU R 0 Reserved