PAC25140 Users Guide Preview
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Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
63 of 77
SOC.CLKOUTCFG
Register 8-44
. SOC.CLKOUTCFG (Clock Out Configuration, SOC 0x41)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7:3
RFU
R
0
Reserved
2:1
CLKOUTFREQ[1:0]
RW
0x0
Low-Speed Clock
Output Frequency
Setting
0: 250Hz
1: 500Hz
2: 1kHz
3: 2kHz
0
CLKOUTEN
RW
0x0
Low Speed Clock
Output Enable
Note: Used during clock test that can help meet Class B Safety
SOC.WWDTCTL
Register 8-45
. SOC.WWDTCTL (Windowed Watchdog Timer Control, SOC 0x42)
BIT
NAME
ACCESS
RESET
DESCRIPTION
7:3
KEY
R
0
Write KEY = 0x14 to
modify WWDT
registers. All other
values disallow writes
to WWDT registers
except WWDTRST
register which can be
written at anytime.
2:1
CLKDIV[1:0]
RW
0x0
WWDT Clock Divider
–
The WWDT Clock =
32kHz / CLKDIV
0: /2
1: /16
2: /128
3: /1024
0
EN
RW
0x0
WWDT Enable
Note: The WWDT runs off of a 32kHz clock that is independent of the 4MHz CLKREF that the MCU runs
off. When the WWDT is used, it can help meet Class B Safety requirements.
