Qorvo PAC25140, User Manual

Page: 58 / 77

PAC25140 Users Guide Preview
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Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
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SOC.VADCRESLO
Register 8-27
. SOC.VADCRESLO (Voltage ADC Result Low, SOC 0x24)
BIT NAME ACCESS RESET DESCRIPTION
7:0 VADCRES[7:0] RW 0
Voltage ADC Result
LSByte
SOC.IADCCTL
Register 8-28
. SOC.IADCCTL (Current ADC Control, SOC 0x25)
BIT NAME ACCESS RESET DESCRIPTION
7 IADCSTART R/W 0x0
Current ADC Start
Conversion
6 IADCBUSY R 0x0
Current ADC Busy
- This bit is set to 1
during conversion and
set to 0 when
complete.
5 RFU R 0 Reserved
4:3 IMUXSEL[1:0] R/W 0x0
0: Isense Diff Amp
Output
1: SCP DAC
2: OCC DAC
3: OCD DAC
2:0 DAGAIN[2:0] R/W 0x0
Differential
Amplifier Gain:
0: 1X
1: 2X
2: 4X
3: 8X
4: 16X
5: 32X
6: 64X
7: 128X
SOC.IADCRESHI
Register 8-29
. SOC.IADCRESHI (Current ADC Result High, SOC 0x26)
BIT NAME ACCESS RESET DESCRIPTION
7:0 IADCRES[15:8] RW 0
Current ADC Result
MSByte
SOC.IADCRESLO
Register 8-30
. SOC.IADCRESLO (Current ADC Result Low, SOC 0x27)
BIT NAME ACCESS RESET DESCRIPTION
7:0 IADCRES[7:0] RW 0
Current ADC Result
LSByte
SOC.SCPDAC
Register 8-31
. SOC.SCPDAC (SCP DAC, SOC 0x28)
BIT NAME ACCESS RESET DESCRIPTION
7:0 SCPDAC RW 0 SCP DAC Setting –