EN 237
3139 785 31681
9.
Circuit- and IC description
PIN CONFIGURATION
VDD 1.8 V
VDD 3.3 V
VSS 0 V
64
11
6
17
32
33
48
SACLK
VSA_OSC
XOUT
XIN
VDA18_OSC
DO[7]
49
GPIO[0]
GPIO[1]
ENSERI
AGC_TUN
AGC_IF
SCL_TUN
SDA_TUN
VDDI18
SCL
SDA
CLR#
SADDR[1]
SADDR[0]
TEST
UNCOR
PSYNC
DEN
OCLK
DO[0]
DO[1]
DO[2]
DO[3]
VDDE33
VDDI18
DO[4]
DO[5]
DO[6]
VD18_PLL_ADC
VSA_PLL_ADC
VDA18_PLL
VSA_ADC
VIP
VIM
VDA33_ADC
VD33_ADC
GPIO[2]
VDDE33
VDDI18
GPIO[3]
TRST
TMS
TDI
TCK
TDO
S_UNCOR
S_PSYNC
S_DEN
31
3
11
9
7
5
27
25
23
21
19
29
35
37
39
41
4
3
4
5
51
55
53
57
59
61
S_DO
S_OCLK
TDA10046A
TQFP 64
VDDE33
VDDI18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Figure 9-31