EN 234
3139 785 31681
9.
Circuit- and IC Description
PIN DESCRIPTION
Symbol
Pin
Number
Type
DESCRIPTION
CLR#
9
I
(5v tol)
The CLR# input is asynchronous and active low, and clears the
TDA10046A. When CLR# goes low, the circuit immediately enters its
RESET mode and normal operation will resume 11 XIN falling edges later
after CLR# returned high. The I2C register contents are all initialized to
their default values. The minimum width of CLR# at low level is 4 XIN
clock periods.
XIN
54
I
XTAL oscillator input pin. Typically a fundamental XTAL oscillator is
connected between the XIN and XOUT pins.
XOUT
55
O
XTAL oscillator output pin. Typically a fundamental XTAL oscillator is
connected between the XIN and XOUT pins.
SACLK
51
I/O
T
8mA
Sampling CLocK. This pin could also be used to provide the sampling
clock to an external ADC. This pin can be set to tri-state (default state at
reset).
AGC_TUN
1
I/O
OD
T
4mA
First delta/sigma encoded output signal for the Tuner AGC. This signal is
typically fed to the AGC Tuner amplifier through a single RC network. But
AGC_TUN can also be configured to output a delta/sigma signal, which
can be used to measure the level of a free running tuner RF AGC.
This output can be set to tri-state (default state at reset) or 3.3V push-pull
or open-drain output (if 5V level is required).
AGC_IF
2
O
OD
T
4mA
Second delta/sigma encoded output signal for the IF AGC. This signal is
typically fed to the AGC IF amplifier through a single RC network.
This output can be set to tri-state (default state at reset) or 3.3V push-pull
or open-drain output (if 5V level is required).
DO[7:0]
49,48,
46,44,
43,41,
39,38
I/O
T
4mA
Data Output Bus. These 8-bit parallel data are the outputs of the
TDA10046A after demodulation, de-interleaving, RS decoding and de-
scrambling (MPEG Transport Stream)
This output can be set to tri-state (default state at reset).
OCLK
37
I/O
T
4mA
Output CLock. OCLK is the output clock for the parallel DO[7:0] output
Bus. OCLK is internally generated depending on which interface is
selected.
This output can be set to tri-state (default state at reset).
DEN
36
I/O
T
4mA
Data ENable : this output signal is high when there is a valid data on the
output Bus DO[7:0].
This output can be set to tri-state (default state at reset).
PSYNC
35
I/O
T
4mA
Pulse SYNChro. This output signal goes high when the sync byte (47
16
)
is provided, then it goes low until the next sync byte. If the serial interface
is selected, then PSYNC is high only on the first bit of the sync byte (47
16
)
or during the 8 bit of the sync byte depending on I2C programming.
This output can be set to tri-state (default state at reset).
UNCOR
33
I/O
T
4mA
UNCORrectable packet. This output signal is high when the provided
MPEG-TS packet is uncorrectable (during the 188 bytes of the packet).
The uncorrectable packet is not affected by the Reed Solomon decoder,
but the MSB of the byte following the sync byte is forced «1 » for the
MPEG2 process: Error Flag Indicator (if RSI and IEI are set low in the I2C
table).
This output can be set to tri-state (default state at reset).
S_DO
32
I/O
Serial data output bus. These data is the output of the TDA10046A after
