EN 220
3139 785 31681
9.
Circuit- and IC Description
Signal name
Pin no.
I/O
Short description
VDDC
C7
1.5V Core supply voltage
VDDC
C8
1.5V Core supply voltage
VSS
C9
Ground
VSS
C10
Ground
VDDC
C11
1.5V Core supply voltage
VDDS
C12
3.3 V supply voltage
VSS
C13
Ground
SNDA
C14
I/O
Snert Data
SNRST
C15
In
Snert Reset
YB5
D1
Out
Luminance output 5
YB4
D2
Out
Luminance output 4
VDDC
D3
1.5V Core supply voltage
N.C.
D4
VSS
D13
Ground
SNCL
D14
In
Snert Clock
TCK
D15
In
Boundary scan test, Test clock
YB3
E1
Out
Luminance output 3
YB2
E2
Out
Luminance output 2
VSS
E3
Ground
VDDC
E13
1.5V Core supply voltage
TMS
E14
In
Boundary scan test, Test Mode Select
TDO
E15
Out
Boundary scan test, Test Data Out
TST2
F1
In
Test input 2
YB1
F2
Out
Luminance output 1
VSS
F3
Ground
VSS
F13
Ground
TRST
F14
In
Boundary scan test, Reset
TDI
F15
In
Boundary scan test, Test Data In
CLKASB
G1
Out
Clock ASB
YB0/Do9
G2
Out
Luminance output 0 / 656 Data output 9
VDDS
G3
3.3 V supply voltage
VDDS
G13
3.3 V supply voltage
A0IIC
G14
In
IIC address select
Reset
G15
In
Resets the 656-outputs and SDRAM Data I/Os to tri-
state and resets the (asynchronous) IIC transceiver. +
defauls. Reset is active low.
CLKASA
H1
In
Clock ASA
UVB8/Do8
H2
Out
UV output 8 / 656 Data output 8
TST3
H3
In
Test input 3
VDDC
H13
1.5V core supply voltage