Omron C200H-ASC11, Manual, Page: 117 / 301

108
Restrictions for CS1-series PCs
Section 6-6
6-6 Restrictions for CS1-series PCs
There are five methods that can be used to transfer data between the CPU
Unit and an ASCII Unit. Refer to
6-2 Selecting the Data Exchange Method for
details. When an ASCII Unit is used with a CS1-series PC, however, there are
addressing restrictions for some of these methods, as shown in the following
table.
The specific restrictions are as follows:
1,2,3... 1. Method 1: There are restrictions in the areas and words that can be ad-
dressed when using allocated words in memory to transfer data.
2. Method 2: There are restrictions in the areas and words that can be ad-
dressed when using PC WRITE@ or PC READ@ in the BASIC program
in the ASCII Unit to transfer data.
3. Method 4, 5: IOWR and IORD can be used to transfer data to any memory
area words in the CS1-series CPU Unit. Dummy addresses may have to
be used in PC QWRITE@ or PC QREAD@.
Method 1: PC WRITE or PC READ
Any words that can be addressed using the allocated words n+3 and n+4 can
be used for data transfer. Possible addresses are shown in the following table.
Note Other addresses cannot be accessed directly in CS1-series CPU Unit mem-
ory. Use methods 3 to 5 for other addresses.
Method CPU Unit ASCII Unit Area restrictions
1 MOV and other
instructions PC WRITE or
PC READ Yes
2 No programming
required PC WRITE@ or
PC READ@ Yes
3 MOV and other
instructions PC GET or PC
PUT None
4 IOWR (#00
@@
) or
IORD(#00
@@
)
PC EGET or
PC EPUT None
5 IOWR (#FD00) or
IORD(#FD00) PC QWRITE@ or
PC QREAD@ None, but dummy addresses
may need to be used for PC
QWRITE@ or PC QREAD@
Area CS1 address
(see note)
Designation method
Area (bits 12
to 15 in word
n+3, 1 BCD
digit)
First word address
(bits 00 to 15 in
word n+4,
4 BCD digits)
DM Area D00000 to D06655 0 0000 to 6655
CIO Area CIO 0000 to
CIO 0511
(except CIO 0281) 1 0000 to 0511
(except 0281)
Data Link Area (in
CIO Area) CIO 1000 to
CIO 1063 2 0000 to 0063
Holding Bit Area,
part 1 H000 to H099 3 0000 to 0099
Holding Bit Area,
part 2 H100
(except H 101) 4 0000
(except 0001)
H102 to H127 0002 to 0027
EM Area, bank 0 E0_00000 to
E0_06143 5 0000 to 6143
Timer Area T0000 to T0511 6 0000 to 0511