CHAPTER 9 WATCH TIMER FUNCTION
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User’s Manual U15109EJ3V0UD
(2) Watch timer high-speed clock select register (WTNHC)
This register selects the count clock of the watch timer.
The count clock is determined using WTNM7 bit of WTNM register in combination with WTNCS1 and WTNCS0
bits of the watch timer clock select register (WTNCS).
WTNHC is set using an 8-bit memory manipulation instruction.
RESET input clears WTNHC to 00H.
After reset: 00H
R/W
Address: FFFFF366H
7
6
5
4
3
2
1
0
WTNHC
0
0
0
0
0
0
0
WTNCS2
Remark
For the settings of WTNCS2, refer to
9.3 (3) Watch timer clock select register (WTNCS)
.
(3) Watch timer clock select register (WTNCS)
This register selects the count clock of the watch timer.
WTNCS is set using an 8-bit memory manipulation instruction.
RESET input clears WTNCS to 00H.
Caution
Do not change the contents of the WTNM, WTNHC, and WTNCS registers (interval time,
interrupt time for watch timer, count clock) during a watch timer operation.
After reset: 00H
R/W
Address: FFFFF364H
7
6
5
4
3
2
1
0
WTNCS
0
0
0
0
0
0
WTNCS1
WTNCS0
WTNCS2
WTNCS1
WTNCS0
WTNM7
Selection of count
clock
Main clock
frequency
0
0
0
0
f
XX
/2
7
4.194 MHz
0
0
0
1
f
XT
(subclock)
–
0
0
1
0
f
XX
/3
×
2
6
6.291 MHz
0
0
1
1
f
XX
/2
8
8.388 MHz
0
1
0
0
Setting prohibited
–
0
1
0
1
Setting prohibited
–
0
1
1
0
f
XX
/3
×
2
7
12.582 MHz
0
1
1
1
f
XX
/2
9
16.777 MHz
1
0
1
0
f
XX
/3
2
×
2
6
18.874 MHz
Other than above
Setting prohibited
–
Remark
WTNM7 is bit 7 of the WTNM register.
WTNCS2 is bit 0 of the WTNHC register.
