User’s Manual U15109EJ3V0UD
732
APPENDIX C REVISION HISTORY
The following table shows the revision history up to the previous editions. The “Applied to:” column indicates the
chapters of each edition in which the revision was applied.
(1/5)
Edition
Major Revision from Previous Edition
Applied to:
•
Deletion of indication “under development” for the following products (developed)
µ
PD703068YGJ-
×××
-UEN, 703069YGJ-
×××
-UEN
•
Addition of watch timer high-speed clock select register (WTNHC), IIC flag registers 0 and
1 (IICF0, IICF1)
Throughout
Change of minimum instruction execution time in
1.4.1 Features (V850/SC3)
CHAPTER 1
INTRODUCTION
Modification of description in
Table 2-1 Pin I/O Buffer Power Supplies
Modification of description in
Table 2-3 Pin Operation States in Various Operating
Modes
CHAPTER 2 PIN
FUNCTIONS
Modification of
3.4.8 Peripheral I/O registers
Addition of
Remarks
in
3.4.9 (2) System status register (SYS)
CHAPTER 3 CPU
FUNCTIONS
Change of frequency of the V850/SC3 in
4.1 (1) Main clock oscillator
Addition of
Note
and
Caution
in
4.3.1 (1) Processor clock control register (PCC)
Modification of description for setting DCLK1 and DCLK0 bits = 01B and addition to
Notes
in
4.3.1 (2) Power save control register (PSC)
Modification of description on operation status of A16 to A21 pins in
Table 4-1 Operating
Statuses in HALT Mode
Modification of description on operation of UART0 to UART3 in
Table 4-2 Operating
Statuses in IDLE Mode
Addition of description in
4.4.4 (1) Settings and operating states
Modification of description on operation status of UART0 to UART3 in
Table 4-3 Operating
Statuses in Software STOP Mode
Addition of
4.6 (1) When executing an instruction on internal ROM
Addition of
Caution
in
4.6 (2) When executing an instruction on external ROM
CHAPTER 4
CLOCK
GENERATION
FUNCTION
Modification of description in
Table 5-1 Pin I/O Buffer Power Supplies
Addition of
Caution
in
5.2.8 (1) Function of P9 pins
Addition and modification of description in
Table 5-16 Setting When Port Pin Is Used for
Alternate Function
Addition of
5.4 Operation of Port Function
CHAPTER 5 PORT
FUNCTIONS
Addition of
Note
and
Caution
in
6.2.2 (1) System control register (SYC) (V850/SC1,
V850/SC2)
CHAPTER 6 BUS
CONTROL
FUNCTION
Modification of description in
Figure 7-2 Acknowledging Non-Maskable Interrupt
Requests
Addition of
7.8.1 Interrupt request valid timing following EI instruction
3rd
Addition of
7.9 Bit Manipulation Instruction of Interrupt Control Register on DMA
Transfer
CHAPTER 7
INTERRUPT/EXCEP
TION PROCESSING
FUNCTION
