NEC V850/SC1 User Manual Download Page 536

Page: 536 / 739

CHAPTER 18 IEBus CONTROLLER (V850/SC2)

534

User’s Manual U15109EJ3V0UD

(8) IEBus unit status register (USR)

After reset: 00H

Address: FFFFF3EEH

<6>

<5>

<4>

<3>

<2>

USR

SLVRQ

ARBIT

ALLTRNS

ACK

LOCK

SLVRQ

Slave request flag

No request from master to slave

Request from master to slave

ARBIT

Arbitration result flag

Arbitration win

Arbitration loss

ALLTRNS

Broadcast communication flag

Individual communication status

Broadcast communication status

ACK

ACK transmission flag

NACK transmitted

ACK transmitted

LOCK

Lock status flag

Unit unlocked

Unit locked

(a) Slave request flag (SLVRQ)...Bit 6

This flag indicates whether there was a slave request from the master.

Set: When the IEBus unit has been sent a slave request (during individual communication

reception, when the received slave address and local UAR match; during broadcast reception,

when the higher 4 bits of the received slave address match, or the received slave address is

FFFH), the flag is set by hardware at the start of the acknowledge period for the slave address

field.

Reset: When the IEBUS unit is not sent a slave request, the flag is reset by hardware. The timing is

the same as for Set. However, if immediately following normal reception of a communication

(SLVRQ bit is set), the IEBus unit is sent a slave request and a parity error occurs in the slave

address field for that communication, the flag is not reset.

Summary of Contents for V850/SC1

Page 1: ...ook over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1st 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ...

Page 2: ...ct for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and meas...

Page 3: ...850 SC3 TM 32 Bit Single Chip Microcontrollers Hardware µ µ µ µPD703068Y µ µ µ µPD703069Y µ µ µ µPD703088Y µ µ µ µPD703089Y µ µ µ µPD70F3089Y Printed in Japan Document No U15109EJ3V0UD00 3rd edition Date Published June 2002 N CP K 2001 2002 ...

Page 4: ...2 User s Manual U15109EJ3V0UD MEMO ...

Page 5: ... behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 ...

Page 6: ...sing from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers mu...

Page 7: ... NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax 250 3...

Page 8: ... 132 Modification of description on operation status of UART0 to UART3 in Table 4 3 Operating Statuses in Software STOP Mode p 135 Addition of 4 6 1 When executing an instruction on internal ROM p 136 Addition of Caution in 4 6 2 When executing an instruction on external ROM p 138 Modification of description in Table 5 1 Pin I O Buffer Power Supplies p 166 Addition of Caution in 5 2 8 1 Function o...

Page 9: ...en communication reservation function is disabled IICRSVn of IICFn register 1 p 423 Change of description in 11 5 13 Cautions p 424 Change of description in 11 5 14 1 Master operations 1 p 425 Addition of 11 5 14 2 Master operations 2 p 426 Addition of description in Figure 11 39 Slave Operation Flowchart p 437 Addition to Cautions in 11 6 2 1 Asynchronous serial interface mode registers 0 to 3 AS...

Page 10: ... bits and modification of register format and bit description in 19 5 10 CAN global interrupt pending register CGINTP pp 594 595 Modification of description on manipulatable bits and modification of register format in 19 5 11 CANn interrupt pending register CnINTP p 596 Addition to Cautions in 19 5 12 CAN stop register CSTOP pp 597 598 Modification of description on manipulatable bits and modifica...

Page 11: ...age Status Registers 00 to 31 M_STAT00 to M_STAT31 p 670 Addition of Figure 19 44 Setting Receive Operation Using Reception Polling p 671 Addition of Figure 19 45 Setting of CAN Message Search Start Result Register CGMSS CGMSR p 674 Addition of description in Figure 19 49 CAN Stop Mode Setting p 674 Addition of description in Figure 19 50 Clearing CAN Stop Mode p 675 Modification of description in...

Page 12: ...l specifications Data types Register set Instruction format and instruction set Interrupts and exceptions Pipeline operation How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering logic circuits and microcontrollers To find out the details of a register whose name is known Refer to APPENDIX A REGISTER INDEX To understand t...

Page 13: ...igher addresses at the top and lower addresses at the bottom Note Footnote for items marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Number representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Prefixes indicating power of 2 address space memory capacity K kilo 2 10 1024 M mega 2 20 1024 2 G giga 2 30 1024 3 ...

Page 14: ...CA850 Ver 2 30 or Later C Compiler Package Assembly Language U14567E Operation U15024E C Language U15025E Project Manager U15026E CA850 Ver 2 40 or Later C Compiler Package Assembly Language U15027E ID850 Ver 2 40 Integrated Debugger Operation WindowsTM Based U15181E SM850 Ver 2 40 System Simulator Operation Windows Based U15182E SM850 Ver 2 00 or Later System Simulator External Part User Open Int...

Page 15: ... V850 SC3 49 1 4 2 Application fields V850 SC3 50 1 4 3 Ordering information V850 SC3 50 1 4 4 Pin configuration top view V850 SC3 51 1 4 5 Function blocks V850 SC3 53 CHAPTER 2 PIN FUNCTIONS 56 2 1 List of Pin Functions 56 2 2 Pin States 66 2 3 Description of Pin Functions 67 2 4 Pin I O Circuit Types I O Buffer Power Supply and Connection of Unused Pins 82 2 5 Pin I O Circuits 85 CHAPTER 3 CPU F...

Page 16: ...on 135 CHAPTER 5 PORT FUNCTIONS 138 5 1 Port Configuration 138 5 2 Port Pin Functions 140 5 2 1 Port 0 140 5 2 2 Port 1 144 5 2 3 Port 2 149 5 2 4 Port 3 153 5 2 5 Ports 4 and 5 157 5 2 6 Port 6 160 5 2 7 Ports 7 and 8 163 5 2 8 Port 9 165 5 2 9 Port 10 168 5 2 10 Port 11 171 5 2 11 Port 12 176 5 2 12 Port 13 180 5 2 13 Port 14 182 5 2 14 Port 15 185 5 2 15 Port 17 188 5 3 Setting When Port Pin Is...

Page 17: ... 10 1 Program space 216 6 10 2 Data space 216 CHAPTER 7 INTERRUPT EXCEPTION PROCESSING FUNCTION 217 7 1 Outline 217 7 1 1 Features 217 7 2 Non Maskable Interrupts 221 7 2 1 Operation 222 7 2 2 Restore 224 7 2 3 NP flag 225 7 2 4 Noise eliminator of NMI pin 225 7 2 5 Edge detection function of NMI pin 226 7 3 Maskable Interrupts 227 7 3 1 Operation 227 7 3 2 Restore 229 7 3 3 Priorities of maskable...

Page 18: ...TM0 TM1 TM7 to TM12 Operation 272 8 2 1 Operation as interval timer 272 8 2 2 PPG output operation 274 8 2 3 Pulse width measurement 276 8 2 4 Operation as external event counter 283 8 2 5 Operation as square wave output 285 8 2 6 Operation as one shot pulse output 286 8 2 7 Cautions 291 8 3 16 Bit Timer TM5 TM6 296 8 3 1 Functions 296 8 3 2 Configuration 297 8 3 3 Timer n control registers 298 8 ...

Page 19: ...5 CSI6 8 or 16 Bits 343 11 4 1 Features 343 11 4 2 Configuration 344 11 4 3 Control registers 346 11 4 4 Operation 354 11 4 5 Output pins 369 11 5 I 2 C Bus 370 11 5 1 Configuration 373 11 5 2 I 2 C control registers 375 11 5 3 I 2 C bus mode functions 388 11 5 4 I 2 C bus definitions and control methods 389 11 5 5 I 2 C interrupt requests INTIICn 396 11 5 6 Interrupt request INTIICn generation ti...

Page 20: ...ation 472 13 4 Control Registers 473 13 5 Operation 479 13 6 Cautions 480 CHAPTER 14 RESET FUNCTION 483 14 1 General 483 14 2 Pin Operations 484 14 3 Power on Clear Operation 486 CHAPTER 15 REGULATOR 488 15 1 Outline 488 15 2 Operation 488 CHAPTER 16 ROM CORRECTION FUNCTION 489 16 1 General 489 16 2 ROM Correction Peripheral I O Registers 490 16 2 1 Correction control register CORCN 490 16 2 2 Cor...

Page 21: ...cation mode 508 18 1 4 Communication address 508 18 1 5 Broadcast communication 509 18 1 6 Transfer format of IEBus 509 18 1 7 Transfer data 518 18 1 8 Bit format 521 18 2 IEBus Controller Configuration 522 18 3 Internal Registers of IEBus Controller 524 18 3 1 Internal register list 524 18 3 2 Internal registers 525 18 4 Interrupt Operations of IEBus Controller 544 18 4 1 Interrupt control block ...

Page 22: ...12 CAN stop register CSTOP 596 19 5 13 CAN global status register CGST 597 19 5 14 CAN global interrupt enable register CGIE 600 19 5 15 CAN main clock select register CGCS 601 19 5 16 CAN time stamp count register CGTSC 603 19 5 17 CAN message search start result register CGMSS CGMSR 604 19 5 18 CANn address mask a registers L and H CnMASKLa and CnMASKHa 606 19 5 19 CANn control register CnCTRL 6...

Page 23: ... 672 19 12 5 CAN stop mode 674 19 13 Rules for Correct Setting of Baud Rate 675 19 14 Ensuring Data Consistency 679 19 14 1 Sequential data read 679 19 14 2 Burst read mode 680 19 15 Interrupt Conditions 681 19 15 1 Interrupts that occur for FCAN controller 681 19 15 2 Interrupts that occur for global CAN interface 681 19 16 How to Shutdown FCAN Controller 682 19 17 Cautions on Use 682 CHAPTER 20 ...

Page 24: ... P07 143 5 2 Block Diagram of P10 and P12 146 5 3 Block Diagram of P11 P13 to P15 and P17 147 5 4 Block Diagram of P16 148 5 5 Block Diagram of P20 and P22 151 5 6 Block Diagram of P21 and P23 to P27 152 5 7 Block Diagram of P30 to P37 156 5 8 Block Diagram of P40 to P47 and P50 to P57 159 5 9 Block Diagram of P60 to P65 162 5 10 Block Diagram of P70 to P77 and P80 to P83 164 5 11 Block Diagram of...

Page 25: ... Process 231 7 8 Example of Servicing Interrupt Requests Simultaneously Generated 233 7 9 ID Flag 237 7 10 Software Exception Processing 241 7 11 RETI Instruction Processing 242 7 12 EP Flag EP 243 7 13 Illegal Op Code 244 7 14 Exception Trap Processing 244 7 15 RETI Instruction Processing 245 7 16 Pipeline Operation at Interrupt Request Acknowledgement 249 7 17 Pipeline Flow and Interrupt Request...

Page 26: ...s in External Event Counter Mode 283 8 19 Configuration of External Event Counter 284 8 20 Timing of External Event Counter Operation with Rising Edge Specified 284 8 21 Control Register Settings in Square Wave Output Mode 285 8 22 Timing of Square Wave Output Operation 286 8 23 Control Register Settings for One Shot Pulse Output via Software Trigger 287 8 24 Timing of One Shot Pulse Output Operat...

Page 27: ...Phase Selection 357 11 15 Timing Chart of Interrupt Request Signal Output in Delay Mode 359 11 16 Repeat Transfer Receive Only Timing Chart 362 11 17 Repeat Transfer Transmission Reception Timing Chart 364 11 18 Timing Chart of Next Transfer Reservation Period 365 11 19 Transfer Request Clear and Register Access Contention 367 11 20 Interrupt Request and Register Access Contention 368 11 21 Block ...

Page 28: ...nous Serial Interface 448 11 50 Timing of Asynchronous Serial Interface Transmission Completion Interrupt 450 11 51 Timing of Asynchronous Serial Interface Reception Completion Interrupt 451 11 52 Receive Error Timing 452 12 1 Block Diagram of A D Converter 455 12 2 Basic Operation of A D Converter 462 12 3 Relationship Between Analog Input Voltage and A D Conversion Result 463 12 4 A D Conversion...

Page 29: ...e for Manipulating Flash Memory 504 17 11 Flash Memory Programming Mode 504 17 12 Communication Command 505 18 1 IEBus Transfer Signal Format 509 18 2 Master Address Field 510 18 3 Slave Address Field 511 18 4 Control Field 513 18 5 Telegraph Length Field 515 18 6 Data Field 516 18 7 Bit Configuration of Slave Status 519 18 8 Configuration of Lock Address 520 18 9 Bit Format of IEBus 521 18 10 IEB...

Page 30: ...ample When PBB Bit 0 634 19 9 Message Processing Example When PBB Bit 1 634 19 10 Composition of Layers 638 19 11 Data Frame 639 19 12 Remote Frame 640 19 13 Start of Frame SOF 640 19 14 Arbitration Field During Standard Format Mode 641 19 15 Arbitration Field in Extended Format Mode 641 19 16 Control Field 642 19 17 Data Field 643 19 18 CRC Field 643 19 19 ACK Field 644 19 20 End of Frame EOF 644...

Page 31: ...of CAN Message Control Registers 00 to 31 M_CTRL00 to M_CTRL31 666 19 41 Setting of CAN Message Status Registers 00 to 31 M_STAT00 to M_STAT31 667 19 42 Transmit Setting 668 19 43 Setting of Receive Operation Using Reception Completion Interrupt 669 19 44 Setting Receive Operation Using Reception Polling 670 19 45 Setting of CAN Message Search Start Result Register CGMSS CGMSR 671 19 46 CAN Sleep ...

Page 32: ...Alternate Function Pins 144 5 4 Port 2 Alternate Function Pins 149 5 5 Port 3 Alternate Function Pins 153 5 6 Alternate Function Pins of Ports 4 and 5 157 5 7 Port 6 Alternate Function Pins 160 5 8 Alternate Function Pins of Ports 7 and 8 163 5 9 Port 9 Alternate Function Pins 165 5 10 Port 10 Alternate Function Pins 168 5 11 Port 11 Alternate Function Pins 171 5 12 Port 12 Alternate Function Pins...

Page 33: ...nterval Timer 317 10 3 Watchdog Timer Configuration 318 10 4 Loop Detection Time of Watchdog Timer 321 10 5 Interval Time of Interval Timer 322 11 1 Configuration of CSIn 325 11 2 Configuration of CSI4 331 11 3 CSIn Configuration 344 11 4 SCKn Pin Output Status 369 11 5 SOn Pin Output Status 369 11 6 Configuration of I 2 Cn 373 11 7 INTIICn Generation Timing and Wait Control 414 11 8 Extension Cod...

Page 34: ...ISR Register 536 18 9 Interrupt Source List 545 18 10 Communication Error Cause Processing List 546 19 1 Overview of Functions 559 19 2 Configuration of Messages and Buffers 562 19 3 Addresses of M_DLCn n 00 to 31 576 19 4 Addresses of M_CTRLn n 00 to 31 579 19 5 Addresses of M_TIMEn n 00 to 31 580 19 6 Addresses of M_DATAnx n 00 to 31 x 0 to 7 582 19 7 Addresses of M_IDLn and M_IDHn n 00 to 31 58...

Page 35: ...ons of Error Frame 647 19 23 Field Definition of Overload Frame 648 19 24 Determination of Bus Priority 649 19 25 Bit Stuffing 649 19 26 Types of Errors 650 19 27 Error Frame Output Timing 650 19 28 Types of Error Statuses 651 19 29 Error Counter 652 B 1 Symbols in Operand Description 725 B 2 Symbols Used for Op Code 726 B 3 Symbols Used for Operation Description 726 B 4 Symbols Used for Flag Oper...

Page 36: ... Area Network controller added to the peripheral functions In addition to high real time response characteristics and 1 clock pitch basic instructions the V850 SC1 V850 SC2 and V850 SC3 can realize multiply saturated operation and bit manipulation instructions by means of a hardware multiplier Table 1 1 shows the outline of the V850 SC1 V850 SC2 and V850 SC3 lineup Table 1 1 Product Lineup of V850...

Page 37: ... External expansion Expandable to 4 MB Memory block allocation function 2 MB per block Programmable wait function Idle state insertion function External bus interface 16 bit data bus address data multiplexed Address bus Separate output possible 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703068Y mask ROM 512 KB RAM 24 KB µPD70F3089Y flash memory 512 KB ...

Page 38: ...ection addresses specifiable Regulator 3 5 V to 5 5 V input internal 3 3 V Key return function 4 to 8 pins selectable falling edge fixed Clock generator During main clock or subclock operation 5 level CPU clock including sub operations Power save functions HALT IDLE STOP modes Package 144 pin plastic LQFP 20 20 mm CMOS structure All static circuits 1 2 2 Application fields V850 SC1 AV equipment su...

Page 39: ...TI5 TO5 P110 A1 WAIT P111 A2 P112 A3 P113 A4 P114 P115 P02 INTP1 P116 P117 PORTV DD1 P100 A5 KR0 TO7 P101 A6 KR1 TI70 P102 A7 KR2 TI00 P103 A8 KR3 TI01 P104 A9 KR4 TO0 P105 A10 KR5 TI10 P106 A11 KR6 TI11 P107 A12 KR7 TO1 P03 INTP2 XT2 XT1 GND2 ADCGND ADCV DD P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 P70 ANI0 P176 VM45 P175 P174 GND1 P173 P172 V DD1 P171 P170 P07 INTP6 P157 TI1...

Page 40: ... Serial input INTP0 to INTP9 Interrupt request from peripherals SO0 SO2 to SO6 Serial output KR0 to KR7 Key return TI00 TI01 TI10 LBEN Lower byte enable TI11 TI100 TI101 MODE Mode TI110 TI111 TI120 NMI Non maskable interrupt request TI121 TI5 TI6 TI70 PORTGND0 TI71 TI80 TI81 PORTGND1 Ground for ports TI90 TI91 Timer input PORTVDD0 to TO0 TO1 PORTVDD2 Power supply for ports TO5 to TO12 Timer output...

Page 41: ...101 TI110 TI111 TI120 TI121 TO0 TO1 TO7 to TO12 TI5 TO5 TI6 TO6 SO2 SI2 SDA1 SCK2 SCL1 SO3 TXD1 SI3 RXD1 SCK3 ASCK1 SO4 TXD0 SI4 RXD0 SCK4 ASCK0 SO5 SI5 SCK5 Key return function DMAC 6 ch Watch timer Watchdog timer KR0 to KR7 SO6 SI6 SCK6 TXD2 RXD2 ASCK2 UART3 TXD3 RXD3 ASCK3 ALU Ports Instruction queue BCU P170 to P176 P150 to P157 P140 to P147 P130 to P133 P120 to P127 P110 to P117 P100 to P107 ...

Page 42: ...e Interrupt controller INTC This controller handles hardware interrupt requests NMI INTP0 to INTP9 from on chip peripheral hardware and external hardware Eight levels of interrupt priorities can be specified for these interrupt requests and multiplexed servicing control can be performed for interrupt sources f Clock generator CG The clock generator includes two types of oscillators one for the mai...

Page 43: ...orated This controller transfers data between the internal RAM and on chip peripheral I O devices in response to interrupt requests sent by on chip peripheral I O m Ports As shown below the following ports have general purpose port functions and control pin functions Port I O Port Function Control Function Port 0 8 bit I O NMI external interrupt A D converter trigger Port 1 8 bit I O Serial interf...

Page 44: ...ata External expansion Expandable to 4 MB Memory block allocation function 2 MB per block Programmable wait function Idle state insertion function External bus interface 16 bit data bus address data multiplexed Address bus Separate output possible 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703069Y mask ROM 512 KB RAM 24 KB µPD70F3089Y flash memory 512 ...

Page 45: ...ection addresses specifiable Regulator 3 5 V to 5 5 V input internal 3 3 V Key return function 4 to 8 pins selectable falling edge fixed Clock generator During main clock or subclock operation 5 level CPU clock including sub operations Power save functions HALT IDLE STOP modes IEBus controller 1 channel Package 144 pin plastic LQFP 20 20 mm CMOS structure All static circuits 1 3 2 Application fiel...

Page 46: ...6 P17 TI5 TO5 P110 A1 WAIT P111 A2 P112 A3 P113 A4 P114 P115 P02 INTP1 P116 P117 PORTV DD1 P100 A5 KR0 TO7 P101 A6 KR1 TI70 P102 A7 KR2 TI00 P103 A8 KR3 TI01 P104 A9 KR4 TO0 P105 A10 KR5 TI10 P106 A11 KR6 TI11 P107 A12 KR7 TO1 P03 INTP2 XT2 XT1 GND2 ADCGND ADCV DD P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 P70 ANI0 P176 VM45 P175 P174 GND1 P173 P172 V DD1 P171 P170 P07 INTP6 P1...

Page 47: ...data SDA0 SDA1 Serial data IETX0 IEBus transmit data SI0 SI2 to SI6 Serial input INTP0 to INTP9 Interrupt request from peripherals SO0 SO2 to SO6 Serial output KR0 to KR7 Key return TI00 TI01 TI10 LBEN Lower byte enable TI11 TI100 TI101 MODE Mode TI110 TI111 TI120 NMI Non maskable interrupt request TI121 TI5 TI6 TI70 PORTGND0 TI71 TI80 TI81 PORTGND1 Ground for ports TI90 TI91 Timer input PORTVDD0 ...

Page 48: ... TI121 TO0 TO1 TO7 to TO12 TI5 TO5 TI6 TO6 SO2 SI2 SDA1 SCK2 SCL1 SO3 TXD1 SI3 RXD1 SCK3 ASCK1 SO4 TXD0 SI4 RXD0 SCK4 ASCK0 SO5 SI5 SCK5 Key return function DMAC 6 ch Watch timer Watchdog timer IEBus KR0 to KR7 SO6 SI6 SCK6 TXD2 RXD2 ASCK2 UART3 TXD3 RXD3 ASCK3 IETX0 IERX0 ALU Ports Instruction queue BCU P170 to P176 P150 to P157 P140 to P147 P130 to P133 P120 to P127 P110 to P117 P100 to P107 P90...

Page 49: ...e Interrupt controller INTC This controller handles hardware interrupt requests NMI INTP0 to INTP9 from on chip peripheral hardware and external hardware Eight levels of interrupt priorities can be specified for these interrupt requests and multiplexed servicing control can be performed for interrupt sources f Clock generator CG The clock generator includes two types of oscillators one for the mai...

Page 50: ...O devices in response to interrupt requests sent by on chip peripheral I O m Ports As shown below the following ports have general purpose port functions and control pin functions Port I O Port Function Control Function Port 0 8 bit I O NMI external interrupt A D converter trigger Port 1 8 bit I O Serial interface timer I O Port 2 8 bit I O Serial interface timer I O IEBus data I O Port 3 8 bit I ...

Page 51: ...nal expansion Expandable to 4 MB Memory block allocation function 2 MB per block Programmable wait function Idle state insertion function External bus interface 16 bit data bus address data multiplexed 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703088Y 703089Y mask ROM 512 KB RAM 24 KB µPD70F3089Y flash memory 512 KB RAM 24 KB Interrupts and exceptions...

Page 52: ... V input internal 3 3 V Key return function 4 to 8 pins selectable falling edge fixed Clock generator During main clock or subclock operation 5 level CPU clock including sub operations Power save functions HALT IDLE STOP modes FCAN controller 2 channels µPD703089Y 70F3089Y 1 channel µPD703088Y Package 144 pin plastic LQFP 20 20 mm CMOS structure All static circuits 1 4 2 Application fields V850 SC...

Page 53: ...TX1 P115 CANRX1 P02 INTP1 P116 CANTX2 Note 2 P117 CANRX2 Note 2 PORTV DD1 P100 A5 KR0 TO7 P101 A6 KR1 TI70 P102 A7 KR2 TI00 P103 A8 KR3 TI01 P104 A9 KR4 TO0 P105 A10 KR5 TI10 P106 A11 KR6 TI11 P107 A12 KR7 TO1 P03 INTP2 XT2 XT1 GND2 ADCGND ADCV DD P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 P70 ANI0 P176 VM45 P175 P174 GND1 P173 P172 V DD1 P171 P170 P07 INTP6 P157 TI121 P156 TI1...

Page 54: ...0 to GND2 Ground SCK6 Serial clock HLDAK Hold acknowledge SCL0 SCL1 Serial clock HLDRQ Hold request SDA0 SDA1 Serial data INTP0 to INTP9 Interrupt request from peripherals SI0 SI2 to SI6 Serial input KR0 to KR7 Key return SO0 SO2 to SO6 Serial output LBEN Lower byte enable TI00 TI01 TI10 MODE Mode TI11 TI100 TI101 NMI Non maskable interrupt request TI110 TI111 TI120 PORTGND0 TI121 TI5 TI6 TI70 POR...

Page 55: ...O3 TXD1 SI3 RXD1 SCK3 ASCK1 SO4 TXD0 SI4 RXD0 SCK4 ASCK0 SO5 SI5 SCK5 Key return function DMAC 6 ch Watch timer Watchdog timer KR0 to KR7 SO6 SI6 SCK6 TXD2 RXD2 ASCK2 UART3 TXD3 RXD3 ASCK3 FCAN CANTX1 CANRX1 CANTX2Note 1 CANRX2Note 1 ALU Ports Instruction queue BCU P170 to P176 P150 to P157 P140 to P147 P130 to P133 P120 to P127 P110 to P117 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65...

Page 56: ...e Interrupt controller INTC This controller handles hardware interrupt requests NMI INTP0 to INTP9 from on chip peripheral hardware and external hardware Eight levels of interrupt priorities can be specified for these interrupt requests and multiplexed servicing control can be performed for interrupt sources f Clock generator CG The clock generator includes two types of oscillators one for the mai...

Page 57: ...ip peripheral I O m Ports As shown below the following ports have general purpose port functions and control pin functions Port I O Port Function Control Function Port 0 8 bit I O NMI external interrupt A D converter trigger Port 1 8 bit I O Serial interface timer I O Port 2 8 bit I O Serial interface timer I O Port 3 8 bit I O Timer I O external address bus external interrupt Port 4 8 bit I O Por...

Page 58: ... P03 P10 to P17 P30 to P37 P100 to P107 P110 to P117 3 0 V PORTVDD1 5 5 VNote 2 PORTVDD2 Note 1 P04 to P07 P20 to P27 P120 to P127 P130 to P133 P140 to P147 P150 to P157 3 0 V PORTVDD2 5 5 VNote 2 VDD0 RESET When A D converter not used 4 0 V VDD0 5 5 V When A D converter used 4 5 V VDD0 ADCVDD 5 5 V VDD1 P170 to P176 4 0 V VDD1 5 5 V ADCVDD P70 to P77 P80 to P83 When A D converter not used 4 0 V A...

Page 59: ...5 5 V Notes 1 The electrical specifications differ between an operating frequency of 4 to 17 MHz and an operating frequency of 4 to 20 MHz 2 When the FCAN controller is used PORTVDD1 PORTVDD2 Due to the supply voltage conditions of the in circuit emulator Caution The conditions for the power supplies are as follows PORTVDD0 PORTVDD1 PORTVDD2 VDD0 VDD1 ADCVDD The differences in the pins of the V850...

Page 60: ...n be specified in 1 bit units Only P10 and P12 can be specified as N ch open drain pins TI5 TO5 P20 SI2 SDA1 P21 SO2 P22 SCK2 SCL1 P23 TI90 P24 TI91 P25 TO9 P26 IERX0Note 1 P27 I O No Port 2 8 bit I O port Input output can be specified in 1 bit units Only P20 and P22 can be specified as N ch open drain pins IETX0Note 1 P30 TI6 TO6 P31 TI80 P32 TI81 P33 TO8 P34 TI71 A13Note 2 P35 INTP7 A14Note 2 P3...

Page 61: ...52 AD10 P53 AD11 P54 AD12 P55 AD13 P56 AD14 P57 I O No Port 5 8 bit I O port Input output can be specified in 1 bit units AD15 P60 A16 P61 A17 P62 A18 P63 A19 P64 A20 P65 I O No Port 6 6 bit I O port Input output can be specified in 1 bit units A21 P70 ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P75 ANI5 P76 ANI6 P77 Input No Port 7 8 bit input port ANI7 P80 ANI8 P81 ANI9 P82 ANI10 P83 Input No Port ...

Page 62: ... O port Input output can be specified in 1 bit units KR7 TO1 A12Note 1 P110 WAIT A1Note 1 P111 A2Note 1 P112 A3Note 1 P113 A4Note 1 P114 CANTX1Note 2 P115 CANRX1Note 2 P116 CANTX2Note 3 P117 I O No Port 11 8 bit I O port Input output can be specified in 1 bit units CANRX2Note 3 P120 SCK5 P121 SI5 P122 SO5 P123 SCK6 P124 SI6 P125 SO6 P126 TO10 P127 I O No Port 12 8 bit I O port Input output can be ...

Page 63: ...7 I O No Port 14 8 bit I O port Input output can be specified in 1 bit units TI101 P150 RXD3 P151 TXD3 P152 ASCK3 P153 TI110 P154 TI111 P155 TO12 P156 TI120 P157 I O Yes Port 15 8 bit I O port Input output can be specified in 1 bit units TI121 P170 P171 P172 P173 P174 P175 P176 I O No Port 17 7 bit I O port Input output can be specified in 1 bit units VM45 Remark PULL On chip pull up resistor ...

Page 64: ... D converter ADTRG Input No A D converter external trigger input P05 INTP4 ANI0 to ANI11 Input No Analog input to A D converter P70 to P77 P80 to P83 ASCK0 Baud rate clock input for UART0 P15 SCK4 ASCK1 Baud rate clock input for UART1 P142 SCK3 ASCK2 Baud rate clock input for UART2 P145 ASCK3 Input No Baud rate clock input for UART3 P152 ASTB Output No External address strobe signal output P94 CAN...

Page 65: ...te 1 T01 LBEN Output No External data bus s lower byte enable signal output P90 WRLNote 1 MODE Specifies operation mode other than µPD78F38089Y VPP Note 2 NMI Input No Non maskable interrupt request input analog noise elimination P00 PORTGND0 PORTGND1 Ground potential for ports PORTVDD0 Positive power supply for ports P40 to P47 P50 to P57 P60 to P65 P90 to P96 CLKOUT PORTVDD1 Positive power suppl...

Page 66: ...mit data output 3 wire type for variable length CSI4 P14 TXD0 SO5 No P122 SO6 Output No Serial transmit data output 3 wire type for CSI5 CSI6 P125 TI00 External count clock input for TM0 external capture trigger input for TM0 P102 A7Note KR2 TI01 External capture trigger input for TM0 P103 A8Note KR3 TI10 External count clock input for TM1 external capture trigger input for TM1 P105 A10Note KR5 TI...

Page 67: ...9 Output No Pulse signal output for TM6 to TM9 P25 TXD0 P14 SO4 TXD1 P141 SO3 TXD2 P144 TXD3 Output No Serial transmit data output for UART0 UART1 UART2 UART3 P151 UBEN Output No Higher byte enable signal output for external data bus P91 VDD0 Positive power supply pin RESET VDD1 Positive power supply pin P170 to P176 VM45 Output No VDD0 4 5 V monitor output P176 VPP High voltage application pin fo...

Page 68: ...ingNote 4 OperatingNote 4 Notes 1 Pins except the CLKOUT pin are used as port pins input mode after reset 2 The bus cycle inactivation timing occurs when the internal memory area is specified by the program counter PC in the external expansion mode 3 When the external memory area has not been accessed even once after reset is released and the external expansion mode is set Undefined When the bus c...

Page 69: ...D converter The pin s valid edge is specified by the EGP0 and EGN0 registers a Port function P00 to P07 can be set to input or output in 1 bit units using the port 0 mode register PM0 b Alternate functions i NMI non maskable interrupt request Input This is a non maskable interrupt request signal input pin ii INTP0 to INTP6 interrupt request from peripherals Input These are external interrupt reque...

Page 70: ...0 and CSI4 ii SO0 SO4 serial output 0 4 Output These are the serial transmit data output pins for CSI0 and CSI4 iii SCK0 SCK4 serial clock 0 4 3 state I O These are the serial clock I O pins for CSI0 and CSI4 iv SDA0 serial data 0 I O This is the serial transmit receive data I O pin for I 2 C0 v SCL0 serial clock 0 I O This is the serial clock I O pin for I 2 C0 vi RXD0 receive data 0 Input This i...

Page 71: ...t data output pin for CSI2 iii SCK2 serial clock 2 3 state I O This is the serial clock I O pin for CSI2 iv SDA1 serial data 1 Input This is the serial transmit receive data I O pin for I 2 C1 v SCL1 serial clock 1 I O This is the serial clock I O pin for I 2 C1 vi TI90 timer input 90 Input This is the external count clock input and external capture trigger input pin for timer 9 vii TI91 timer inp...

Page 72: ...pin for timer 7 iii TI80 timer input 80 Input This is the external count clock input and external capture trigger input pin for timer 8 iv TI81 timer input 81 Input This is the external capture trigger input pin for timer 8 v TO6 TO8 timer output 6 8 Output These are the pulse signal output pins for timer 6 and timer 8 vi A13 to A15 address 13 to 15 Output These pins comprise an address bus for ex...

Page 73: ...clock in each state in the bus cycle When the timing sets the bus cycle to inactive these pins go into a high impedance state 6 P50 to P57 port 5 3 state I O P50 toP57 function as an 8 bit I O port in which input and output can be specified in 1 bit units In addition to I O port pins these pins can also be used as a time division address data bus AD8 to AD15 when memory is expanded externally a Po...

Page 74: ...cycle to inactive these pins hold the address of the bus cycle immediately before 8 P70 to P77 port 7 P80 to P83 port 8 Input P70 to P77 function as an 8 bit input only port in which all pins are fixed as input pins P80 to P83 function as a 4 bit input only port in which all pins are fixed as input pins In addition to input ports these pins can also be used as analog input pins of the A D converte...

Page 75: ...bered addresses these pins are set to inactive high level The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle When the timing sets the bus cycle to inactive this pin holds the address of the bus cycle immediately before Access UBEN LBEN AD0 Word access 0 0 0 Halfword access 0 0 0 Even numbered address 1 0 0 Byte access Odd numbered address 0 1 1...

Page 76: ... impedance This occurs either when the V850 SC1 V850 SC2 and V850 SC3 complete execution of the current bus cycle or immediately if no bus cycle is being executed The HLDAK signal is then set to active and the bus is released viii WRL write strobe low level data Output This is the write strobe signal output pin for the lower data of the external 16 bit data bus This is output in the same write cyc...

Page 77: ...e key return mode register KRM ii TI00 TI10 TI70 timer input 00 10 70 Input These are external count clock input and external capture trigger input pins for timers 0 1 and 7 iii TI01 TI11 timer input 01 11 Input These are external capture trigger input pins for timers 0 and 1 iv TO0 TO1 TO7 timer output 0 1 7 Output These are pulse signal output pins for timers 0 1 and 7 v A5 to A12 address 5 to 1...

Page 78: ... of the bus cycle ON OFF switching of the wait function is performed by the port alternate function control register PAC ii CANRX1 CANRX2 CAN receive data 1 2 Input These are data input signals for CAN1 and CAN2 CANRX1 is available only for the V850 SC3 CANRX2 is available only for the µPD703089Y and 70F3089Y iii CANTX1 CANTX2 CAN transmit data 1 2 Output These are data output signals for CAN1 and...

Page 79: ...mode register PM12 b Alternate functions i SI5 SI6 serial input 5 6 Input These are the serial receive data input pins for CSI5 and CSI6 ii SO5 SO6 serial output 5 6 Output These are the serial transmit data output pins for CSI5 and CSI6 iii SCK5 SCK6 serial clock 5 6 3 state I O These are the serial clock I O pins for CSI5 and CSI6 iv TO10 TO11 timer output 10 11 Output These are the pulse signal...

Page 80: ...is the serial receive data input pin for CSI3 ii SO3 serial output 3 Output This is the serial transmit data output pin for CSI3 iii SCK3 serial clock 3 3 state I O This is the serial clock I O pin for CSI3 iv RXD1 receive data 1 Input This is the serial receive data input pin for UART1 v TXD1 transmit data 1 Output This is the serial transmit data output pin for UART1 vi ASCK1 asynchronous serial...

Page 81: ...t pin for UART3 ii TXD3 transmit data 3 Output This is the serial transmit data output pin for UART3 iii ASCK3 asynchronous serial clock 3 Input This is the serial baud rate clock input pin for UART3 iv TI110 timer input 110 Input This is the external count clock input and external capture trigger input pin for timer 11 v TI111 timer input 111 Input This is the external capture trigger input pin f...

Page 82: ...first priority ahead of all other operations In addition to being used for ordinary initialization start operations this signal can also be used to cancel a standby mode HALT IDLE or STOP mode 18 Mode mode This is pin used in other than the µPD78F3089 Connect to GND0 to GND2 in normal operating mode 19 CLKOUT clock output Output This pin outputs internally generated bus clocks 20 X1 X2 crystal The...

Page 83: ...xcept for the alternate function ports of the bus interface 27 VDD0 VDD1 power supply These are positive power supply pins VDD0 and VDD1 pins should be connected to a positive power source 28 GND0 to GND2 ground These are ground pins All the GND0 to GND2 pins should be grounded 29 VPP programming power supply This is the positive power supply pin used for flash memory programming mode This pin is ...

Page 84: ...16 5 P17 TI5 TO5 8 PORTVDD1 Input Independently connect to PORTVDD1 PORTGND0 or PORTGND1 via a resistor Output Leave open P20 SI2 SDA1 10 P21 SO2 5 P22 SCK2 SCL1 10 P23 P24 TI90 TI91 8 P25 TO9 5 P26 IERX0Note 1 8 P27 IETX0Note 1 5 PORTVDD2 Input Independently connect to PORTVDD2 PORTGND0 or PORTGND1 via a resistor Output Leave open P30 TI6 TO6 P31 P32 TI80 TI81 8 P33 TO8 5 P34 TI71 A13Note 2 P35 P...

Page 85: ...12Note 1 8 A PORTVDD1 Input Independently connect to PORTVDD1 PORTGND0 or PORTGND1 via a resistor When connecting to PORTGND0 or PORTGND1 disconnect on chip pull up resistors by software Output Leave open P110 WAIT A1Note 1 P111 to P113 A2 to A4Note 1 P114 CANTX1Note 2 5 P115 CANRX1Note 2 8 P116 CANTX2Note 3 5 P117 CANRX2Note 3 8 PORTVDD1 Input Independently connect to PORTVDD1 PORTGND0 or PORTGND...

Page 86: ...CK3 P153 P154 TI110 TI111 8 P155 TO12 5 P156 P157 TI120 TI121 8 PORVDD2 Input Independently connect to PORTVDD2 PORTGND0 or PORTGND1 via a resistor Output Leave open P170 to P175 P176 VM45 5 VDD1 Input Independently connect to VDD1 PORTGND0 or PORTGND1 via a resistor Output Leave open CLKOUT 4 PORTVDD0 Leave open RESET 2 VDD0 X1 X2 XT1 XT2 CPUREG CPUREG VPP Note 1 MODE VDD0 Connect to either GND0 ...

Page 87: ...sable N ch P ch P ch VDD VDD Type 4 OUT Output disable N ch Data P ch VDD Push pull output that can be set for high impedance output both P ch and N ch off Type 9 N ch P ch Input enable VREF threshold voltage Comparator Type 5 Output disable Input enable IN OUT Data N ch P ch VDD Type 10 IN OUT Data Open drain Output disable N ch P ch VDD Type 8 IN OUT Data Output disable N ch P ch VDD ...

Page 88: ...0 SC1 50 ns 20 MHz internal operation V850 SC2 53 ns 18 87 MHz internal operation V850 SC3 62 5 ns 16 MHz internal operation Address space 16 MB linear General purpose registers 32 bits 32 Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions One clock 32 bit shift instruction Load store instructions with long short format Fo...

Page 89: ...ser s Manual Figure 3 1 CPU Register Set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero register Reserved for address register Stack pointer SP Global pointer GP Text pointer TP Element pointer EP Link pointer LP PC Program counter PSW Program status word ECR Exception cause register FEPC FEPSW Fatal error PC Fatal error P...

Page 90: ... Operation r0 Zero register Always holds 0 r1 Assembler reserved register Working register for generating 32 bit immediate r2 Address data variable register when r2 is not used by the real time OS being used r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text a...

Page 91: ...n maskable interrupt or NMI occurs this register will hold the information referencing the interrupt source The higher 16 bits of this register are called FECC to which the exception code of the NMI is set The lower 16 bits are called EICC to which the exception code of the exception interrupt is set 5 PSW Program status word The program status word is a collection of flags that indicate the progr...

Page 92: ...7 4 3 EP flag ID Maskable interrupt servicing specification 0 Maskable interrupt acknowledgement enabled 1 Maskable interrupt acknowledgement disabled This flag is set 1 when a maskable interrupt request is acknowledged For details refer to 7 3 6 ID flag SATNote Saturation detection of operation result of saturation operation instruction 0 Not saturated This flag is not cleared 0 if the result of ...

Page 93: ...of the OV and S bits in the saturation operation Simply setting 1 the OV bit will set 1 the SAT bit in a saturation operation Flag status Status of operation result SAT OV S Saturation processed operation result Maximum positive value exceeded 1 1 0 7FFFFFFFH Maximum negative value exceeded 1 1 1 80000000H Positive not exceeding the maximum 0 Negative not exceeding the maximum Retains the value be...

Page 94: ...of the internal ROM and the instruction processing written in the internal ROM is started External expansion mode can be entered by setting the memory expansion mode register MM via an instruction enabling an external device to be connected to the external memory area 2 Flash memory programming mode This mode is provided only in the µPD70F3089Y The internal flash memory can be programmed or erased...

Page 95: ...d supports up to 4 GB of linear address space data space during operand addressing data access When referencing instruction addresses a linear address space program space of up to 16 MB is supported The CPU address space is shown below Figure 3 2 CPU Address Space FFFFFFFFH CPU address space Program area 16 MB linear Data area 4 GB linear 01000000H 00FFFFFFH 00000000H ...

Page 96: ...its of a 32 bit CPU address are ignored and the CPU address is only seen as a 24 bit external physical address the physical location xx000000H is equally referenced by multiple address values 00000000H 01000000H 02000000H FE000000H FF000000H Figure 3 3 Address Space Imaging FFFFFFFFH FF000000H FEFFFFFFH Image CPU address space Image Image Image Image FE000000H FDFFFFFFH 02000000H 01FFFFFFH 0100000...

Page 97: ...es Caution No instruction can be fetched from the 4 KB area of 00FFF000H to 00FFFFFFH because this area is defined as peripheral I O area Therefore do not execute any branch operation instructions in which the destination address will reside in any part of this area Figure 3 4 Program Space 00FFFFFEH 00FFFFFFH 00000000H 00000001H Program space Program space direction direction 2 Data space The res...

Page 98: ...FFFH On chip peripheral I O area Internal RAM area FCAN address area Internal flash memory ROM area On chip peripheral I O area Internal RAM area FCAN address area External memory area Internal flash memory ROM area Single chip mode Single chip mode external expansion mode 16 MB 1 MB 4 KB xxFFF000H xxFFEFFFH xx100000H xx0FFFFFH xx000000H xxFF8000H xxFF7FFFH 28 KB ...

Page 99: ...rved for the internal ROM flash memory area 512 KB are available for the addresses xx000000H to xx07FFFFH Addresses xx080000H to xx0FFFFFH are an access prohibited area Figure 3 7 Internal ROM Flash Memory Area x x 0 F F F F F H x x 0 8 0 0 0 0 H x x 0 7 F F F F H x x 0 0 0 0 0 0 H Access prohibited area Internal ROM flash memory ...

Page 100: ... 00000280H INTTM80 000000A0H INTP1 00000290H INTTM81 000000B0H INTP2 000002A0H INTTM90 000000C0H INTP3 000002B0H INTTM91 000000D0H INTP4 000002C0H INTSR1 INTCSI3 000000E0H INTP5 000002D0H INTST1 000000F0H INTP6 000002E0H INTDMA3 00000100H INTCSI5 000002F0H INTDMA4 00000110H INTAD 00000300H INTDMA5 00000120H INTDMA0 00000310H INTCE2Note 4 00000130H INTDMA1 00000320H INTCR2Note 4 00000140H INTDMA2 0...

Page 101: ...m is reserved for the internal RAM area 24 KB are available for the addresses xxFF9000H to xxFFEFFFH Addresses xxFF8000H to xxFF8FFFH are an access prohibited area Figure 3 8 Internal RAM Area x x F F E F F F H x x F F 9 0 0 0 H x x F F 8 F F F H x x F F 8 0 0 0 H Access prohibited area Internal RAM ...

Page 102: ...s 2n 1 in the peripheral I O area is referenced accessed in byte units the register at the next lowest even address 2n will be accessed 2 If a register that can be accessed in byte units is accessed in halfword units the higher 8 bits become undefined if the access is a read operation If a write access is made only the data in the lower 8 bits is written to the register 3 If a register with addres...

Page 103: ...In other than the physical external memory area images of the physical external memory can be seen The internal RAM area and on chip peripheral I O area are not subject to external memory access Caution Addresses xxnFF800H to xxnFFFFFH n 3 7 B constitute an access prohibited area because this is an FCAN address area Figure 3 10 External Memory Area When Expanded to 64 KB 256 KB or 1 MB xxFFFFFFH x...

Page 104: ... When Expanded to 4 MB xxFFFFFFH xx000000H Physical external memory FCAN address area External memory 3FFFFFH 3FF800H 3FF7FFH 000000H On chip peripheral I O Internal RAM Image Image xxFF7FFFH xxC00000H xxBFFFFFH xx800000H xx7FFFFFH xx400000H xx3FFFFFH xx100000H xx0FFFFFH Internal ROM Image ...

Page 105: ... Manual of the relevant in circuit emulator about debugging when using the separate bus Caution Because the A1 pin and WAIT pin are alternate function pins for the V850 SC1 and V850 SC2 the WAIT pin based wait function cannot be used when using a separate bus programmable wait can be used however Similarly a separate bus cannot be used when the WAIT pin based wait function is being used Because th...

Page 106: ...8 or 1 bit units However bits 4 to 7 are fixed to 0 After reset 00H R W Address FFFFF04CH Symbol 7 6 5 4 3 2 1 0 MM 0 0 0 0 MM3 MM2 MM1 MM0 MM3 P95 and P96 operating modes 0 Port mode 1 External expansion mode HLDAK P95 HLDRQ P96 MM2 MM1 MM0 Address space Port 4 Port 5 Port 6 Port 9 0 0 0 Port mode 0 1 1 64 KB expansion mode 1 0 0 256 KB expansion mode 1 0 1 1 MB expansion mode 1 1 4 MB expansion ...

Page 107: ...mode register MAM cannot be debugged by an in circuit emulator Also switching to a separate bus is not possible by setting the MAM register using software For details refer to the User s Manual of the relevant in circuit emulator Remark For details of the operation of each port see 2 3 Description of Pin Functions P34 to P36 P100 to P107 and P110 to P113 are used for separate bus output The proced...

Page 108: ...ly the lower 24 bits are valid Therefore a continuous 16 MB space starting from address 00000000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources utilizing the wrap around feature of the data space the continuous 8 MB address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4 GB CPU are used as the data space With th...

Page 109: ...OM xxFFFFFFH xxFFF400H xxFFF3FFH xxFFF000H xxFFEFFFH xxFF9000H xxFF8FFFH xxFF8000H xxFF7FFFH xx100000H xx0FFFFFH xx080000H xx07FFFFH xx800000H xx7FFFFFH xx000000H FFFFF000H FFFFEFFFH FFFF8000H FFFF7FFFH FF800000H FF7FFFFFH 01000000H 00FFFFFFH 00FFF000H 00FFEFFFH 00FF8000H 00FF7FFFH 00800000H 007FFFFFH 00100000H 000FFFFFH 00080000H 0007FFFFH Note 2 Notes 1 This area cannot be used as a program area...

Page 110: ...r PM1 FFH FFFFF024H Port 2 mode register PM2 FFFFF026H Port 3 mode register PM3 FFFFF028H Port 4 mode register PM4 FFFFF02AH Port 5 mode register PM5 FFH FFFFF02CH Port 6 mode register PM6 3FH FFFFF032H Port 9 mode register PM9 7FH FFFFF034H Port 10 mode register PM10 FFH FFFFF036H Port 11 mode register PM11 FFFFF038H Port 12 mode register PM12 FFH FFFFF03AH Port 13 mode register PM13 0FH FFFFF03C...

Page 111: ...W 00H FFFFF0D0H 16 bit timer register 10 TM10 R FFFFF0D2H 16 bit capture compare register 100 CR100 Note 3 FFFFF0D4H 16 bit capture compare register 101 CR101 0000H FFFFF0D6H Prescaler mode register 100 PRM100 R W FFFFF0D8H 16 bit timer mode control register 10 TMC10 FFFFF0DAH Capture compare control register 10 CRC10 FFFFF0DCH Timer output control register 10 TOC10 FFFFF0DEH Prescaler mode regist...

Page 112: ...upt control register DMAIC0 FFFFF116H Interrupt control register DMAIC1 FFFFF118H Interrupt control register DMAIC2 FFFFF11AH Interrupt control register TMIC00 FFFFF11CH Interrupt control register TMIC01 FFFFF11EH Interrupt control register TMIC10 FFFFF120H Interrupt control register TMIC11 FFFFF122H Interrupt control register TMIC70 FFFFF124H Interrupt control register TMIC71 FFFFF126H Interrupt ...

Page 113: ...0H Interrupt control register STIC3 FFFFF162H Interrupt control register TMIC100 FFFFF164H Interrupt control register TMIC101 R W 47H FFFFF166H In service priority register ISPR R 00H FFFFF168H Interrupt control register TMIC110 FFFFF16AH Interrupt control register TMIC111 FFFFF16CH Interrupt control register TMIC120 FFFFF16EH Interrupt control register TMCI121 R W 47H FFFFF170H Command register P...

Page 114: ...compare register 00 CR00 FFFFF204H 16 bit capture compare register 01 CR01 Note 0000H FFFFF206H Prescaler mode register 00 PRM00 FFFFF208H 16 bit timer mode control register 0 TMC0 FFFFF20AH Capture compare control register 0 CRC0 FFFFF20CH Timer output control register 0 TOC0 FFFFF20EH Prescaler mode register 01 PRM01 R W 00H FFFFF210H 16 bit timer register 1 TM1 R FFFFF212H 16 bit capture compar...

Page 115: ...gister L5 SOTBFL5 R W 00H FFFFF254H Serial I O shift register 5 SIO5 0000H FFFFF256H Serial I O shift register L5 SIOL5 R 00H FFFFF260H Clocked serial interface mode register 6 CSIM6 0000H FFFFF262H Clocked serial interface clock select register 6 CSICK6 R W 00H FFFFF264H Clocked serial interface receive buffer register 6 SIRB6 0000H FFFFF266H Clocked serial interface receive buffer register L6 SI...

Page 116: ...FFFFF2C4H Serial clock select register 2 CSIS2 FFFFF2D0H Serial I O shift register 3 SIO3 FFFFF2D2H Serial operation mode register 3 CSIM3 FFFFF2D4H Serial clock select register 3 CSIS3 00H FFFFF2E0H Variable length serial I O shift register 4 SIO4 0000H FFFFF2E2H Variable length serial control register 4 CSIM4 FFFFF2E4H Variable length serial setting register 4 CSIB4 FFFFF2E6H Baud rate generator...

Page 117: ...F350H IIC control register 1 IICC1 R W FFFFF352H IIC status register 1 IICS1 R FFFFF354H IIC clock select register 1 IICCL1 FFFFF356H Slave address register 1 SVA1 FFFFF358H IIC shift register 1 IIC1 FFFFF35AH IIC function expansion register 1 IICX1 FFFFF35CH IIC clock expansion register 1 IICCE1 FFFFF360H Watch timer mode register WTNM FFFFF364H Watch timer clock select register WTNCS FFFFF366H W...

Page 118: ...rol register 7 TOC7 FFFFF3AEH Prescaler mode register 71 PRM71 R W 00H FFFFF3B0H 16 bit timer register 9 TM9 R FFFFF3B2H 16 bit capture compare register 90 CR90 FFFFF3B4H 16 bit capture compare register 91 CR91 Note 1 0000H FFFFF3B6H Prescaler mode register 90 PRM90 FFFFF3B8H 16 bit timer mode control register 9 TMC9 FFFFF3BAH Capture compare control register 9 CRC9 FFFFF3BCH Timer output control ...

Page 119: ... IEBus telegraph length registerNote DLR 01H FFFFF3ECH IEBus data registerNote DR R W FFFFF3EEH IEBus unit status registerNote USR R FFFFF3F0H IEBus interrupt status registerNote ISR R W 00H FFFFF3F2H IEBus slave status registerNote SSR 41H FFFFF3F4H IEBus communication success counterNote SCR 01H FFFFF3F6H IEBus transmit counterNote CCR R 20H FFFFF3F8H IEBus clock select registerNote IECLK R W 00...

Page 120: ... DMA operation No special sequence is required when reading the specific registers Cautions 1 If an interrupt request or a DMA request is acknowledged between the time PRCMD is generated 3 and the specific register write operation 4 that follows immediately after the write operation to the specific register is not performed and a protection error PRERR bit of SYS register 1 may occur Therefore set...

Page 121: ...ion of protection error 0 Protection error did not occur 1 Protection occurred The operating conditions of the PRERR flag are shown below a Set conditions PRERR 1 1 When a write operation to the specific register took place in a state where the store instruction operation for the recent peripheral I O was not a write operation to the PRCMD register 2 When the first store instruction operation foll...

Page 122: ... main clock oscillator is stopped by reset input or STOP mode setting the oscillation stabilization time is secured after the stop mode is canceled This oscillation stabilization time is set via the oscillation stabilization time select register OSTS The watchdog timer is used to count the oscillation stabilization time 2 If the main clock halt is released by clearing MCK to 0 after the main clock...

Page 123: ...XX 2 CK2 to CK0 4 3 Clock Output Function This function outputs the CPU clock via the CLKOUT pin When clock output is enabled the CPU clock is output via the CLKOUT pin When it is disabled a low level signal is output via the CLKOUT pin Output is stopped in the IDLE or STOP mode fixed to low level This function is controlled via the DCLK1 and DCLK0 bits in the PSC register A high impedance status ...

Page 124: ...ver when manipulating the PCC register in 8 bit units be sure not to change the values of CK1 and CK0 2 Do not set the STOP mode when the CPU is operating on the subclock CK2 1 Cautions 1 Do not change the CPU clock the values of CK2 to CK0 in the PCC register while CLKOUT is being output 2 Even if the MCK bit is set to 1 during main clock operation the main clock is not stopped The CPU clock stop...

Page 125: ...n be written to only when a specified combination of sequences is used For details see 3 4 9 Specific registers This register can be read written in 8 or 1 bit units After reset C0H R W Address FFFFF070H 7 6 5 4 3 2 1 0 PSC DCLK1 DCLK0 0 0 0 IDLE STP 0 DCLK1 DCLK0 Specification of CLKOUT pin operation 0 0 Output enabled 0 1 Hi Z outputNote 1 1 0 Setting prohibited 1 1 Output disabled after reset I...

Page 126: ...ress FFFFF380H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time fXX OSTS2 OSTS1 OSTS0 Clock 20 MHz 18 87 MHz 16 MHz 0 0 0 216 fXX 3 3 ms 3 5 ms 4 10 ms 0 0 1 218 Fxx after reset 13 1 ms 13 9 ms 16 4 ms 0 1 0 219 fXX 26 2 ms 27 8 ms 32 8 ms 0 1 1 220 fXX 52 4 ms 55 6 ms 65 5 ms 1 0 0 221 fXX 104 9 ms 111 1 ms 131 ms Other than above Setting prohibited ...

Page 127: ...his mode is canceled there is no need for the oscillator to wait for the oscillation stabilization time so normal operation can be resumed quickly When the IDLE bit in the power save control register PSC is set 1 the system switches to IDLE mode 3 Software STOP mode This mode stops the entire system by stopping the main clock oscillators The subclock continues to be supplied to keep on chip periph...

Page 128: ...ng via either the main clock or subclock The operating statuses in the HALT mode are listed in Table 4 1 2 Cancellation of HALT mode HALT mode can be canceled by an NMI request an unmasked maskable interrupt request or RESET input a Cancellation by interrupt request HALT mode is canceled regardless of the priority level when an NMI request or an unmasked maskable interrupt request occurs However t...

Page 129: ...lock is selected for count clock Operating Operates when fXT is selected for count clock 16 bit timer TM6 Operating Stopped 16 bit timer TM7 to TM12 Operating Stopped Watch timer Operates when main clock is selected for count clock Operating Operates when fXT is selected for count clock Watchdog timer Operating interval timer only CSI0 CSI2 to CSI6 Operating Operates when an external clock is sele...

Page 130: ...noise eliminator Operating Operates when fXT is selected for noise eliminator Key return function Operating AD0 to AD15 High impedanceNote 1 A1 to A15Note 2 HeldNote 1 high impedance when HLDAK 0 A16 to A21 HeldNote 1 high impedance when HLDAK 0 LBEN UBEN HeldNote 1 high impedance when HLDAK 0 R W DSTB WRLNote 2 WRHNote 2 RDNote 2 ASTB High level outputNote 1 high impedance when HLDAK 0 In externa...

Page 131: ... IDLE mode IDLE mode can be canceled by a non maskable interrupt an unmasked maskable interrupt request output from an operable on chip peripheral I O or RESET input Table 4 2 Operating Statuses in IDLE Mode 1 2 IDLE Mode Settings Item When Subclock Exists When Subclock Does Not Exist CPU Stopped ROM correction Stopped Clock generator Both main clock and subclock oscillating Clock supply to CPU an...

Page 132: ...rface Stopped NMI Operating INTP0 to INTP3 INTP7 to INTP9 Operating INTP4 and INTP5 Stopped External interrupt request INTP6 Operates when fXT is selected for the sampling clock Stopped Key return function Operating AD0 to AD15 High impedance A1 to A15Note Held A16 to A21 LBEN UBEN R W DSTB WRLNote WRHNote RDNote ASTB In external expansion mode HLDAK High impedance Note Only for the V850 SC1 and V...

Page 133: ...topped The external bus hold request HLDRQ is not acknowledged This mode can be set only when the main clock is being used as the CPU clock This mode is set when the STP bit in the power save control register PSC has been set to 1 Do not set this mode when the subclock has been selected as the CPU clock The operating statuses for software STOP mode are listed in Table 4 3 Caution To reduce the cur...

Page 134: ...he count clock for the watch timer Stopped 16 bit timer TM1 Stopped 16 bit timer TM5 Operates when fXT is selected for the count clock Stopped 16 bit timer TM6 Stopped 16 bit timer TM7 to TM12 Stopped Watch timer Operates when fXT is selected for the count clock Stopped operation disabled Watchdog timer Stopped CSI0 CSI2 to CSI6 Operates when an external clock is selected as the serial clock I2 C0...

Page 135: ...Held External bus interface Stopped NMI Operating INTP0 to INTP3 INTP7 to INTP9 Operating INTP4 and INTP5 Stopped External interrupt request INTP6 Operates when fXT is selected for the sampling clock Stopped Key return function Operating AD0 to AD15 High impedance A1 to A15Note Held A16 to A21 LBEN UBEN R W DSTB WRLNote WRHNote RDNote ASTB In external expansion mode HLDAK High impedance Note Only ...

Page 136: ...f time that must elapse until the oscillator s clock output stabilizes The oscillation stabilization time is set by the oscillation stabilization time select register OSTS Oscillation stabilization time WDT count time After the specified amount of time has elapsed system clock output starts and processing branches to the interrupt handler address Figure 4 2 Oscillation Stabilization Time STOP mode...

Page 137: ... instructions two or five instructions 7 If DMA operation is needed enable DMA operation Cautions 1 Insert two NOP instructions if the value of the ID bit of the PSW is not changed by executing the instruction that clears the NP bit to 0 5 and if changed insert five NOP instructions 6 The following shows an example of description Description example LDSR rX 5 NP bit 1 ST B r0 PRCMD r0 write to PRC...

Page 138: ...ation of power save mode as the result of an interrupt request iii Execution of the next instruction when an interrupt request is held pending following cancellation of the power save mode Conditions for interrupt request to be held pending When NP flag of PSW register is 1 NMI servicing in progress set by software When ID flag of PSW register is 1 interrupt request servicing in progress DI instru...

Page 139: ...ts rX value to PSW ST B r0 PRCMD r0 Writes to PRCMD ST B rD PSC r0 Sets PSC register LDSR rY 5 Returns PSW value NOP 6 or more NOP instructions NOP NOP NOP NOP NOP BR 2 Cancels PC discrepancy Remark It is assumed that rD PSC setting value rX value written to PSW and rY value written back to PSW have been set ...

Page 140: ...110 to P117 3 0 V PORTVDD1 5 5 VNote 2 PORTVDD2 Note 1 P04 to P07 P20 to P27 P120 to P127 P130 to P133 P140 to P147 P150 to P157 3 0 V PORTVDD2 5 5 VNote 2 VDD0 RESET When A D converter not used 4 0 V VDD0 5 5 V When A D converter used 4 5 V VDD0 ADCVDD 5 5 V VDD1 P170 to P176 4 0 V VDD1 5 5 V ADCVDD P70 to P77 P80 to P83 When A D converter not used 4 0 V ADCVDD 5 5 V When A D converter used 4 5 V...

Page 141: ...DD2 5 5 VNote 2 VDD0 RESET When A D converter not used 3 5 V VDD0 5 5 V When A D converter used 4 5 V VDD0 ADCVDD 5 5 V VDD1 P170 to P176 3 5 V VDD1 5 5 V ADCVDD P70 to P77 P80 to P83 When A D converter not used 3 5 V ADCVDD 5 5 V When A D converter used 4 5 V VDD0 ADCVDD 5 5 V Notes 1 Electrical specifications differ between the cases with operating frequency of 4 to 17 MHz and with operating fre...

Page 142: ...n Control of output data in output mode n 0 to 7 0 Outputs 0 1 Outputs 1 Remark In input mode When P0 is read the pin levels at that time are read Writing to P0 writes the values to that port This does not affect the input pins In output mode When P0 is read the values of P0 are read Writing to P0 writes the values to that port and those values are immediately output Port 0 includes the following ...

Page 143: ...o INTP3 pins An on chip noise eliminator is provided that uses analog delay to eliminate noise Consequently if a signal having a constant level is input for longer than a specified time to these pins it is detected as a valid edge Edge detection occurs only after the specified amount of time has elapsed b Elimination of noise from INTP4 to INTP6 and ADTRG pins A digital noise eliminator is provide...

Page 144: ...I O mode n 0 to 7 0 Output mode 1 Input mode b Rising edge specification register 0 EGP0 EGP0 can be read written in 8 or 1 bit units After reset 00H R W Address FFFFF0C0H 7 6 5 4 3 2 1 0 EGP0 EGP07 EGP06 EGP05 EGP04 EGP03 EGP02 EGP01 EGP00 EGP0n Control of rising edge detection n 0 to 7 0 Interrupt request signal does not occur at rising edge 1 Interrupt request signal occurs at rising edge Remar...

Page 145: ...tion n 0 to 7 0 Interrupt request signal does not occur at falling edge 1 Interrupt request signal occurs at falling edge Remark n 0 Control of NMI pin n 1 to 7 Control of INTP0 to INTP6 pins 4 Block diagram port 0 Figure 5 1 Block Diagram of P00 to P07 WRPM WRPORT RD P00 NMI P01 INTP0 P02 INTP1 P03 INTP2 P04 INTP3 P05 INTP4 ADTRG P06 INTP5 P07 INTP6 Selector Output latch P0n PM0n PM0 Internal bus...

Page 146: ...1 is read the pin levels at that time are read Writing to P1 writes the values to that port This does not affect the input pins In output mode When P1 is read the values of P1 are read Writing to P1 writes the values to that port and those values are immediately output Port 1 includes the following alternate functions Table 5 3 Port 1 Alternate Function Pins Pin Name Alternate Function I O PULLNot...

Page 147: ...utput mode Clear P1 and the PM1 register to 0 when using alternate function pins as outputs The logical sum ORed result of the port output and the alternate function pin is output from the pins When a reset is input the settings are initialized to input mode 2 Control registers a Port 1 mode register PM1 PM1 can be read written in 8 or 1 bit units After reset FFH R W Address FFFFF022H 7 6 5 4 3 2 ...

Page 148: ... 5 2 Block Diagram of P10 and P12 WRPM WRPF WRPORT RD VDD Selector PF1n PF1 PM1n PM1 P ch N ch Internal bus Output latch P1n Alternate function P10 SI0 SDA0 P12 SCK0 SCL0 Remarks 1 PF1 Port 1 function register PM1 Port 1 mode register RD Port 1 read signal WR Port 1 write signal 2 n 0 2 ...

Page 149: ...k Diagram of P11 P13 to P15 and P17 WRPM WRPORT RD Selector Output latch P1n PM1n PM1 Internal bus Alternate function P11 SO0 P13 SI4 RXD0 P14 SO4 TXD0 P15 SCK4 ASCK0 P17 TI5 TO5 Remarks 1 PM1 Port 1 mode register RD Port 1 read signal WR Port 1 write signal 2 n 1 3 to 5 7 ...

Page 150: ...FUNCTIONS User s Manual U15109EJ3V0UD 148 Figure 5 4 Block Diagram of P16 WRPM WRPORT RD Selector Output latch P16 PM16 PM1 Internal bus P16 Remark PM1 Port 1 mode register RD Port 1 read signal WR Port 1 write signal ...

Page 151: ...in levels at that time are read Writing to P2 writes the values to that port This does not affect the input pins In output mode When P2 is read the values of P2 are read Writing to P2 writes the values to that port and those values are immediately output Port 2 includes the following alternate functions Table 5 4 Port 2 Alternate Function Pins Pin Name Alternate Function I O PULLNote 1 Remark P20 ...

Page 152: ...ut mode Clear P2 and the PM2 register to 0 when using alternate function pins as outputs The logical sum ORed result of the port output and the alternate function pin is output from the pins When a reset is input the settings are initialized to input mode 2 Control registers a Port 2 mode register PM2 PM2 can be read written in 8 or 1 bit units After reset FFH R W Address FFFFF024H 7 6 5 4 3 2 1 0...

Page 153: ... 5 5 Block Diagram of P20 and P22 WRPM WRPF WRPORT RD VDD Selector PF2n PF2 PM2n PM2 P ch N ch Internal bus Output latch P2n Alternate function P20 SI2 SDA1 P22 SCK2 SCL1 Remarks 1 PF2 Port 2 function register PM2 Port 2 mode register RD Port 2 read signal WR Port 2 write signal 2 n 0 2 ...

Page 154: ...f P21 and P23 to P27 WRPM WRPORT RD Selector Output latch P2n PM2n PM2 Internal bus Alternate function P21 SO2 P23 TI90 P24 TI91 P25 TO90 P26 IERX0Note P25 IETX0Note Note Only for the V850 SC2 Remarks 1 PM2 Port 2 mode register RD Port 2 read signal WR Port 2 write signal 2 n 1 3 to 7 ...

Page 155: ...When P3 is read the pin levels at that time are read Writing to P3 writes the values to that port This does not affect the input pins In output mode When P3 is read the values of P3 are read Writing to P3 writes the values to that port and those values are immediately output Port 3 includes the following alternate functions Table 5 5 Port 3 Alternate Function Pins Pin Name Alternate Function I O P...

Page 156: ...P9 pins is specified by the rising edge specification register 1 EGP1 and falling edge specification register 1 EGN1 When using the alternate function A13 to A15 pins set this port via the memory address output mode register MAM Clear P3 and the PM3 register to 0 when using alternate function pins as outputs The logical sum ORed result of the port output and the alternate function pin is output fr...

Page 157: ...l does not occur at rising edge 1 Interrupt request signal occurs at rising edge Remark n 5 to 7 Control of INTP7 to INTP9 pins c Falling edge specification register 1 EGN1 EGN1 can be read written in 8 or 1 bit units After reset 00H R W Address FFFFF0C6H 7 6 5 4 3 2 1 0 EGN1 EGN17 EGN16 EGN15 0 0 0 0 0 EGN1n Control of falling edge detection n 5 to 7 0 Interrupt request signal does not occur at f...

Page 158: ...P37 WRPM WRPORT RD Selector Output latch P3n PM3n PM3 Internal bus Alternate function P30 TI6 TO6 P31 TI80 P32 TI81 P33 TO8 P34 TI71 A13Note P35 INTP7 A14Note P36 INTP8 A15Note P37 INTP9 Note Only for the V850 SC1 and V850 SC2 Remarks 1 PM3 Port 3 mode register RD Port 3 read signal WR Port 3 write signal 2 n 0 to 7 ...

Page 159: ...at that time are read Writing to P4 and P5 writes the values to those ports This does not affect the input pins In output mode When P4 and P5 are read their values are read Writing to P4 and P5 writes the values to those ports and those values are immediately output Ports 4 and 5 include the following alternate functions Table 5 6 Alternate Function Pins of Ports 4 and 5 Pin Name Alternate Functio...

Page 160: ...nd P5 output latch can be read by reading P4 and P5 while in output mode A software pull up function is not implemented When using the alternate function AD0 to AD15 pins set the pin functions via the memory expansion mode register MM This does not affect the PM4 and PM5 registers When a reset is input the settings are initialized to input mode 2 Control registers a Port 4 mode register and port 5...

Page 161: ... Block diagram ports 4 and 5 Figure 5 8 Block Diagram of P40 to P47 and P50 to P57 WRPM WRPORT RD Selector Output latch Pmn PMmn PMm Internal bus Pmn ADx Remarks 1 PMm Port m mode register RD Port m read signal WR Port m write signal 2 m 4 5 n 0 to 7 x 0 to 15 ...

Page 162: ...In input mode When P6 is read the pin levels at that time are read Writing to P6 writes the values to that port This does not affect the input pins In output mode When P6 is read the values of P6 are read Writing to P6 writes the values to that port and those values are immediately output Port 6 includes the following alternate functions Table 5 7 Port 6 Alternate Function Pins Pin Name Alternate ...

Page 163: ...alues of P6 output latch can be read by reading P6 while in output mode A software pull up function is not implemented When using the alternate function A16 to A21 pins set the pin functions via the memory expansion mode register MM This does not affect the PM6 register When a reset is input the settings are initialized to input mode 2 Control register a Port 6 mode register PM6 PM6 can be read wr...

Page 164: ...9EJ3V0UD 162 3 Block diagram port 6 Figure 5 9 Block Diagram of P60 to P65 WRPM WRPORT RD Selector Output latch P6n PM6n PM6 Internal bus P6n Ax Remarks 1 PM6 Port 6 mode register RD Port 6 read signal WR Port 6 write signal 2 n 0 to 5 x 16 to 21 ...

Page 165: ...level n 0 to 7 0 1 Read pin level of bit n After reset Undefined R Address FFFFF010H 7 6 5 4 3 2 1 0 P8 0 0 0 0 P83 P82 P81 P80 P8n Pin level n 0 to 3 0 1 Read pin level of bit n Ports 7 and 8 include the following alternate functions Table 5 8 Alternate Function Pins of Ports 7 and 8 Pin Name Alternate Function I O PULLNote Remark P70 ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P75 ANI5 P76 ANI6 Por...

Page 166: ... and P8 Data cannot be written to P7 or P8 A software pull up function is not implemented Values read from pins specified as analog inputs are undefined values Do not read values from P7 or P8 during A D conversion 2 Block diagram ports 7 and 8 Figure 5 10 Block Diagram of P70 to P77 and P80 to P83 Pmn ANIx RD Internal bus Remarks 1 RD Port 7 port 8 read signals 2 m 7 8 n 0 to 7 m 7 0 to 3 m 8 x 0...

Page 167: ...ls at that time are read Writing to P9 writes the values to that port This does not affect the input pins In output mode When P9 is read the values of P9 are read Writing to P9 writes the values to that port and those values are immediately output Port 9 includes the following alternate functions Table 5 9 Port 9 Alternate Function Pins Pin Name Alternate Function I O PULLNote 1 Remark P90 LBEN WR...

Page 168: ...de A software pull up function is not implemented When using P9 for control signals in expansion mode set the pin functions via the memory expansion mode register MM When a reset is input the settings are initialized to input mode Caution In the V850 SC1 and V850 SC2 when using port 9 as an I O port set the BIC bit of the system control register SYC to 0 Note that the BIC bit is 0 after system res...

Page 169: ...iagram of P90 to P96 WRPM WRPORT RD Selector Output latch P9n PM9n PM9 Internal bus P90 LBEN WRLNote P91 UBEN P92 R W WRHNote P93 DSTB RDNote P94 ASTB P95 HLDAK P96 HLDRQ Note Only for the V850 SC1 and V850 SC2 Remarks 1 PM9 Port 9 mode register RD Port 9 read signal WR Port 9 write signal 2 n 0 to 6 ...

Page 170: ...de When P10 is read the pin levels at that time are read Writing to P10 writes the values to that port This does not affect the input pins In output mode When P10 is read the values of P10 are read Writing to P10 writes the values to that port and those values are immediately output Port 10 includes the following alternate functions Table 5 10 Port 10 Alternate Function Pins Pin Name Alternate Fun...

Page 171: ...e of the V850 SC1 and V850 ASC2 this port is set via the memory address output mode register MAM Clear P10 and the PM10 register to 0 when using alternate function pins as outputs The logical sum ORed result of the port output and the alternate function pin is output from the pins When a reset is input the settings are initialized to input mode 2 Control register a Port 10 mode register PM10 PM10 ...

Page 172: ...rnal bus Output latch P10n Alternate function P100 KR0 TO7 A5Note P101 KR1 TI70 A6Note P102 KR2 TI00 A7Note P103 KR3 TI01 A8Note P104 KR4 TO0 A9Note P105 KR5 TI10 A10Note P106 KR6 TI11 A11Note P107 KR7 TO1 A12Note Note Only for the V850 SC1 and V850 SC2 Remarks 1 PU10 Pull up resistor option register 10 PM10 Port 10 mode register RD Port 10 read signal WR Port 10 write signal 2 n 0 to 7 ...

Page 173: ...tput mode n 0 to 7 0 Outputs 0 1 Outputs 1 Remark In input mode When P11 is read the pin levels at that time are read Writing to P11 writes the values to that port This does not affect the input pins In output mode When P11 is read the values of P11 are read Writing to P11 writes the values to that port and those values are immediately output Port 11 includes the following alternate functions Tabl...

Page 174: ...unction and setting use as the CANTX1 CANRX1 CANTX2 and CANRX2 pins can be performed via the port alternate function control register PAC When used as the A1 to A4 pins in the case of V850 SC1 and V850 SC2 this port is set via the memory address output mode register MAM In this case be sure to set the PM11 register PM110 to PM113 and P11 P110 to P113 to 0 When a reset is input the settings are ini...

Page 175: ...W Address FFFFF040H 7 6 5 4 3 2 1 0 PAC PAC117Note PAC116Note PAC115 PAC114 0 0 0 WAC WAC Control of wait function 0 Wait function OFF 1 Wait function ON PAC11n Control of port alternate function n 4 to 7 0 Port function 1 Alternate function Note Bits PAC117 and PAC116 are available only for the µPD703089Y and 70F3089Y Set bits 7 and 6 to 0 when using the µPD703088Y ...

Page 176: ...ctor P110 WAIT ANote 1 P114 CANTX1Note 2 P115 CANRX1Note 2 P116 CANTX2Note 3 P117 CANRX2Note 3 Alternate function Selector Internal bus Notes 1 Only for the V850 SC1 and V850 SC2 2 Only for the V850 SC3 3 Only for the µPD703089Y and 70F3089Y Remarks 1 PM11 Port 11 mode register RD Port 11 read signal WR Port 11 write signal PAC Port alternate function control register PAC 2 n 0 4 to 7 m 4 to 7 ...

Page 177: ...lock Diagram of P111 to P113 WRPM WRPORT RD Selector Output latch P11n PM11n PM11 Internal bus P111 A2Note P113 A4Note Alternate function Note Only for the V850 SC1 and V850 SC2 Remarks 1 PM11 Port 11 mode register RD Port 11 read signal WR Port 11 write signal 2 n 1 to 3 ...

Page 178: ...l of output data in output mode n 0 to 7 0 Outputs 0 1 Outputs 1 Remark In input mode When P12 is read the pin levels at that time are read Writing to P12 writes the values to that port This does not affect the input pins In output mode When P12 is read the values of P12 are read Writing to P12 writes the values to that port and those values are immediately output Port 12 includes the following al...

Page 179: ...rnate function control register 2 PAC2 When using this port as the TO10 and TO11 pins set P126 P127 PM126 and PM127 to 0 When a reset is input the settings are initialized to input mode 2 Control registers a Port 12 mode register PM12 PM12 can be read written in 8 or 1 bit units After reset FFH R W Address FFFFF038H 7 6 5 4 3 2 1 0 PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120 PM12n Control...

Page 180: ...re 5 15 Block Diagram of P120 to P125 RD WRPORT WRPM Output latch P12n PM12n PM12 PAC12n PAC2 Selector Alternate function Selector Internal bus Remarks 1 PM12 Port 12 mode register RD Port 12 read signal WR Port 12 write signal PAC2 Port alternate function control register 2 2 n 0 to 5 ...

Page 181: ...3V0UD 179 Figure 5 16 Block Diagram of P126 and P127 WRPM WRPORT RD Selector Output latch P12n PM12n Alternate function PM12 Internal bus P126 TO10 P127 TO11 Remarks 1 PM12 Port 12 mode register RD Port 12 read signal WR Port 12 write signal 2 n 6 7 ...

Page 182: ...ues to that port and those values are immediately output 1 Function of P13 pins Port 13 is a 4 bit port for which I O settings can be controlled in 1 bit units I O settings are controlled via the port 13 mode register PM13 In output mode the values set to each bit are output to port 13 P13 When using this port in input mode the pin statuses can be read by reading P13 Also the values of P13 output ...

Page 183: ...D 181 3 Block diagram port 13 Figure 5 17 Block Diagram of P130 to P133 WRPM WRPORT RD P130 P131 P132 P133 Selector Output latch P13n PM13n PM13 Internal bus Remarks 1 PM13 Port 13 mode register RD Port 13 read signal WR Port 13 write signal 2 n 0 to 3 ...

Page 184: ...14 is read the pin levels at that time are read Writing to P14 writes the values to that port This does not affect the input pins In output mode When P14 is read the values of P14 are read Writing to P14 writes the values to that port and those values are immediately output Port 14 includes the following alternate functions Table 5 13 Port 14 Alternate Function Pins Pin Name Alternate Function I O...

Page 185: ...lues of P14 output latch can be read by reading P14 while in output mode Clear P14 and the PM14 register to 0 when using alternate function pins as outputs The logical sum ORed result of the port output and the alternate function pin is output from the pins When a reset is input the settings are initialized to input mode 2 Control register a Port 14 mode register PM14 PM14 can be read written in 8...

Page 186: ...140 to P147 WRPM WRPORT RD Selector Output latch P14n PM14n PM14 Internal bus Alternate function P140 SI3 RXD1 P141 SO3 TXD1 P142 SCK3 ASCK1 P143 RXD2 P144 TXD2 P145 ASCK2 P146 TI100 P147 TI101 Remarks 1 PM14 Port 14 mode register RD Port 14 read signal WR Port 14 write signal 2 n 0 to 7 ...

Page 187: ...When P15 is read the pin levels at that time are read Writing to P15 writes the values to that port This does not affect the input pins In output mode When P15 is read the values of P15 are read Writing to P15 writes the values to that port and those values are immediately output Port 15 includes the following alternate functions Table 5 14 Port 15 Alternate Function Pins Pin Name Alternate Functi...

Page 188: ...lues of P15 output latch can be read by reading P15 while in output mode Clear P15 and the PM15 register to 0 when using alternate function pins as outputs The logical sum ORed result of the port output and the alternate function pin is output from the pins When a reset is input the settings are initialized to input mode 2 Control register a Port 15 mode register PM15 PM15 can be read written in 8...

Page 189: ...Block Diagram of P150 to P157 WRPM WRPORT RD Selector Output latch P15n PM15n PM15 Internal bus Alternate function P150 RXD3 P151 TXD3 P152 ASCK3 P153 TI110 P154 TI111 P155 TO12 P156 TI120 P157 TI121 Remarks 1 PM15 Port 15 mode register RD Port 15 read signal WR Port 15 write signal 2 n 0 to 7 ...

Page 190: ...Remark In input mode When P17 is read the pin levels at that time are read Writing to P17 writes the values to that port This does not affect the input pins In output mode When P17 is read the values of P17 are read Writing to P17 writes the values to that port and those values are immediately output Port 17 includes the following alternate functions Table 5 15 Port 17 Alternate Function Pins Pin ...

Page 191: ...read by reading P17 Also the values of P17 output latch can be read by reading P17 while in output mode When using this port as the VM45 pin set via the VM45 control register VM45C In this case be sure to set P176 and PM176 to 0 When a reset is input the settings are initialized to input mode 2 Control register a Port 17 mode register PM17 PM17 can be read written in 8 or 1 bit units After reset 7...

Page 192: ... 3 Block diagram port 17 Figure 5 20 Block Diagram of P170 to P175 WRPM WRPORT RD Selector Output latch P17n PM17n PM17 Internal bus P170 P171 P172 P173 P174 P175 Remarks 1 PM17 Port 17 mode register RD Port 17 read signal WR Port 17 write signal 2 n 0 to 5 ...

Page 193: ...Manual U15109EJ3V0UD 191 Figure 5 21 Block Diagram of P176 WRPM WRPORT RD Selector Output latch P176 PM176 PM17 Internal bus Alternate function P176 VM45 Remark PM17 Port 17 mode register RD Port 17 read signal WR Port 17 write signal ...

Page 194: ...put PM02 1 Setting not needed for P02 P03 INTP2 Input PM03 1 Setting not needed for P03 P04 INTP3 Input PM04 1 Setting not needed for P04 INTP4 Input P05 ADTRG Input PM05 1 Setting not needed for P05 P06 INTP5 Input PM06 1 Setting not needed for P06 P07 INTP6 Input PM07 1 Setting not needed for P07 SI0 Input PM10 1 Setting not needed for P10 P10 SDA0 I O PM10 0 P10 0 PF10 1 P11 SO0 Output PM11 0 P...

Page 195: ...TO9 Output PM25 0 P25 0 P26 IERX0Note 1 Input PM26 1 Setting not needed for P26 P27 IETX0Note 1 Output PM27 0 P27 0 TI6 Input PM30 1 Setting not needed for P30 P30 TO6 Output PM30 0 P30 0 P31 TI80 Input PM31 1 Setting not needed for P31 P32 TI81 Input PM32 1 Setting not needed for P32 P33 TO8 Output PM33 0 P33 0 TI71 Input PM34 1 Setting not needed for P34 P34 A13Note 2 Output PM34 0 P34 0 Refer t...

Page 196: ...t needed for PM90 Setting not needed for P90 Refer to 3 4 6 1 MM P91 UBEN Output Setting not needed for PM91 Setting not needed for P91 Refer to 3 4 6 1 MM R W Output P92 WRHNote Output Setting not needed for PM92 Setting not needed for P92 Refer to 3 4 6 1 MM DSTB Output P93 RDNote Output Setting not needed for PM93 P93 1 Refer to 3 4 6 1 MM P94 ASTB Output Setting not needed for PM94 P94 1 Refer...

Page 197: ...ote 1 Output PM105 0 P105 0 Refer to 3 4 6 2 MAM KR6 Input TI11 Input PM106 1 Setting not needed for P106 P106 A11Note 1 Output PM106 0 P106 0 Refer to 3 4 6 2 MAM KR7 Input PM107 1 Setting not needed for P107 TO1 Output P107 A12Note 1 Output PM107 0 P107 0 Refer to 3 4 6 2 MAM WAIT Input PM110 1 Setting not needed for P110 WAC 1 PAC P110 A1Note 1 Output PM110 0 P110 0 Refer to 3 4 6 2 MAM P111 A2...

Page 198: ... P124 SI6 Input PM124 1 P124 0 PAC124 1 PAC2 P125 SO6 Output PM125 0 P125 0 PAC125 1 PAC2 P126 TO10 Output PM126 0 P126 0 P127 TO11 Output PM127 0 P127 0 SI3 Input P140 RXD1 Input PM140 1 Setting not needed for P140 SO3 Output P141 TXD1 Output PM141 0 P141 0 Input PM142 1 Setting not needed for P142 SCK3 Output PM142 0 P142 0 P142 ASCK1 Input PM142 1 Setting not needed for P142 P143 RXD2 Input PM1...

Page 199: ...1 Setting not needed for P157 P176 VM45 Output PM176 0 P176 0 Refer to 14 3 2 VM45C Caution When changing the output level of ports 0 and 3 by setting the port function output mode of ports 0 and 3 the interrupt request flag will be set because ports 0 and 3 also have alternate functions as external interrupt request inputs Therefore be sure to set the corresponding interrupt mask flag to 1 before...

Page 200: ...the status of the pin does not change Once data has been written to the output latch it is retained until new data is written to the output latch Caution A bit manipulation instruction CLR1 SET1 NOT1 manipulates 1 bit but accesses a port in 8 bit units If this instruction is executed to manipulate a port with a mixture of input and output bits the contents of the output latch of a pin set in the i...

Page 201: ...connected 6 1 Features Address bus separate output possible only for the V850 SC1 and V850 SC2 16 bit data bus Able to be connected to external devices via pins with alternate functions as ports Wait function Programmable wait function up to 3 wait states can be inserted every 2 blocks External wait control through WAIT input pin Idle state insertion function Bus mastership arbitration function Bu...

Page 202: ...ite control LBEN UBEN R W DSTB WRLNote WRHNote RDNote Port 9 P90 to P93 Address strobe ASTB Port 9 P94 Bus hold control HLDRQ HLDAK Port 9 P95 P96 External wait control WAIT Port 11 P110 Note Only for the V850 SC1 and V850 SC2 The bus interface function of each pin is enabled by setting the memory expansion mode register MM or memory address output mode register MAM for the V850 SC1 and V850 SC2 a...

Page 203: ...al is output regardless of the BIC bit setting in the external expansion mode set by the memory expansion mode register MM Caution In the V850 SC1 and V850 SC2 when using port 9 as an I O port set the BIC bit to 0 Note that the BIC bit is 0 after system reset 6 3 Bus Access 6 3 1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows Table 6 2 Number...

Page 204: ...te data External data bus a Access to even addresses 0 7 0 7 8 15 Byte data External data bus b Access to odd addresses 2 Halfword access 16 bits In halfword access to external memory data is handled as is because the data bus is fixed to 16 bits Figure 6 2 Halfword Access 16 Bits 0 0 15 15 Halfword data External data bus 3 Word access 32 bits In word access to external memory the lower halfword i...

Page 205: ... Memory Block Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 On chip peripheral I O area Internal RAM area External memory area FFFFFFH F00000H EFFFFFH E00000H DFFFFFH D00000H CFFFFFH C00000H BFFFFFH B00000H AFFFFFH A00000H 9FFFFFH 900000H 8FFFFFH 800000H 7FFFFFH 700000H 6FFFFFH 600000H 5FFFFFH 500000H 4FFFFFH 4...

Page 206: ...Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DWC DW71 DW70 DW61 DW60 DW51 DW50 DW41 DW40 DW31 DW30 DW21 DW20 DW11 DW10 DW01 DW00 DWn1 DWn0 Number of wait states to be inserted 0 0 0 0 1 1 1 0 2 1 1 3 n Blocks into which wait states are inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 11 6 Blocks 12 13 7 Blocks 14 15 Block 0 is reserved for the internal ROM area...

Page 207: ...T pin are alternate function pins in the V850 SC1 and V850 SC2 the WAIT pin based wait function cannot be used when using a separate bus programmable wait can be used however Similarly a separate bus cannot be used when the WAIT pin based wait function is being used 6 5 3 Relationship between programmable wait and external wait A wait cycle is inserted as a result of an OR operation between the wa...

Page 208: ...grammed for all memory blocks 1 Bus cycle control register BCC This register can be read written in 16 bit units After reset AAAAH R W Address FFFFF062H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCC BC71 0 BC61 0 BC51 0 BC41 0 BC31 0 BC21 0 BC11 0 BC01 0 BCn1 Idle state insert specification 0 Not inserted 1 Inserted n Blocks into which Idle state is inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4...

Page 209: ... indicating that the request for the bus is cleared these pins are driven again During the bus hold period the internal operation continues until the next external memory access The bus hold status can be recognized by the HLDAK pin becoming active low This feature can be used to design a system where two or more bus masters exist such as when a multi processor configuration is used and when a DMA...

Page 210: ... the HALT mode the HLDAK pin immediately becomes active when the HLDRQ pin becomes active and the bus hold status is set When the HLDRQ pin becomes inactive the HLDAK pin becomes inactive As a result the bus hold status is cleared and the HALT mode is set again HLDRQ HLDAK 1 2 3 4 5 7 8 9 6 1 HLDRQ 0 acknowledged 2 All bus cycle start requests pending 3 End of current bus cycle 4 Bus idle status 5...

Page 211: ...bit of the system control register SYC see 6 2 2 1 System control register SYC V850 SC1 V850 SC2 Figure 6 8 Memory Read 1 4 a 0 waits T1 T2 T3 CLKOUT output A16 to A21Note output AD0 to AD15 I O Address Data Address ASTB output R W output DSTB RDNote output UBEN LBEN output WAIT input WRHNote WRLNote output H A1 to A15 output Address Note Only for the V850 SC1 and V850 SC2 Remarks 1 indicates the ...

Page 212: ...0 to AD15 I O Address Address ASTB output R W output DSTB RDNote output UBEN LBEN output WAIT input WRHNote WRLNote output T3 Data H A1 to A15Note output Address Note Only for the V850 SC1 and V850 SC2 Remarks 1 indicates the sampling timing when the number of programmable waits is set to 1 2 The broken lines indicate the high impedance state ...

Page 213: ...output AD0 to AD15 I O Address Address ASTB output R W output DSTB RDNote output UBEN LBEN output WAIT input WRHNote WRLNote output H TI Data A16 to A21 output Address Note Only for the V850 SC1 and V850 SC2 Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken lines indicate the high impedance state ...

Page 214: ...ddress CLKOUT output A1 to A15Note output AD0 to AD15 I O ASTB output R W output DSTB RDNote output UBEN LBEN output WAIT input WRHNote WRLNote output A16 to A21 output Note Only for the V850 SC1 and V850 SC2 Remarks 1 indicates the sampling timing when the number of programmable waits is set to 1 2 The broken lines indicate the high impedance state ...

Page 215: ...put UBEN LBEN output WAIT input RDNote 1 output WRHNote 1 WRLNote 1 output A1 to A15Note 1 output Notes 1 Only for the V850 SC1 and V850 SC2 2 AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken lines indica...

Page 216: ... RDNote 1 output WRHNote 1 WRLNote 1 output T3 DataNote 2 Address H A1 to A15Note 1 output Address Notes 1 Only for the V850 SC1 and V850 SC2 2 AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 1 2 The broken lines indic...

Page 217: ...ddress ASTB output Undefined Address Address Note 1 Note 3 Notes 1 If the HLDRQ signal is inactive high level at this sampling timing the bus hold state is not entered 2 Only for the V850 SC1 and V850 SC2 3 If the bus hold status is entered after a write cycle a high level may be output momentarily from the R W pin immediately before the HLDAK signal changes from high level to low level Remarks 1 ...

Page 218: ...ch continuous 4 6 10 Memory Boundary Operation Condition 6 10 1 Program space 1 Do not execute a branch to the on chip peripheral I O area or a continuous fetch from the internal RAM area to peripheral I O area If a branch or instruction fetch is executed the NOP instruction code is continuously fetched and fetching from external memory is not performed 2 A prefetch operation extending over the on...

Page 219: ...sing can be started exception trap by the TRAP instruction software exception or by generation of an exception event fetching of an illegal op code 7 1 1 Features Interrupts Non maskable 2 sources Maskable Number of maskable interrupt sources differs depending on product V850 SC1 µPD703068Y 70F3089Y 49 sources V850 SC2 µPD703069Y 70F3089Y 51 sources V850 SC3 µPD703088Y 53 sources µPD703089Y 70F308...

Page 220: ...transfer end DMA0 0120H 00000120H nextPC DMAIC0 11 INTDMA1 DMA1 transfer end DMA1 0130H 00000130H nextPC DMAIC1 12 INTDMA2 DMA2 transfer end DMA2 0140H 00000140H nextPC DMAIC2 13 INTTM00 TM0 and CR00 match TI01 pin valid edge TM0 0150H 00000150H nextPC TMIC00 14 INTTM01 TM0 and CR01 match TI00 pin valid edge TM0 0160H 00000160H nextPC TMIC01 15 INTTM10 TM1 and CR10 match TI11 pin valid edge TM1 01...

Page 221: ...ch TI90 pin valid edge TM9 02B0H 000002B0H nextPC TMIC91 36 INTSR1 INTCSI3 UART1 receive end CSI3 transmit end UART1 CSI3 02C0H 000002C0H nextPC CSIC3 37 INTST1 UART1 transmit end UART1 02D0H 000002D0H nextPC STIC1 38 INTDMA3 DMA3 transfer end DMA3 02E0H 000002E0H nextPC DMAIC3 39 INTDMA4 DMA4 transfer end DMA4 02F0H 000002F0H nextPC DMAIC4 40 INTDMA5 DMA5 transfer end DMA5 0300H 00000300H nextPC ...

Page 222: ...00003E0H nextPC TMIC121 Maskable Interrupt 55 INTIIC1 INTIIC2 I2 C interrupt CSI2 transmit end I2 C1 SIO2 03F0H 000003F0H nextPC CSIC2 Remarks 1 Default Priority Priority when two or more maskable interrupt requests occur at the same time The highest priority is 0 Restored PC The value of the PC saved to EIPC or FEPC when interrupt exception processing is started However the value of the PC saved ...

Page 223: ...rrupt occurs INTWDT functions as the non maskable interrupt INTWDT only when the WDTM4 bit of the watchdog timer mode register WDTM is set to 1 While the service routine of a non maskable interrupt is being executed PSW NP 1 the acknowledgement of another non maskable interrupt request is held pending The pending NMI is acknowledged when PSW NP is cleared to 0 after the original service routine of...

Page 224: ... to the higher halfword FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Loads the handler address 00000010H 00000020H of the non maskable interrupt routine to the PC and transfers control Figure 7 1 Non Maskable Interrupt Servicing NMI input Non maskable interrupt request Interrupt servicing Interrupt request pending FEPC FEPSW ECR FECC PSW NP PSW EP PSW ID PC restored PC ...

Page 225: ...I request PSW NP 1 NMI request held pending regardless of the NP bit of PSW Pending NMI request processed b If a new NMI request is generated twice while an NMI service routine is being executed Main routine NMI request NMI request Held pending because NMI service program is being processed Held pending because NMI service program is being processed NMI request Only one NMI request is acknowledged...

Page 226: ...bit of the PSW is 1 2 Transfers control back to the address of the restored PC and PSW How the RETI instruction is processed is shown below Figure 7 3 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt servicin...

Page 227: ...1 8 7 6 5 4 3 2 1 0 PSW 0 NP EP ID SAT CY OV S Z NP NMI servicing state 0 No NMI interrupt servicing 1 NMI interrupt currently being serviced 7 2 4 Noise eliminator of NMI pin NMI pin noise is eliminated by a noise eliminator using analog delay Therefore a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period The edge is detected only after...

Page 228: ...ge is specified by using the EGP0 and EGN0 registers When using P00 as an output port set the NMI valid edge to neither rising nor falling edge detected 1 Format of rising edge specification register 0 EGP0 After reset 00H R W Address FFFFF0C0H Symbol 7 6 5 4 3 2 1 0 EGP0 EGP07 EGP06 EGP05 EGP04 EGP03 EGP02 EGP01 EGP00 EGP0n Rising edge validity control 0 No interrupt request signal occurs at the ...

Page 229: ...pability interrupts with the same priority level cannot be nested To use multiple interrupts it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction When the WDTM4 bit of the watchdog timer mode register WDTM is set to 0 the watchdog timer overflo...

Page 230: ...owledged CPU processing Mask Yes No PSW ID 0 Priority higher than that of interrupt currently being serviced Interrupt request pending PSW NP PSW ID Interrupt request pending No No No No 1 0 1 0 INT input Yes Yes Yes Yes Priority higher than that of other interrupt request Highest default priority of interrupt requests with the same priority Interrupt enable mode Restored PC PSW Exception code 0 1...

Page 231: ...f the PSW is 0 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 7 6 RETI Instruction Processing RETI instruction Restores original processing PC PSW EIPC EIPSW PSW EP 1 0 1 0 PC PSW FEPC FEPSW PSW NP Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during maskable interrupt servicing in orde...

Page 232: ...aving the same priority level specified by xxPRn are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level beforehand For more information refer to Table 7 1 Programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag Note that when a...

Page 233: ...s held pending even if interrupts are enabled because its priority is the same as that of g Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled Although the priority of interrupt request d is higher than that of c d is held pe...

Page 234: ...Servicing of p Servicing of q Servicing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status Pending interrupt requests are acknowledged after s...

Page 235: ...maskable interrupt and sets the control conditions for each maskable interrupt request The interrupt control register can be read written in 8 or 1 bit units Caution If the following three conditions conflict interrupt servicing is executed twice However this does not occur when DMA is not used Execution of a bit manipulation instruction corresponding to the interrupt request flag xxIFn An interru...

Page 236: ... flag 0 Enables interrupt servicing 1 Disables interrupt servicing pending xxPRn2 xxPRn1 xxPRn0 Interrupt priority specification bit 0 0 0 Specifies level 0 highest 0 0 1 Specifies level 1 0 1 0 Specifies level 2 0 1 1 Specifies level 3 1 0 0 Specifies level 4 1 0 1 Specifies level 5 1 1 0 Specifies level 6 1 1 1 Specifies level 7 lowest Note Automatically reset by hardware when interrupt request ...

Page 237: ...MIF70 TMMK70 0 0 0 TMPR702 TMPR701 TMPR700 FFFFF124H TMIC71 TMIF71 TMMK71 0 0 0 TMPR712 TMPR711 TMPR710 FFFFF126H CSIC6 CSIF6 CSMK6 0 0 0 CSPR62 CSPR61 CSPR60 FFFFF128H TMIC5 TMIF5 TMMK5 0 0 0 TMPR52 TMPR51 TMPR50 FFFFF12AH WTNIC WTNIF WTNMK 0 0 0 WTNPR2 WTNPR1 WTNPR0 FFFFF12CH WTNIIC WTNIIF WTNIMK 0 0 0 WTNIPR2 WTNIPR1 WTNIPR0 FFFFF12EH CSIC0 CSIF0 CSMK0 0 0 0 CSPR02 CSPR01 CSPR00 FFFFF130H TMIC6...

Page 238: ...PIC7 PIF7 PMK7 0 0 0 PPR72 PPR71 PPR70 FFFFF15AH SRIC2 SRIF2 SRMK2 0 0 0 SRPR22 SRPR21 SRPR20 FFFFF15CH STIC2 STIF2 STMK2 0 0 0 STPR22 STPR21 STPR20 FFFFF15EH SRIC3 SRIF3 SRMK3 0 0 0 SRPR32 SRPR31 SRPR30 FFFFF160H STIC3 STIF3 STMK3 0 0 0 STPR32 STPR31 STPR30 FFFFF162H TMIC100 TMIF100 TMMK100 0 0 0 TMPR1002 TMPR1001 TMPR1000 FFFFF164H TMIC101 TMIF101 TMMK101 0 0 0 TMPR1012 TMPR1011 TMPR1010 FFFFF16...

Page 239: ...th priority n not acknowledged 1 Interrupt request with priority n acknowledged Remark n 0 to 7 priority level 7 3 6 ID flag The interrupt disable flag ID controls the enabling and disabling of maskable interrupt requests and is assigned to the PSW Figure 7 9 ID Flag After reset 00000020H Symbol 31 8 7 6 5 4 3 2 1 0 PSW 0 NP EP ID SAT CY OV S Z ID Specifies maskable interrupt servicingNote 0 Maska...

Page 240: ...on of noise from INTP0 to INTP3 and INTP7 to INTP9 pins An on chip noise eliminator is provided that uses analog delay to eliminate noise Consequently if a signal having a constant level is input for longer than a specified time it is detected as a valid edge Edge detection occurs only after the specified amount of time has elapsed 2 Elimination of noise from INTP4 and INTP5 pins A digital noise e...

Page 241: ...e is input within these 3 clocks an interrupt request may occur Therefore observe the following points when using the interrupt and DMA functions When using the interrupt function after 3 sampling clocks have elapsed enable interrupts after the interrupt request flag bit 7 of PIC6 has been cleared When using the DMA function after 3 sampling clocks have elapsed enable DMA by setting bit 0 of DCHCn...

Page 242: ...NTP0 to INTP9 pins are set to the neither rising nor falling edge detected state Therefore the NMI pin functions as a normal port and interrupt requests cannot be acknowledged unless a valid edge is specified by using the EGP0 and EGN0 registers When using P01 to P07 or P35 to P37 as output ports set the valid edges of INTP0 to INTP6 or INTP7 to INTP9 to neither rising nor falling edge detected or...

Page 243: ... processing and transfers control to the handler routine 1 Saves the restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code to the lower 16 bits EICC of ECR interrupt source 4 Sets the EP and ID bits of the PSW 5 Loads the handler address 00000040H or 00000050H of the software exception routine in the PC and transfers control How a software exception is processed is shown ...

Page 244: ...of the PSW is 1 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 7 11 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during software exception processing in o...

Page 245: ...SW is a status flag used to indicate that exception processing is in progress It is set when an exception occurs Figure 7 12 EP Flag EP After reset 00000020H Symbol 31 8 7 6 5 4 3 2 1 0 PSW 0 NP EP ID SAT CY OV S Z EP Exception processing 0 Exception processing is not in progress 1 Exception processing is in progress ...

Page 246: ... Figure 7 13 Illegal Op Code 15 16 17 23 22 x 21 x 20 x x x x x x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 12 13 1 1 1 1 0 to 1 0 1 x don t care 7 5 2 Operation If an exception trap occurs the CPU performs the following processing and transfers control to the handler routine 1 Saves the restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code 0060H to the...

Page 247: ...t of the PSW is 1 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 7 15 RETI Instruction Processing RETI instruction Jump to PC PC PSW EIPC EIPSW PSW EP 1 0 1 0 PC PSW FEPC FEPSW PSW NP Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during exception trap processing in order to restore the ...

Page 248: ...and Exceptions RESET NMI INT TRAP ILGOP RESET NMI INT TRAP ILGOP RESET Reset NMI Non maskable interrupt INT Maskable interrupt TRAP Software exception ILGOP Illegal op code exception Item on the left ignores the item above Item on the left is ignored by the item above Item above is higher than the item on the left in priority Item on the left is higher than the item above in priority ...

Page 249: ...askable interrupt or exception is generated in a maskable interrupt or exception service program EIPC and EIPSW must be saved The following example shows the procedure of interrupt nesting 1 To acknowledge maskable interrupts in service program Service program of maskable interrupt or exception 2 To generate exception in service program Service program of maskable interrupt or exception EIPC saved...

Page 250: ...ing name of each peripheral unit see Table 7 2 n Peripheral unit number see Table 7 2 Priorities of maskable interrupts High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the RETI instruction has been ex...

Page 251: ... time system clock Internal interrupt External interrupt Conditions Minimum 11 13 Maximum 18 20 Time to eliminate noise 2 system clocks is also necessary for external interrupts except when In IDLE STOP mode External bus is accessed Two or more interrupt request non sample instructions are executed in succession Access to interrupt control register System clock IF ID IFX IDX IFX EX MEM INT1 INT2 I...

Page 252: ...rupts are not masked MK flag 0 7 system clocks are required until the interrupt request is acknowledged following execution of the EI instruction interrupt enable If the DI instruction interrupt disable is executed during the 7 system clocks the interrupt request is not acknowledged by the CPU Therefore instructions equivalent to 7 system clocks must be inserted as the number of instruction execut...

Page 253: ... at the 8th clock after EI instruction execution so an interrupt request is acknowledged by the CPU and the interrupt is serviced 2 This timing does not imply that the interrupt servicing routine instruction is executed at the 8th clock after EI instruction The interrupt servicing routine instruction is executed 4 system clocks after interrupt request acknowledgement by the CPU 3 This example indi...

Page 254: ...equest is acknowledged b When DI instruction is executed at 7th system clock after EI instruction execution interrupt request is not acknowledged ei signal intrq signal ei signal intrq signal intrq signal generated intrq signal not generated 7 9 Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer When using the DMA function execute the DI instruction before performing bit ma...

Page 255: ...r 1 bit units After reset 00H R W Address FFFFF3D0H 7 6 5 4 3 2 1 0 KRM KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 KRMn Key return mode control 0 Does not detect key return signal 1 Detects key return signal Caution If the key return mode register KRM is changed an interrupt request flag may be set To avoid setting this flag change the KRM register after disabling interrupts and then enable interrupts after c...

Page 256: ... INTERRUPT EXCEPTION PROCESSING FUNCTION User s Manual U15109EJ3V0UD 254 Figure 7 18 Block Diagram of Key Return INTKR Key return mode register KRM KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0 ...

Page 257: ...er output set the value of port 3 P3 to 0 port mode output and the port 3 mode register PM3 to 0 When using the P25 TO9 pins as TO9 timer output set the value of port 2 P2 to 0 port mode output and the port 2 mode register PM2 to 0 When using the P126 TO10 and P127 TO11 pins as TO10 and TO11 timer output set the value of port 12 P12 to 0 port mode output and the port 12 mode register PM12 to 0 Whe...

Page 258: ... INTTMn0 3 Timer output control register n TOCn fXX 2 Selector Selector Selector Selector PRMn2 Prescaler mode register n1 PRMn1 Noise eliminator Noise eliminator Note The count clock is set by the PRMn0 and PRMn1 registers Remark n 0 1 7 to 12 1 Interval timer Generates an interrupt at preset time intervals 2 PPG output Can output a square wave with a frequency and output pulse width that can be ...

Page 259: ...7 to 12 1 16 bit timer registers 0 1 7 to 12 TM0 TM1 TM7 to TM12 TMn is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of the input clock If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count value is reset to 0000H in the following case...

Page 260: ...e for the TIn1 pin is specified as the capture trigger refer to Table 8 3 n 0 1 7 to 12 Table 8 2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0 ESn01 ESn00 Valid Edge of TIn0 Pin CRn0 Capture Trigger 0 0 Falling edge Rising edge 0 1 Rising edge Falling edge 1 0 Setting prohibited Setting prohibited 1 1 Both rising and falling edges No capture operation Remark n 0 1 7 to 12 Table 8 3 Valid Edg...

Page 261: ...ure trigger is specified as the valid edge of TIn0 the relationship between the TIn0 valid edge and the CRn1 capture trigger is as follows Table 8 4 Valid Edge of TIn0 Pin and Capture Trigger of CRn1 ESn01 ESn00 TIn0 Pin Valid Edge CRn1 Capture Trigger 0 0 Falling edge Falling edge 0 1 Rising Edge Rising Edge 1 0 Setting prohibited Setting prohibited 1 1 Both rising and falling edges Both rising a...

Page 262: ...RMn1 Remark n 0 1 7 to 12 1 16 bit timer mode control registers 0 1 7 to 12 TMC0 TMC1 TMC7 to TMC12 TMCn specifies the operation mode of the 16 bit timer and the clear mode output timing and overflow detection of 16 bit timer register n TMCn is set by an 8 bit or 1 bit memory manipulation instruction RESET input clears TMC0 TMC1 and TMC7 to TMC12 to 00H Caution 16 bit timer register n starts opera...

Page 263: ...Mn and CRn0 match between TMn and CRn1 or valid edge of TIn0 1 1 0 Match between TMn and CRn0 or match between TMn and CRn1 1 1 1 Clears and starts on match between TMn and CRn0 Match between TMn and CRn0 match between TMn and CRn1 or valid edge of TIn0 Generates on match between TMn and CRn0 and match between TMn and CRn1 OVFn Detection of overflow of 16 bit timer register n 0 Does not overflow 1...

Page 264: ...CRCn be sure to stop the timer operation 2 When the mode in which the timer is cleared and started on a match between TMn and CRn0 is selected by 16 bit timer mode control register n TMCn do not specify CRn0 as a capture register 3 When both the rising edge and falling edge are specified for the TIn0 valid edge the capture operation does not work 4 For the capture trigger a pulse longer than twice...

Page 265: ...erse timer output F F LVSn LVRn Sets status of timer output F F of timer n 0 0 Not affected 0 1 Resets timer output F F 0 1 0 Sets timer output F F 1 1 1 Setting prohibited TOCn1 Controls timer output F F on match between CRn0 and TMn or valid edge of TIn0 0 Disables reverse timer output F F 1 Enables reverse timer output F F TOEn Controls output of timer n 0 Disables output output is fixed to 0 l...

Page 266: ...0 ES001 ES000 0 0 PRM01 PRM00 ES011 ES010 Selects valid edge of TI01 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES001 ES000 Selects valid edge of TI00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Count clock selection f PRM02 PRM01 PRM00 Count clock 20 MHz 18 87 MHz 16 MHz 0 0 0 f 2 100 ns 0 5 ns 125 ns 0 0...

Page 267: ...ways stop the timer operation 3 If the 16 bit timer TM0 operation is enabled by specifying the rising edge or both edges as the valid edge of the TI00 pin while the TI00 or TI01 pin is high level immediately after system reset the rising edge is detected immediately after the rising edge or both edges is specified Care is therefore needed when pulling up the TI00 or TI01 pin However the rising edg...

Page 268: ...RMn0 ESn11 ESn10 ESn01 ESn00 0 0 PRMn1 PRMn0 n 1 7 ESn11 ESn10 Selects valid edge of TIn1 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ESn01 ESn00 Selects valid edge of TIn0 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Count clock selection f PRMn2 PRMn1 PRMn0 Count clock 20 MHz 18 87 MHz 16 MHz 0 0 0 f 2 100...

Page 269: ... the timer operation 3 If the 16 bit timer TM1 TM7 operation is enabled by specifying the rising edge or both edges as the valid edge of the TIn0 or TIn1 pin while the TIn0 or TIn1 pin is high level immediately after system reset the rising edge is detected immediately after the rising edge or both edges is specified Care is therefore needed when pulling up the TIn0 or TIn1 pin However the rising ...

Page 270: ... FFFFF0F6H 7 6 5 4 3 2 1 0 PRMn0 ESn11 ESn10 ESn01 ESn00 0 0 PRMn1 PRMn0 n 8 10 12 ESn11 ESn10 Selects valid edge of TIn1 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ESn01 ESn00 Selects valid edge of TIn0 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Count clock selection f PRMn2 PRMn1 PRMn0 Count clock 20 MH...

Page 271: ...op the timer operation 3 If the 16 bit timer TM8 TM10 TM12 operation is enabled by specifying the rising edge or both edges for the valid edge of the TIn0 or TIn1 pin while the TIn0 or TIn1 pin is high level immediately after system reset the rising edge is detected immediately after the rising edge or both edges is specified Be careful when pulling up the TIn0 or TIn1 pin However the rising edge ...

Page 272: ...0 PRMn0 ESn11 ESn10 ESn01 ESn00 0 0 PRMn1 PRMn0 n 9 11 ESn11 ESn10 Selects valid edge of TIn1 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ESn01 ESn00 Selects valid edge of TIn0 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Count clock selection f PRMn2 PRMn1 PRMn0 Count clock 20 MHz 18 87 MHz 16 MHz 0 0 0 f 4...

Page 273: ...s stop the timer operation 3 If the 16 bit timer TM9 TM11 operation is enabled by specifying the rising edge or both edges for the valid edge of the TIn0 or TIn1 pin while the TIn0 or TIn1 pin is high level immediately after system reset the rising edge is detected immediately after the rising edge or both edges is specified Be careful when pulling up the TIn0 or TIn1 pin However the rising edge i...

Page 274: ...the 16 bit timer event counter can be selected by bits 0 and 1 PRMn0 and PRMn1 of prescaler mode register n0 PRMn0 and by bits 0 PRMn2 of prescaler mode register n1 PRMn1 Remark n 0 1 7 to 12 Figure 8 2 Control Register Settings When TMn Operates as Interval Timer a 16 bit timer mode control registers 0 1 7 to 12 TMC0 TMC1 TMC7 to TMC12 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 1 0 Clears and star...

Page 275: ...ion of Interval Timer 490 Note The count clock is set by the PRMn0 and PRMn1 registers Remarks 1 indicates the signal that can be directly connected to ports 2 n 0 1 7 to 12 Figure 8 4 Timing of Interval Timer Operation N N t Remarks 1 Interval time N 1 t N 0001H to FFFFH 2 n 0 1 7 to 12 ...

Page 276: ...registers 0 1 7 to 12 TMC0 TMC1 TMC7 to TMC12 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 0 Clears and starts on match between TMn and CRn0 b Capture compare control registers 0 1 7 to 12 CRC0 CRC1 CRC7 to CRC12 CRCn2 CRCn1 CRCn0 CRCn 0 0 0 0 0 0 0 CRn0 as compare register CRn1 as compare register c 16 bit timer output control registers 0 1 7 to 12 TOC0 TOC1 TOC7 to TOC12 OSPTn OSPEn TOCn4 LVSn LVRn...

Page 277: ...bit timer register n TMn Clear circuit Output controller Note The count clock is set by the PRMn0 and PRMn1 registers Remarks 1 indicates a signal that can be directly connected to ports 2 n 0 1 7 to 12 Figure 8 7 PPG Output Operation Timing t 0000H 0000H 0001H 0001H M 1 TOn N M M N 1 N Count clock TMn count value Value loaded to CRn0 Value loaded to CRn1 Clear Count starts Pulse width M t 1 cycle...

Page 278: ...falling or both rising and falling edges can be selected The valid edge is detected through sampling at a count clock cycle selected by prescaler mode registers n0 and n1 PRMn0 PRMn1 and the capture operation is not performed until the valid level is detected two times eliminating noise with a short pulse width Figure 8 8 Control Register Settings for Pulse Width Measurement with Free Running Coun...

Page 279: ...th Free Running Counter 490 Note The count clock is set by the PRMn0 and PRMn1 registers Remarks 1 indicates a signal that can be directly connected to ports 2 n 0 1 7 to 12 Figure 8 10 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with Both Edges Specified OVFn Remark n 0 1 7 to 12 ...

Page 280: ...he rising falling or both rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle selected by prescaler mode registers n0 and n1 PRMn0 PRMn1 and the capture operation is not performed until the valid level is detected two times eliminating noise with a short pulse width Remark n 0 1 7 to 12 Figure 8 11 Control Register Settings for Measurement o...

Page 281: ...e following figure illustrates the operation of the capture register when the capture trigger is input Figure 8 12 CRn1 Capture Operation with Rising Edge Specified Remark n 0 1 7 to 12 Figure 8 13 Timing of Pulse Width Measurement with Free Running Counter with Both Edges Specified Remark n 0 1 7 to 12 ...

Page 282: ...ode registers n0 and n1 PRMn0 PRMn1 and the capture operation is not performed until the valid level is detected two times eliminating noise with a short pulse width Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges capture compare register n0 CRn0 cannot perform a capture operation Remark n 0 1 7 to 12 Figure 8 14 Control Register Settings for Pulse Wi...

Page 283: ...oading the count value of TMn to 16 bit capture compare register n1 CRn1 see Figure 8 17 The edge is specified by bits 4 and 5 ESn00 and ESn01 of prescaler mode register n0 PRMn0 The rising or falling edge can be specified The valid edge is detected through sampling at a count clock cycle selected by prescaler mode registers n0 and n1 PRMn0 PRMn1 and the capture operation is not performed until th...

Page 284: ...0 at edge reverse to valid edge of TIn0 CRn1 as capture register Remarks 1 0 1 When these bits are reset to 0 or set to 1 other functions can be used along with the pulse width measurement function For details refer to 8 1 4 1 16 bit timer mode control registers 0 1 7 to 12 TMC0 TMC1 TMC7 to TMC12 and 2 Capture compare control registers 0 1 7 to 12 CRC0 CRC1 CRC7 to CRC12 2 n 0 1 7 to 12 Figure 8 ...

Page 285: ...is detected through sampling at a count clock cycle of f 2 and the capture operation is not performed until the valid level is detected two times eliminating noise with a short pulse width Remark n 0 1 7 to 12 Figure 8 18 Control Register Settings in External Event Counter Mode a 16 bit timer mode control registers 0 1 7 to 12 TMC0 TMC1 TMC7 to TMC12 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 1 0 C...

Page 286: ...ote The count clock is set by the PRMn0 and PRMn1 registers Remarks 1 indicates a signal that can be directly connected to ports 2 n 0 1 7 to 12 Figure 8 20 Timing of External Event Counter Operation with Rising Edge Specified Caution Read TMn when reading the count value of the external event counter Remark n 0 1 7 to 12 ...

Page 287: ...n 0 1 7 to 12 Figure 8 21 Control Register Settings in Square Wave Output Mode a 16 bit timer mode control registers 0 1 7 to 12 TMC0 TMC1 TMC7 to TMC12 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 0 Clears and starts on match between TMn and CRn0 b Capture compare control registers 0 1 7 to 12 CRC0 CRC1 CRC7 to CRC12 CRCn2 CRCn1 CRCn0 CRCn 0 0 0 0 0 0 1 0 1 1 CRn0 as compare register c 16 bit timer ...

Page 288: ...setting 16 bit timer mode control register n TMCn capture compare control register n CRCn and 16 bit timer output control register n TOCn as shown in Figure 8 23 and by setting bit 6 OSPTn of TOCn by software By setting OSPTn to 1 the 16 bit timer event counter is cleared and started and its output is asserted active at the count value N preset to 16 bit capture compare register n1 CRn1 After that...

Page 289: ...ol registers 0 1 7 to 12 TOC0 TOC1 TOC7 to TOC12 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn output Inverts output on match between TMn and CRn0 Specifies initial value of TOn output F F Inverts output on match between TMn and CRn1 Sets one shot pulse output mode Set to 1 for output Caution Do not set CRn0 and CRn1 to 0000H Remarks 1 0 1 When these bits are reset to...

Page 290: ...s an external trigger The valid edge of the TIn0 pin is specified by bits 4 and 5 ESn00 and ESn01 of prescaler mode register n0 PRMn0 The rising falling or both rising and falling edges can be specified When the valid edge of the TIn0 pin is detected the 16 bit timer event counter is cleared and started and the output is asserted active at the count value N preset to 16 bit capture compare registe...

Page 291: ... bit timer output control registers 0 1 7 to 12 TOC0 TOC1 TOC7 to TOC12 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn output Inverts output on match between TMn and CRn0 Specifies initial value of TOn output F F Inverts output on match between TMn and CRn1 Sets one shot pulse output mode Caution Do not set CRn0 and CRn1 to 0000H Remarks 1 0 1 When these bits are reset...

Page 292: ...V0UD Figure 8 26 Timing of One Shot Pulse Output Operation via External Trigger with Rising Edge Specified 1 Caution 16 bit timer register n starts operating as soon as TMCn2 and TMCn3 are set to values other than 0 0 operation stop mode Remark n 0 1 7 to 12 N M ...

Page 293: ...it capture compare registers n0 and n1 CRn0 CRn1 to a value other than 0000H a 1 pulse count operation is disabled when these registers are used as event counters 3 Setting compare register during timer count operation If the value to which the current value of 16 bit capture compare register n0 CRn0 has been changed is less than the value of 16 bit timer register n TMn TMn continues counting over...

Page 294: ...f prescaler mode register n0 PRMn0 Remark n 0 1 7 to 12 6 Re triggering one shot pulse a One shot pulse output via software When a one shot pulse is being output do not set OSPTn to 1 Do not output the one shot pulse again until the current one shot pulse output ends b One shot pulse output via external trigger If the external trigger occurs while a one shot pulse is being output the 16 bit timer ...

Page 295: ...TMn has overflowed the OVFn flag is set again and the clear becomes invalid Remark n 0 1 7 to 12 8 Conflict operation a If the read period and capture trigger input conflict When 16 bit capture compare registers n0 and n1 CRn0 CRn1 are used as capture registers if the read period and capture trigger input conflict the capture trigger has priority The read data of CRn0 and CRn1 is undefined b If th...

Page 296: ...th rising and falling edges are selected as valid edge of TIn0 If both rising and falling edges are selected as the valid edge of TIn0 a capture operation is not performed c To capture the signals correctly from TIn0 and TIn1 The capture trigger needs a pulse longer than twice the count clock selected by prescaler mode registers n0 and n1 PRMn0 PRMn1 in order to correctly capture the signals from ...

Page 297: ...erefore needed when the TIn0 or TIn1 pin is pulled up However when operation is enabled after being stopped the rising or falling edge is not detected b Sampling clock for noise elimination The sampling clock for noise elimination differs depending on whether the TIn0 valid edge is used as a count clock or a capture trigger The former is sampled by f 2 and the latter is sampled by the count clock ...

Page 298: ... bit resolution Interval timer with 16 bit resolution External event counter with 16 bit resolution Square wave output with 16 bit resolution Figure 8 31 Block Diagram of TM5 and TM6 3 4 4 4 5 4 5 4 4 4 3 6 4 6 490 4 490 Notes 1 The count clock is set by the TCLn register 2 Serial interface clock Remarks 1 is a signal that can be directly connected to ports 2 n 5 6 ...

Page 299: ...TMn is a 16 bit read only register that counts the count pulses The counter is incremented in synchronization with the rising edge of the count clock When the count is read out during operation the count clock input temporarily stops and the count is read at that time In the following cases the count becomes 0000H 1 When RESET is input 2 When TCEn is cleared 3 When TMn and CRn match in the clear s...

Page 300: ... 6 5 4 3 2 1 0 TCL50 0 0 0 0 0 TCL502 TCL501 TCL500 Count clock selection f TCL503 TCL502 TCL501 TCL500 Count clock 20 MHz 18 87 MHz 16 MHz 0 0 0 0 TI5 falling edge 0 0 0 1 TI5 rising edge 0 0 1 0 f 2 100 ns 105 ns 125 ns 0 0 1 1 f 4 200 ns 212 ns 250 ns 0 1 0 0 f 8 400 ns 424 ns 500 ns 0 1 0 1 f 16 800 ns 848 ns 1 µs 0 1 1 0 f 64 3 2 µs 3 4 µs 4 µs 0 1 1 1 f subclock 30 5 µs 30 5 µs 30 5 µs 1 0 0...

Page 301: ...1 0 f 2 100 ns 105 ns 125 ns 0 0 1 1 f 4 200 ns 212 ns 250 ns 0 1 0 0 f 8 400 ns 424 ns 500 ns 0 1 0 1 f 16 800 ns 848 ns 1 µs 0 1 1 0 f 64 3 2 µs 3 4 µs 4 µs 0 1 1 1 f 256 12 8 µs 13 6 µs 16 µs 1 0 0 0 Setting prohibited 1 0 0 1 Setting prohibited 1 0 1 0 f 32 1 6 µs 1 7 µs 2 µs 1 0 1 1 f 128 6 4 µs 6 8 µs 8 µs 1 1 0 0 Setting prohibited 1 1 0 1 Setting prohibited 1 1 1 0 Setting prohibited 1 1 1...

Page 302: ...TMn 2 Selects the operating mode of 16 bit counter n TMn 3 Sets the state of the timer output flip flop 4 Controls the timer flip flop or selects the active level in the PWM free running mode 5 Controls timer output TMCn0 is set by an 8 bit or 1 bit memory manipulation instruction RESET input sets these registers to 04H although the state of the hardware is initialized to 04H 00H is readout when r...

Page 303: ... output flip flop 0 1 0 Set timer output flip flop 1 1 1 Setting prohibited Other than PWM free running mode TMCn06 0 PWM free running mode TMCn06 1 TMCn01 Controls timer F F Selects active level 0 Disable inversion operation Active high 1 Enable inversion operation Active low TOEn0 Timer output control 0 Disable output port mode 1 Enable output Cautions 1 When using the timer output pin TOn set t...

Page 304: ...ount clock can be selected by bits 0 to 2 TCLn0 to TCLn2 of timer clock select register n0 TCLn0 and by bit 0 TCLn3 of timer clock select register n1 TCLn1 n 5 6 Setting method 1 Set each register TCLn0 TCLn1 Selects the count clock CRn Compare value TMCn0 Selects the clear and start mode entered when TMn and CRn match TMCn0 0000xxx0B don t care 2 When TCEn0 1 is set counting starts 3 When the val...

Page 305: ... FUNCTION User s Manual U15109EJ3V0UD 303 Figure 8 32 Timing of Interval Timer Operation 2 2 When CRn 0000H 3 0000H 0000H 0000H 0000H 0000H Remark n 5 6 When CRn FFFFH 0001H FFFEH FFFFH 0000H FFFEH FFFFH 0000H 3 Remark n 5 6 ...

Page 306: ...incremented The edge setting can be selected to be either a rising or falling edge If the total value of TMn and the value of 16 bit compare register n CRn match TMn is cleared to 0 and an interrupt request signal INTTMn is generated INTTMn is generated each time the TMn value matches the CRn value Remark n 5 6 Figure 8 33 Timing of External Event Counter Operation with Rising Edge Specified TIn T...

Page 307: ...MCn0 Clear and start mode entered when TMn and CRn match LVSn0 LVRn0 Setting state of timer output flip flop 1 0 High level output 0 1 Low level output Inversion of timer output flip flop enabled Timer output enabled TOEn0 1 2 When TCEn0 1 is set the counter starts operating 3 If the values of TMn and CRn match the timer output flip flop inverts Also INTTMn is generated and TMn is cleared to 0000H...

Page 308: ...WM mode Remark n 5 6 1 Basic operation of PWM output Setting method 1 Set the port latch and port mode register n to 0 2 Set the active level width to 16 bit compare register n CRn 3 Select the count clock using timer clock select register n0 n1 TCLn0 TCLn1 4 Set the active level to bit 1 TMCn01 of TMCn0 5 If bit 7 TCEn0 of TMCn0 is set to 1 counting starts To stop counting set TCEn0 to 0 PWM outp...

Page 309: ...WM output Figure 8 35 Timing of PWM Output Basic operation active level H 3 7 7 0001H FFFFH 0000H 0001H 0002H FFFFH 0000H 0001H 0002H When CRn 0 3 0001H FFFFH 0000H 0001H 0002H FFFFH 0000H 0001H 0002H When CRn FFFFH 3 7 7 0001H FFFFH 0000H 0001H 0002H FFFFH 0000H 0001H 0002H Remark n 5 6 ...

Page 310: ...r the timer has been started This is because 16 bit counter n TMn is started asynchronously to the count pulse Figure 8 36 Start Timing of Timer n Remark n 5 6 2 TMn readout during timer operation Since reading out TMn during operation occurs while the selected clock is temporarily stopped be sure to select a high or low level waveform that is longer than the selected clock n 5 6 ...

Page 311: ...mer fXX fW 24 fW 25 fW 26 fW 27 fW 28 fW 210 fW 211 fW 29 fXT 4 INTWTN INTWTNI WTNM0 WTNM1 WTNM2 WTNM3 WTNM4 WTNM5 WTNM6 WTNM7 WTNCS0 WTNCS1 WTNCS2 fW Clear Clear Internal bus Watch timer mode control register WTNM Watch timer high speed clock select register WTNHC Watch timer clock select register WTNCS 5 bit counter Selector Selector Selector Selector 11 bit prescaler Remark fXX Main clock frequ...

Page 312: ...terval Time of Interval Timer Interval Time fW 32 768 kHz 24 1 fW 488 µs 25 1 fW 977 µs 26 1 fW 1 95 ms 27 1 fW 3 91 ms 28 1 fW 7 81 ms 29 1 fW 15 6 ms 210 1 fW 31 2 ms 211 1 fW 62 4 ms Remark fW Watch timer clock frequency 9 2 Configuration The watch timer includes the following hardware Table 9 2 Configuration of Watch Timer Item Configuration Counter 5 bits 1 Prescaler 11 bits 1 Control registe...

Page 313: ...nstruction RESET input clears WTNM to 00H After reset 00H R W Address FFFFF360H 7 6 5 4 3 2 1 0 WTNM WTNM7 WTNM6 WTNM5 WTNM4 WTNM3 WTNM2 WTNM1 WTNM0 WTNM6 WTNM5 WTNM4 Selects interval time of prescaler 0 0 0 24 fW 488 µs 0 0 1 25 fW 977 µs 0 1 0 26 fW 1 95 ms 0 1 1 27 fW 3 91 ms 1 0 0 28 fW 7 81 ms 1 0 1 29 fW 15 6 ms 1 1 0 210 fW 31 2 ms 1 1 1 211 fW 62 4 ms WTNM3 WTNM2 Selects interrupt time of ...

Page 314: ...WTNCS This register selects the count clock of the watch timer WTNCS is set using an 8 bit memory manipulation instruction RESET input clears WTNCS to 00H Caution Do not change the contents of the WTNM WTNHC and WTNCS registers interval time interrupt time for watch timer count clock during a watch timer operation After reset 00H R W Address FFFFF364H 7 6 5 4 3 2 1 0 WTNCS 0 0 0 0 0 0 WTNCS1 WTNCS...

Page 315: ...d when bits 0 WTNM0 and 1 WTNM1 of the watch timer mode control register WTNM are set to 1 When these bits are cleared to 0 the 11 bit prescaler and 5 bit counter are cleared and the watch timer stops the count operation Setting the WTNM1 bit to 0 can clear the 5 bit counter of the watch timer An error of up to 15 6 ms may occur at this time Setting the WTNM0 bit to 0 can clear the interval timer ...

Page 316: ...Time fW 32 768 kHz 0 0 0 24 1 fW 488 µs 0 0 1 25 1 fW 977 µs 0 1 0 26 1 fW 1 95 ms 0 1 1 27 1 fW 3 91 ms 1 0 0 28 1 fW 7 81 ms 1 0 1 29 1 fW 15 6 ms 1 1 0 210 1 fW 31 2 ms 1 1 1 211 1 fW 62 4 ms Remark fW Watch timer clock frequency Figure 9 2 Operation Timing of Watch Timer Interval Timer Start 5 bit counter Overflow Overflow 0H Interrupt time of watch timer 0 5 s Interrupt time of watch timer 0 ...

Page 317: ...interrupt request INTWTN after operation is enabled WTNM1 and WTNM0 bits of WTNM register 1 Figure 9 3 Watch Timer Interrupt Request INTWTN Generation Interrupt Period 0 5 s It takes 0 515625 s to generate the first INTWTN 2 9 1 32 768 0 015625 s longer INTWTN is then generated every 0 5 s 0 5 s 0 5 s 0 515625 s WTNM0 WTNM1 INTWTN ...

Page 318: ...the watchdog timer mode or the interval timer mode Figure 10 1 Block Diagram of Watchdog Timer Internal bus OSTS0 OSTS1 OSTS2 OSTS WDTM4 WDTM3 RUN WDTM WDCS WDCS0 WDCS1 WDCS2 3 Internal reset signal INTWDTNote 1 INTWDTMNote 2 3 Output controller Output controller Prescaler Selector fXX 224 fXX 212 fXX 222 fXX 221 fXX 220 fXX 219 fXX 218 fXX 217 fXX 216 RUN Clear Selector OSC Notes 1 In watchdog ti...

Page 319: ... ms 219 fXX 26 2 ms 27 8 ms 32 8 ms 220 fXX 52 4 ms 55 6 ms 65 5 ms 221 fXX 104 9 ms 111 1 ms 131 1 ms 222 fXX 209 7 ms 222 3 ms 262 1 ms 224 fXX 838 9 ms 889 1 ms 1 05 s 2 Interval timer mode Interrupts are generated at a preset time interval Table 10 2 Interval Time of Interval Timer Interval Time Clock fXX 20 MHz fXX 18 87 MHz fXX 16 MHz 216 fXX 3 3 ms 3 5 ms 4 1 ms 217 fXX 6 6 ms 6 9 ms 8 2 ms...

Page 320: ... Watchdog timer mode register WDTM 1 Oscillation stabilization time select register OSTS This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until the oscillation is stable OSTS is set by an 8 bit memory manipulation instruction RESET input sets OSTS to 01H After reset 01H R W Address FFFFF380H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OS...

Page 321: ...Address FFFFF382H 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 Watchdog timer interval timer overflow time fXX WDCS2 WDCS1 WDCS0 Clock 20 MHz 18 87 MHz 16 MHz 0 0 0 216 fXX 3 3 ms 3 5 ms 4 1 ms 0 0 1 217 fXX 6 6 ms 6 9 ms 8 2 ms 0 1 0 218 fXX 13 1 ms 13 9 ms 16 4 ms 0 1 1 219 fXX 26 2 ms 27 8 ms 32 8 ms 1 0 0 220 fXX 52 4 ms 55 6 ms 65 5 ms 1 0 1 221 fXX 104 9 ms 111 1 ms 131 1 ms 1 1 0 222 fX...

Page 322: ...ection for the watchdog timerNote 2 0 Interval timer mode If an overflow occurs the maskable interrupt INTWDTM is generated 1 Watchdog timer mode 1 If an overflow occurs the non maskable interrupt INTWDT is generated WDTM3 Internal reset signal generation selectionNote 2 0 Internal reset signal not generated when overflow 1 Internal reset signal generated when overflow Notes 1 Once RUN is set 1 th...

Page 323: ...unning in the IDLE and STOP modes Consequently set RUN to 1 and clear the watchdog timer before entering the IDLE or STOP mode Do not set the watchdog timer when using the HALT mode since the watchdog timer continues to operate in the HALT mode Cautions 1 The actual loop detection time may be up to 2 12 fXX seconds shorter than the set time 2 When the subclock is selected for the CPU clock the wat...

Page 324: ...OP modes Therefore before entering the IDLE STOP mode set the RUN bit of the WDTM register to 1 to clear the interval timer and then set to the IDLE or STOP mode Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 selecting the watchdog timer mode the interval timer mode is not entered as long as RESET is not input 2 The interval time immediately after being set by WDTM may be up to 2 12 fXX seconds s...

Page 325: ...7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fXX OSTS2 OSTS1 OSTS0 Clock 20 MHz 18 87 MHz 16 MHz 0 0 0 216 fXX 3 3 ms 3 5 ms 4 1 ms 0 0 1 218 fXX after reset 13 1 ms 13 9 ms 16 4 ms 0 1 0 219 fXX 26 2 ms 27 8 ms 32 8 ms 0 1 1 220 fXX 52 4 ms 55 6 ms 65 5 ms 1 0 0 221 fXX 104 9 ms 111 1 ms 131 1 ms Other than above Setting prohibited Caution The wait tim...

Page 326: ...3 Wire Serial I O CSI0 CSI2 CSI3 8 Bits CSIn n 0 2 3 has the following two modes 1 Operation stopped mode This mode is used when serial transfers are not performed 2 3 wire serial I O mode fixed as MSB first This is an 8 bit data transfer mode using three lines a serial clock line SCKn a serial output line SOn and a serial input line SIn Since data can be transmitted and received simultaneously in...

Page 327: ...below When n 0 3 TM5 output When n 2 TM6 output 1 Serial I O shift register n SIOn SIOn is an 8 bit register that performs parallel serial conversion and serial transmission reception shift operations in synchronization with the serial clock SIOn is set by an 8 bit memory manipulation instruction When bit 7 CSIEn of serial operation mode register n CSIMn is set to 1 a serial operation can be start...

Page 328: ...er n CSISn and serial operation mode register n CSIMn CSISn is used to set the serial clock of serial interface channel n CSISn can be set by an 8 bit memory manipulation instruction n 0 2 3 RESET input sets CSISn to 00H CSIMn is used to enable or disable the serial clock operation modes and specific operations of serial interface channel n CSIMn can be set by an 8 bit or 1 bit memory manipulation...

Page 329: ...utput 0 Transmit receive mode SIOn write Normal output 1 Receive only mode SIOn read Port function SCLn2 SCLn1 SCLn0 Clock selection 0 0 0 External clock input SCKn 0 0 1 at n 0 3 TM5 output at n 2 TM6 output 0 1 0 fXX 8 0 1 1 fXX 16 1 0 0 Setting prohibited 1 0 1 Setting prohibited 1 1 0 fXX 32 1 1 1 fXX 64 Notes 1 The SIn SOn and SCKn pins are used as port function pins when CSIEn 0 SIOn operati...

Page 330: ... stopped mode the SIn SOn and SCKn pins can be used as normal I O port pins a Register settings Operation stopped mode is set via the CSIEn bit of serial operation mode register n CSIMn Figure 11 2 CSIMn Setting Operation Stopped Mode After reset 00H R W Address CSIM0 FFFFF2A2H CSIM2 FFFFF2C2H CSIM3 FFFFF2D2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 2 3 SIOn operation enable disab...

Page 331: ...Ln0 n 0 2 3 SIOn operation enable disable specification CSIEn Shift register operation Serial counter Port 1 Operation enabled Count operation enabled Serial function port function Transfer operation mode flag MODEn Operation mode Transfer start trigger SOn output 0 Transmit receive mode Write to SIOn Normal output 1 Receive only mode Read from SIOn Port function SCLn2 SCLn1 SCLn0 Clock selection ...

Page 332: ...I2 DI1 DI0 INTCSIn Serial clock 1 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 2 3 4 5 6 7 8 Transfer completion Transfer starts in synchronization with the falling edge of the serial clock c Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial I O shift register n SIOn The SIOn operation control bit CSIEn 1 After an 8 bit se...

Page 333: ...ly in 3 wire serial I O mode the processing time for data transfer is reduced The first bit of serial transfer data can be switched between MSB and LSB 3 wire serial I O mode is useful for connection to devices such as peripheral I O that include a clocked serial interface and display controllers 11 3 1 Configuration CSI4 includes the following hardware Table 11 2 Configuration of CSI4 Item Config...

Page 334: ...tion shift operations in synchronization with the serial clock SIO4 is set by a 16 bit memory manipulation instruction When bit 7 CSIE4 of variable length serial control register 4 CSIM4 is set to 1 a serial operation can be started by writing data to or reading data from SIO4 When transmitting data written to SIO4 is output via the serial output SO4 When receiving data is read from the serial inp...

Page 335: ...regardless of whether the first transfer bit is MSB or LSB Any data can be set to the unused higher bits but in this case the data received after a serial transfer operation becomes 0 Figure 11 6 When Transfer Bit Length Other Than 16 Bits Is Set a When transfer bit length is 10 bits and MSB first SI4 SO4 15 10 9 0 Fixed to 0 b When transfer bit length is 12 bits and LSB first SI4 SO4 Fixed to 0 1...

Page 336: ...eset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SIO4 operation enable disable specification CSIE4 Shift register operation Serial counter Port 0 Operation disabled Clear Port functionNote 1 1 Operation enabled Count operation enabled Serial function port functionNote 2 Transfer operation mode flag MODE4 Operation mode Transfer start trigger SO4 output 0 Transmit rec...

Page 337: ...put sets CSIB4 to 00H After reset 00H R W Address FFFFF2E4H 7 6 5 4 3 2 1 0 CSIB4 0 CMODE DMODE DIR BSEL3 BSEL2 BSEL1 BSEL0 CMODE DMODE SCK4 active level SI4 interrupt timing SO4 output timing 0 0 Low level Rising edge of SCK4 Falling edge of SCK4 0 1 Low level Falling edge of SCK4 Rising edge of SCK4 1 0 High level Falling edge of SCK4 Rising edge of SCK4 1 1 High level Rising edge of SCK4 Fallin...

Page 338: ...BRGCN4 is set by an 8 bit memory manipulation instruction RESET input sets BRGCN4 to 00H After reset 00H R W Address FFFFF2E6H 7 6 5 4 3 2 1 0 BRGCN4 0 0 0 0 0 BRGN2 BRGN1 BRGN0 BRGN2 BRGN1 BRGN0 Source clock fSCK n 0 0 0 fXX 0 0 0 1 fXX 2 1 0 1 0 fXX 4 2 0 1 1 fXX 8 3 1 0 0 fXX 16 4 1 0 1 fXX 32 5 1 1 0 fXX 64 6 1 1 1 fXX 128 7 ...

Page 339: ...SCK 252 126 1 1 1 1 1 1 1 fSCK 254 127 The baud rate transmit receive clock that is generated is obtained by dividing the main clock Generation of baud rate transmit receive clock using main clock The transmit receive clock is obtained by dividing the main clock The following equation is used to obtain the baud rate from the main clock When 1 k 127 Baud rate Hz fXX Main clock oscillation frequency...

Page 340: ... SCK4 pins can be used as normal I O port pins a Register settings Operation stopped mode is set via the CSIE4 bit of variable length serial control register 4 CSIM4 When CSIE4 0 SIO4 operation stop state the pins connected to SI4 SO4 or SCK4 function as port pins Figure 11 7 CSIM4 Setting Operation Stopped Mode After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4...

Page 341: ... by the variable length serial control register 4 CSIM4 Figure 11 8 CSIM4 Setting 3 Wire Serial I O Mode After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SIO4 operation enable disable specification CSIE4 Shift register operation Serial counter Port 1 Operation enabled Count operation enabled Serial function port function Transfer operation mode flag MODE4 Oper...

Page 342: ... BSEL2 BSEL1 BSEL0 CMODE DMODE SCK4 active level SI4 interrupt timing SO4 output timing 0 0 Low level Rising edge of SCK4 Falling edge of SCK4 0 1 Low level Falling edge of SCK4 Rising edge of SCK4 1 0 High level Falling edge of SCK4 Rising edge of SCK4 1 1 High level Rising edge of SCK4 Falling edge of SCK4 DIR Serial transfer direction 0 LSB first 1 MSB first BSEL3 BSEL2 BSEL1 BSEL0 Bit length o...

Page 343: ...ed to change the attribute of the serial clock SCK4 and the phases of serial data SI4 and SO4 Figure 11 10 Timing of 3 Wire Serial I O Mode SCK4 CMODE 0 SIO4 Write SO4 DMODE 1 INTCSI4 SCK4 CMODE 1 SO4 DMODE 0 Remark The arrows show the SI4 data fetch timing When CMODE 0 the serial clock SCK4 stops at a high level during the operation stop and outputs a low level during a data transfer operation Wh...

Page 344: ...ied Transmit and transmit receive mode MODE4 0 Transfer starts when writing to SIO4 Receive only mode MODE4 1 Transfer starts when reading from SIO4 Caution After data has been written to SIO4 transfer will not start even if the CSIE4 bit value is set to 1 Completion of the final bit transfer automatically stops the serial transfer operation and sets the interrupt request flag INTCSI4 Figure 11 11...

Page 345: ...rupt sources 1 type Transmission reception completion interrupt INTCSIn Transmit receive mode and receive only mode can be specified Two transmit buffers SOTBFn SOTBFLn SOTBn SOTBLn and two receive buffers SIRBn SIRBLn SIRBEn SIRBELn are provided on chip Single transfer mode and repeat transfer mode can be specified Caution When using P120 SCK5 P121 SI5 and P122 SO5 for CSI5 transmission reception...

Page 346: ...ster n Ln SIRBEn SIRBELn Clocked serial interface transmit buffer register n Ln SOTBn SOTBLn Clocked serial interface initial transmit buffer register SOTBFn SOTBFLn Remark n 5 6 Figure 11 12 Block Diagram of 3 Wire Serial I O CSI5 CSI6 Selector Transmission control SO selection SO latch Transmit buffer register SOTBn SOTBLn Receive buffer register SIRBn SIRBLn Shift register SIOn SIOLn Initial tr...

Page 347: ... parallel data into serial data and is used for both transmission and reception Data is shifted in reception and shifted out transmission from the MSB or LSB side The actual transmit receive operations are started up by accessing the buffer register Remark n 5 6 3 Selector The selector selects the serial clock to be used 4 Serial clock controller The serial clock controller controls the serial clo...

Page 348: ... Ln SIRBEn SIRBELn Clocked serial interface transmit buffer register n Ln SOTBn SOTBLn Clocked serial interface initial transmit buffer register n Ln SOTBFn SOTBFLn 1 Clocked serial interface mode registers 5 6 CSIM5 CSIM6 These registers control CSIn operations n 5 6 CSIMn can be set by an 8 bit or 1 bit memory manipulation instruction RESET input sets these registers to 00H Caution The TRMDn CCL...

Page 349: ...ding the SIRBn register When the TRMDn bit 1 transmission reception is started by writing data to the SOTBn register CCLn Data length specification 0 8 bits 1 16 bits DIRn Transfer direction mode MSB LSB specification 0 First bit of transfer data is MSB 1 First bit of transfer data is LSB CSITn Delay of interrupt request signal control 0 No delay 1 Delay mode interrupt request signal is delayed 1 ...

Page 350: ... CKSn1 CKSn0 n 5 6 CKPn DAPn Operation mode 0 0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 SOn output SCKn I O SIn input DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 SOn output SCKn I O SIn input DI6 DI5 DI4 DI3 DI2 DI1 DI0 1 0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 SOn output SCKn I O SIn input DI6 DI5 DI4 DI3 DI2 DI1 DI0 1 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 SOn output SCKn I O SI...

Page 351: ... read operation only in the idle state CSOTn bit of CSIMn register 0 If the SIRBn register is read during data transfer the data cannot be guaranteed 4 Clocked serial interface receive buffer registers L5 L6 SIRBL5 SIRBL6 The SIRBLn register is an 8 bit buffer register that stores receive data When the receive only mode is set TRMDn bit of CSIMn register 0 reception is started by reading data from...

Page 352: ...eive operation is not started even if data is read from the SIRBEn register 2 The SIRBEn register can be read only if a data length of 16 bits is set CCLn bit of CSIMn register 1 6 Clocked serial interface read only receive buffer registers L5 L6 SIRBEL5 SIRBEL6 The SIRBELn register is an 8 bit buffer register that stores receive data SIRBELn is set by an 8 bit or 1 bit memory manipulation instruc...

Page 353: ... only in the idle state CSOTn bit of CSIMn register 0 If the SOTBn register is accessed during data transfer the data cannot be guaranteed 8 Clocked serial interface transmit buffer registers L5 L6 SOTBL5 SOTBL6 The SOTBLn register is an 8 bit buffer register that stores transmit data When the transmit receive mode is set TRMDn bit of CSIMn register 1 transmission is started by writing data to the...

Page 354: ...r 1 and only in the idle state CSOTn bit of CSIMn register 0 If the SOTBFn register is accessed during data transfer the data cannot be guaranteed 10 Clocked serial interface initial transmit buffer registers L5 L6 SOTBFL5 SOTBFL6 The SOTBFLn register is an 8 bit buffer register that stores the initial transmit data in the repeat transfer mode Transmission is not started even if data is written to...

Page 355: ...d only in the idle state CSOTn bit of CSIMn register 0 If the SIOn register is accessed during data transfer the data cannot be guaranteed 12 Serial I O shift registers L5 L6 SIOL5 SIOL6 The SIOLn register is an 8 bit shift register that converts parallel data into serial data Data is shifted in received or shifted out transmitted starting from MSB or LSB Transfer is not started even if the SIOLn ...

Page 356: ...ister 1 When transfer is started the value of the CSOTn bit of the CSIMn register becomes 1 transmission execution status Upon transfer completion the transmission reception completion interrupt INTCSIn is set 1 and the CSOTn bit is cleared 0 The next data transfer request is then waited for Notes 1 When a data length of 16 bits CCLn bit of CSIMn register 1 has been set read the SIRBn register Whe...

Page 357: ...on mode CKPn bit 0 DAPn bit 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 55H AAH AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn I O SOn output SIn input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSIn interrupt 55H transmit data Write 55H to SOTBLn register Remarks 1 n 5 6 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data b...

Page 358: ...on mode CKPn bit 0 DAPn bit 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn I O SOn output SIn input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSIn interrupt 55H AAH 55H transmit data Write 55H to SOTBLn register Remarks 1 n 5 6 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data b...

Page 359: ...t signal delay control CSITn bit of CSIMn register 0 Figure 11 14 Timing Chart According to Clock Phase Selection 1 2 a When CKPn bit 0 DAPn bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 b When CKPn bit 1 DAPn bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W ...

Page 360: ...O1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 d When CKPn bit 1 DAPn bit 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 Remarks 1 n 5 6 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn wr...

Page 361: ...not 111B The delay mode cannot be set when the slave mode is set bits CKSn2 to CKSn0 111B Figure 11 15 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 a When CKPn bit 0 DAPn bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit Delay Remarks 1 n 5 6 2 Reg_R W Internal signal This signal ...

Page 362: ...en CKPn bit 1 DAPn bit 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit Delay Remarks 1 n 5 6 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed ...

Page 363: ...mission reception completion interrupt request INTCSIn has been set 1 read the SIRBn register Note reserve next transfer 5 Repeat steps 3 and 4 N 2 times N Number of transfer data 6 Following output of the last transmission reception completion interrupt request INTCSIn read the SIRBEn register and the SIOn register Note Note When transferring N number of data receive data is loaded by reading the...

Page 364: ... indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the first transfer Following the transmission reception completion interrupt request INTCSIn transfer is continued if the SIRBn register...

Page 365: ...nterrupt request INTCSIn 5 When the transmission reception completion interrupt request INTCSIn has been set 1 write the next data to the SOTBn register reserve next transfer and read the SIRBn register to load the receive data 6 Repeat steps 4 and 5 as long as data to be sent remains 7 Wait for the INTCSIn interrupt When the interrupt request signal is set 1 read the SIRBn register to load the N ...

Page 366: ...al This signal indicates that the transmit data buffer register SOTBn SOTBLn has been written Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the firs...

Page 367: ...ed within the period shown below Figure 11 18 Timing Chart of Next Transfer Reservation Period 1 2 a When data length is 8 bits operation mode CKPn bit 0 DAPn bit 0 SCKn I O INTCSIn interrupt Reservation period 7 SCKn cycles b When data length is 16 bits operation mode CKPn bit 0 DAPn bit 0 SCKn I O INTCSIn interrupt Reservation period 15 SCKn cycles Remark n 5 6 ...

Page 368: ... Transfer Reservation Period 2 2 c When data length is 8 bits operation mode CKPn bit 0 DAPn bit 1 SCKn I O INTCSIn interrupt Reservation period 6 5 SCKn cycles d When data length is 16 bits operation mode CKPn bit 0 DAPn bit 1 SCKn I O INTCSIn interrupt Reservation period 14 5 SCKn cycles Remark n 5 6 ...

Page 369: ...n transfer request clear and register access Since request cancellation has higher priority the next transfer request is ignored Therefore transfer is interrupted and normal data transfer cannot be performed Figure 11 19 Transfer Request Clear and Register Access Contention SCKn I O INTCSIn interrupt rq_clr Reg_R W Transfer reservation period Remarks 1 n 5 6 2 rq_clr Internal signal Transfer reque...

Page 370: ...r to Figure 11 20 In the transmit receive mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 11 20 Interrupt Request and Register Access Contention SCKn I O INTCSIn interrupt rq_clr Reg_R W Transfer reservation period 0 1 2 3 4 Remarks 1 n 5 6 2 rq_clr Internal signal Transfer request clear signal Reg_R W Internal signal This signal indicates that receive data b...

Page 371: ... output changes 2 SOn pin When CSIn operation is disabled CSIEn bit of CSIMn register 0 the SOn pin output status is as follows n 5 6 Table 11 5 SOn Pin Output Status TRMDn DAPn AUTOn CCLn DIRn SOn Pin Output 0 don t care don t care don t care don t care Fixed at low level 0 don t care don t care don t care SO latch value low level 0 SOTB7 value 0 1 SOTB0 value 0 SOTB15 value 0 1 1 SOTB0 value 0 S...

Page 372: ... bus mode multimasters support This mode is used for 8 bit data transfers with several devices via two lines a serial clock line SCLn and a serial data bus line SDAn This mode complies with the I 2 C bus format and the master device can output start condition data and stop condition data to the slave device via the serial data bus The slave device automatically detects these received data by hardw...

Page 373: ...ister n SVAn Noise eliminator Match signal IIC shift register n IICn SO latch Start condition generator Data hold time correction circuit Acknowledge output circuit Wakeup controller N ch open drain output Acknowledge detector Start condition detector Stop condition detector Serial clock counter Interrupt request signal generator Noise eliminator Serial clock controller Serial clock wait controlle...

Page 374: ...ation example is shown below Figure 11 22 Serial Bus Configuration Example Using I 2 C Bus SDA SCL SDA VDD VDD SCL SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N Master CPU1 Slave CPU1 Address 1 Serial data bus Serial clock Master CPU2 Slave CPU2 Address 2 ...

Page 375: ...on and reception n 0 1 Write and read operations to IICn are used to control the actual transmit and receive operations IICn is set by an 8 bit memory manipulation instruction RESET input sets the IIC0 and IIC1 to 00H 2 Slave address registers 0 and 1 SVA0 SVA1 This register sets local addresses when in slave mode SVAn is set by an 8 bit memory manipulation instruction n 0 1 RESET input sets the S...

Page 376: ...etector start condition detector and ACK detector These circuits are used to output and detect various control signals 11 Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock 12 Start condition generator A start condition is issued when the STTn bit is set However in the communication reservation disabled status IICRS...

Page 377: ...rol registers 0 1 IICC0 IICC1 These registers are used to enable disable I 2 C operations set the wait timing and set other I 2 C operations IICCn can be set by an 8 bit or 1 bit memory manipulation instruction n 0 1 RESET input sets IICCn to 00H Caution In I 2 C0 I 2 C1 bus mode set the port 1 mode register PM1 port 2 mode register PM2 port 1 function register PF1 and port 2 function register PF2...

Page 378: ... locally irrelevant extension code has been received The SCLn and SDAn lines are set for high impedance The following flags are cleared STDn ACKDn TRCn COIn EXCn MSTSn STTn SPTn The standby mode following exit from communications remains in effect until the following communication entry conditions are met After a stop condition is detected restart is in master mode An address match or extension co...

Page 379: ...ave mode After input of eight clocks the clock is set to low level and wait is set for master device 1 Interrupt request is generated at the ninth clock s falling edge Master mode After output of nine clocks clock output is set to low level and wait is set Slave mode After input of nine clocks the clock is set to low level and wait is set for master device This bit s setting is invalid during an a...

Page 380: ...erates a start condition If the communication reservation function is disabled IICRSVn 1 The STCFn bit is set This trigger does not generate a start condition In the wait state when master device Generates a restart condition after releasing the wait Cautions concerning set timing For master reception Cannot be set during transfer Can be set only when ACKEn has been set to 0 and slave has been not...

Page 381: ...the wait period that follows output of eight clocks note that a stop condition will be generated during the high level period of the ninth clock When a ninth clock must be output WTIMn should be changed from 0 to 1 during the wait period following output of eight clocks and SPTn should be set during the wait period that follows output of the ninth clock Condition for clearing SPTn 0 Condition for ...

Page 382: ...for setting MSTSn 1 When a stop condition is detected When ALDn 1 Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is generated ALDn Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a win 1 This status indicates the arbitration result was a loss MSTSn is cleared Condition for cleari...

Page 383: ...receive status 0 Receive status other than transmit status The SDAn line is set for high impedance 1 Transmit status The value in the SO latch is enabled for output to the SDAn line valid starting at the falling edge of the first byte s ninth clock Condition for clearing TRCn 0 Condition for setting TRCn 1 When a stop condition is detected Cleared by LRELn 1 When IICEn changes from 1 to 0 Cleared ...

Page 384: ...for clearing STDn 0 Condition for setting STDn 1 When a stop condition is detected At the rising edge of the next byte s first clock following address transfer Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is detected SPDn Detection of stop condition 0 Stop condition was not detected 1 Stop condition was detected The master device s communication is t...

Page 385: ...ration is enabled IICEn 1 IICFn can be read 1 2 After reset 00H R WNote Address FFFFF368H FFFFF36AH 7 6 5 4 3 2 1 0 IICFn STCFn IICBSYn 0 0 0 0 STCENn IICRSVn n 0 1 STCFn STTn clear flag 0 Start condition issued 1 STTn flag cleared Condition for clearing STCFn 0 Condition for setting STCFn 1 Cleared by STTn 1 When RESET is input Clearance of STTn when communication reservation disabled IICRSVn 1 I...

Page 386: ...ction disable bit 0 Communication reservation enabled 1 Communication reservation disabled Condition for clearing IICRSVn 0 Condition for setting IICRSVn 1 Clearing by instruction When RESET is input Setting by instruction Cautions 1 Write STCENn and IICRSVn only when operation is stopped IICEn 0 2 When STCENn 1 the bus released status IICBSYn 0 is recognized regardless of the actual bus status im...

Page 387: ...0 CLXn n 0 1 After reset 00H R WNote Address FFFFF344H FFFFF354H 7 6 5 4 3 2 1 0 IICCLn 0 0 CLDn DADn SMCn DFCn CLn1 CLn0 n 0 1 CLDn Detection of SCLn line level valid only when IICEn 1 0 SCLn line was detected at low level 1 SCLn line was detected at high level Condition for clearing CLDn 0 Condition for setting CLDn 1 When the SCLn line is at low level When IICEn 0 When RESET is input When the S...

Page 388: ... x x 0 1 0 x fXX 24 4 0 MHz to 8 38 MHz x x 0 1 1 0 fXX 48 8 0 MHz to 16 67 MHz 0 1 0 1 1 1 fXX 36 12 0 MHz to 13 4 MHz 1 0 0 1 1 1 fXX 54 16 0 MHz to 20 0 MHz n 0 TM5 output 18 TM5 setting 0 0 0 1 1 1 n 1 TM6 output 18 TM6 setting High speed mode x x 0 0 0 0 fXX 44 4 0 MHz to 4 19 MHz x x 0 0 0 1 fXX 86 4 19 MHz to 8 38 MHz x x 0 0 1 0 fXX 172 8 38 MHz to 16 67 MHz 0 1 0 0 1 1 fXX 132 12 0 MHz to...

Page 389: ...lowing expression fSCL 1 198 50 ns 200 ns 50 ns 98 5 kHz m T tR tF m 2 T tF tR m 2 T SCLn SCLn inversion SCLn inversion SCLn inversion 5 IIC shift registers 0 1 IIC0 IIC1 IICn is used for serial transmission reception shift operations synchronized with the serial clock It can be read from or written to in 8 bit units but data should not be written to IICn during a data transfer n 0 1 After reset 0...

Page 390: ...slave devices Input is Schmitt input SDAn This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since outputs from the serial clock line and the serial data bus line are N ch open drain outputs an external pull up resistor is required Figure 11 23 Pin Configuration Diagram PORTVDD SCLn SDAn SCLn SDAn PORTVDD...

Page 391: ...device normally it is output by the device that receives 8 bit data The serial clock SCLn is continuously output by the master device However in the slave device the SCLn s low level period can be extended and a wait can be inserted n 0 1 1 Start condition A start condition is met when the SCLn pin is high level and the SDAn pin changes from high level to low level The start conditions for the SCL...

Page 392: ...lave address register n SVAn If the address data matches the SVAn values the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition n 0 1 Figure 11 26 Address Address SCLn 1 SDAn INTIICn Note 2 3 4 5 6 7 8 9 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R W Note INTIICn is generated if a local address or extension code is received durin...

Page 393: ...indicates that the master device is transmitting data to a slave device When the transfer direction specification bit has a value of 1 it indicates that the master device is receiving data from a slave device Figure 11 27 Transfer Direction Specification SCLn 1 SDAn INTIICn 2 3 4 5 6 7 8 9 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R W Transfer direction specification Note Note INTIICn is generated if a local ad...

Page 394: ...a bits causes bit 3 TRCn of IIC status register n IICSn to be set When this TRCn bit s value is 0 it indicates receive mode Therefore ACKEn should be set to 1 n 0 1 When the slave device is receiving when TRCn 0 if the slave device does not need to receive any more data after receiving several bytes setting ACKEn to 0 will prevent the master device from starting transmission of the subsequent data...

Page 395: ...ter device outputs to the slave device when serial transfer has been completed The slave device includes hardware that detects stop conditions Figure 11 29 Stop Condition H SCLn SDAn Remark n 0 1 A stop condition is generated when bit 0 SPTn of IIC control register n IICCn is set to 1 When the stop condition is detected bit 0 SPDn of IIC status register n IICSn is set to 1 and INTIICn is generated...

Page 396: ...for both the master and slave devices the next data transfer can begin n 0 1 Figure 11 30 Wait Signal 1 2 1 When master device has a nine clock wait and slave device has an eight clock wait master transmission slave reception and ACKEn 1 SCLn 6 SDAn 7 8 9 1 2 3 SCLn IICn 6 H 7 8 1 2 3 D2 D1 D0 ACK D7 D6 D5 9 IICn SCLn ACKEn Master Master returns to high impedance but slave is in wait state low lev...

Page 397: ...ing to previously set ACKEn value Transfer lines Remarks 1 ACKEn Bit 2 of IIC control register n IICCn WRELn Bit 5 of IIC control register n IICCn 2 n 0 1 A wait may be automatically generated depending on the setting of bit 3 WTIMn of IIC control register n IICCn n 0 1 Normally when bit 5 WRELn of IICCn is set to 1 or when FFH is written to IIC shift register n IICn on the receiving side the wait...

Page 398: ...a Data Stop normal transmission reception 1 When WTIMn 0 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXX000B 3 IICSn 10XXX000B WTIMn 1 4 IICSn 10XXXX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 10XXX110B 2 IICSn 10XXX10...

Page 399: ...000B WTIMn 1 3 IICSn 10XXXX00B WTIMn 0 4 IICSn 10XXX110B WTIMn 0 5 IICSn 10XXX000B WTIMn 1 6 IICSn 10XXXX00B 7 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 STTn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXXX00B 3 IICSn 10XXX110B 4 IICSn 10XXXX00B 5 IICSn 00000001B Remark...

Page 400: ... 2 3 4 5 1 IICSn 1010X110B 2 IICSn 1010X000B 3 IICSn 1010X000B WTIMn 1 4 IICSn 1010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1010X110B 2 IICSn 1010X100B 3 IICSn 1010XX00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 ...

Page 401: ...o AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X100B 3 IICSn 0001XX00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0...

Page 402: ...ICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 0001X110B 4 IICSn 0001XX00B 5 IICSn 00000001B Remark Always generated Genera...

Page 403: ...10B 2 IICSn 0001X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 0010X010B 4 IICSn 0010X110B 5 IICSn 0010XX00B 6 IICSn 00000001B Remark Alway...

Page 404: ... AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated G...

Page 405: ... D7 to D0 AK SP 1 2 3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010X100B 4 IICSn 0010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 ...

Page 406: ...10B 2 IICSn 0010X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 0001X110B 5 IICSn 0001XX00B 6 IICSn 00000001B Remark Always generat...

Page 407: ...0010X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 7 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 0010X010B 5 IICSn 0010X110B 6 IICSn 0010XX00B 7 IICSn 00000001B Rema...

Page 408: ...3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 00000X10B 5 IICSn 00000001B Remark Always ge...

Page 409: ...sion of slave address data 1 When WTIMn 0 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn is read during interrupt servicing 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn i...

Page 410: ...is read during interrupt servicing 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0110X010B Example when ALDn is read during interrupt servicing 2 IICSn 0010X110B 3 IICSn 0010X100B 4 IICSn 0010XX00B 5 IICSn 00000001B Remark Always generated G...

Page 411: ...P 1 2 1 IICSn 01000110B Example when ALDn is read during interrupt servicing 2 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 b When arbitration loss occurs during transmission of extension code ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 1 IICSn 0110X010B Example when ALDn is read during interrupt servicing IICCn s LRELn is set to 1 by software 2 IICSn 00000001B ...

Page 412: ...ICSn 10001110B 2 IICSn 01000000B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 1 IICSn 10001110B 2 IICSn 01000100B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 ...

Page 413: ...2 IICSn 01000110B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 2 Extension code ST AD6 to AD0 RW AK D7 to Dn ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 1 IICSn 1000X110B 2 IICSn 0110X010B Example when ALDn is read during interrupt servicing IICCn s LRELn is set to 1 by software 3 IICSn 000000...

Page 414: ...enerated only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 f When arbitration loss occurs due to low level data when attempting to generate a restart condition When WTIMn 1 STTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000XX00B 3 IICSn 01000100B Example when ALDn is read during interrupt servicing 4 IICSn 00000001B Remark Always generated Gener...

Page 415: ... 3 IICSn 01000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 h When arbitration loss occurs due to low level data when attempting to generate a stop condition When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000XX00B 3 IICSn 01000000B Example when ALDn is read during interrupt servicing 4 IICSn 00000001B ...

Page 416: ...IICn nor a wait occurs Remarks 1 The numbers in the table indicate the number of the serial clock s clock signals Interrupt requests and wait control are both synchronized with the falling edge of these clock signals 2 n 0 1 1 During address transmission reception Slave device operation Interrupt and wait timing are determined regardless of the WTIMn bit Master device operation Interrupt and wait ...

Page 417: ...the extension code flag EXCn is set for extension code reception and an interrupt request INTIICn is issued at the falling edge of the eighth clock n 0 1 The local address stored in slave address register n SVAn is not affected 2 If 11110xx0 is set to SVAn by a 10 bit address transfer and 11110xx0 is transferred from the master device the results are as follows Note that INTIICn occurs at the fall...

Page 418: ...IICSn is set via the timing by which the arbitration loss occurred and the SCLn and SDAn lines are both set to high impedance which releases the bus n 0 1 The arbitration loss is detected based on the timing of the next interrupt request the eighth or ninth clock when a stop condition is detected etc and the ALDn 1 setting that has been made by software n 0 1 For details of interrupt request timin...

Page 419: ...rt condition At falling edge of eighth or ninth clock following byte transfer Note 1 Notes 1 When WTIMn bit 3 of IIC control register n IICCn 1 an interrupt request occurs at the falling edge of the ninth clock When WTIMn 0 and the extension code s slave address is received an interrupt request occurs at the falling edge of the eighth clock n 0 1 2 When there is a possibility that arbitration will...

Page 420: ...ion is detected When the bus release is detected when a stop condition is detected writing to IIC shift register n IICn causes the master s address transfer to start At this point IICCn s bit 4 SPIEn should be set n 0 1 When STTn has been set the operation mode as start condition or as communication reservation is determined according to the bus status n 0 1 If the bus has been released A start co...

Page 421: ...us access IICn IIC shift register n STTn Bit 1 of IIC control register n IICCn STDn Bit 1 of IIC status register n IICSn SPDn Bit 0 of IIC status register n IICSn Remark n 0 1 Communication reservations are accepted via the following timing After bit 1 STDn of IIC status register n IICSn is set to 1 a communication reservation can be made by setting bit 1 STTn of IIC control register n IICCn to 1 ...

Page 422: ... MSTSn 0 Communication reservation Note Generate start condition Sets STTn bit communication reservation Secures wait period set by software see Table 11 10 Confirmation of communication reservation Clears user flag IICn write operation Defines that communication reservation is in effect defines and sets user flag to any part of RAM Note The communication reservation operation executes a write to ...

Page 423: ... the start condition was generated or request was rejected check the STCFn flag of the IICFn register The time shown in Table 11 11 is required until the STCFn flag is set after setting STTn 1 Therefore secure the time by software Table 11 11 Wait Time IICCEn1 IICCEn0 CLn1 CLn0 Wait Time 0 0 3 clocks 0 1 3 clocks 1 0 6 clocks 0 0 1 1 3 N 0 1 1 1 6 clocks 1 0 1 1 9 clocks Remarks 1 N TM5 and TM6 ou...

Page 424: ...0UD Figure 11 36 Communication Reservation Flowchart 2 DI EI DI No Yes No Yes IICBSYn 0 SET1 STTn EI STCFn 0 IICn H Set STTn bit Wait time Table 11 11 is secured by software IICn write operation Bus communicating status Wait Master communication stopped Remark n 0 1 ...

Page 425: ...ion and then release the bus before starting the master communication Use the following sequence for generating a stop condition 1 Set IIC clock select register n IICCLn 2 Set IICEn of the IIC control register n IICCn 3 Set SPTn of IICCn 2 When STCENn of IIC flag register n IICFn 1 Immediately after I 2 Cn operation is enabled the bus released status IICBSYn of IICFn register 0 is recognized regar...

Page 426: ... No No Yes Yes Yes Yes Yes Yes Yes INTIICn 1 WTIMn 0 ACKEn 1 INTIICn 1 INTIICn 1 TRCn 1 ACKDn 1 MSTSn 1 Yes No INTIICn 1 INTIICn 1 ACKDn 1 WRELn 1 Start reception Yes stop condition detection Wait Wait time is secured by software see Table 11 10 Yes start condition generation Communication reservation Start IICn write transfer Stop condition detection start condition generation by communication re...

Page 427: ...En 1 WRELn 1 Start reception ACKEn 0 SPTn 1 Generate stop condition No Yes Yes transmit INTIICn 1 No Yes Yes INTIICn 1 No Yes INTIICn 1 No Yes ACKDn 1 No Yes No ACKDn 1 TRCn 1 STCFn 0 End Transfer clock selection IICFn register setting IICCn register initial setting Wait time is secured by software see Table 11 11 Insert wait Start IICn write transfer Stop master communication Master communication...

Page 428: ...H IICEn 1 WRELn 1 Start reception START ACKEn 0 LRELn 1 No Yes No No No No No No Yes No Yes Yes Yes START restart detection Yes Yes WTIMn 0 ACKEn 1 INTIICn 1 Yes INTIICn 1 WTIMn 1 Start IICn write transfer INTIICn 1 EXCn 1 COIn 1 TRCn 1 ACKDn 1 START or STOP Transfer completed Communicate No receive Yes transmit Data processing Data processing End Stop stop condition detection Remark n 0 1 ...

Page 429: ...vice transmits the TRCn bit bit 3 of IIC status register n IICSn which specifies the data transfer direction and then starts serial communication with the slave device The shift operation of IIC bus shift register n IICn is synchronized with the falling edge of the serial clock SCLn The transmit data is transferred to the SO latch and is output MSB first via the SDAn pin Data input via the SDAn pi...

Page 430: ...H H L L L L H H H L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4 D5 D6 D7 IICn address IICn data IICn FFH Transmit Start condition Receive When EXC 1 Note Note Note To cancel slave wait write...

Page 431: ...L L L L L H H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 9 8 2 3 4 5 6 7 8 9 3 2 1 D7 D0 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 IICn data IICn FFH Note IICn FFH Note IICn data Transmit Receive Note Note Note To cancel slave wait write FFH to IICn ...

Page 432: ... ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IICn data IICn address IICn FFH Note IICn FFH Note Stop condition Start condition Transmit Note Note When SPIEn 1 Receive When SPIEn 1 Note To cancel slave ...

Page 433: ... SPDn WTIMn H H L L H H L ACKEn MSTSn STTn L L SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 5 6 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R D4 D3 D2 D5 D6 D7 IICn address IICn FFH Note Note IICn data Start condition Note To cancel master wait write FFH to IICn ...

Page 434: ... L L L H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 8 9 2 3 4 5 6 7 8 9 3 2 1 D7 D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5 D6 D7 Note Note Receive Transmit IICn data IICn data IICn FFH Note IICn FFH Note Note To cancel master wait write FFH to I...

Page 435: ...H L L L H H ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IICn address IICn FFH Note Note IICn data Stop condition Start condition When SPIEn 1 N ACK When SPIEn 1 Note To cancel master wait write FFH to ...

Page 436: ...n addition a baud rate based on divided clock input to the ASCKn pin can also be defined The UARTn baud rate generator can also be used to generate a MIDI standard baud rate 31 25 Kbps 11 6 1 Configuration The UARTn includes the following hardware Table 11 12 Configuration of UARTn Item Configuration Registers Transmit shift registers 0 to 3 TXS0 to TXS3 Receive buffer registers 0 to 3 RXB0 to RXB...

Page 437: ...serial data Writing data to TXSn starts the transmit operation TXSn is written by an 8 bit memory manipulation instruction It cannot be read RESET input sets these registers to FFH Caution Do not write to TXSn during a transmit operation 2 Receive shift registers 0 to 3 RX0 to RX3 The RXn register converts serial data input via the RXDn pin to parallel data When one byte of data is received at RXn...

Page 438: ...ve operations based on the values set to asynchronous serial interface mode register n ASIMn During a receive operation it performs error checking such as for parity errors and sets various values to asynchronous serial interface status register n ASISn according to the type of error that is detected 11 6 2 UARTn control registers UARTn is controlled by the following registers n 0 to 3 Asynchronou...

Page 439: ...nsmit only Port function Serial function 1 1 UARTn mode transmit and receive Serial function Serial function PS1n PS0n Parity bit specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity UCLn Character length specification 0 7 bits 1 8 bits SLn Stop bit length specification for transm...

Page 440: ...lag 0 No parity error 1 Parity error Transmit data parity does not match FEn Framing error flag 0 No framing error 1 Framing errorNote 1 Stop bit not detected OVEn Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if the stop bit length has been set as two bits by setting bit 2 SLn of asyn...

Page 441: ...prohibited 0 0 0 0 1 0 0 0 fSCK 8 8 0 0 0 0 1 0 0 1 fSCK 9 9 0 0 0 0 1 0 1 0 fSCK 10 10 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255 Cautions 1 The value of BRGCn becomes 00H after reset Before starting operation select a setting other than Setting prohi...

Page 442: ...n3 TPSn2 TPSn1 TPSn0 8 bit counter source clock selection m 0 0 0 0 External clock ASCKn 0 0 0 1 fXX 0 0 0 1 0 fXX 2 1 0 0 1 1 fXX 4 2 0 1 0 0 fXX 8 3 0 1 0 1 fXX 16 4 0 1 1 0 fXX 32 5 0 1 1 1 at n 0 2 TM6 output at n 1 3 TM5 output 1 0 0 0 fXX 64 6 1 0 0 1 fXX 128 7 1 0 1 0 fXX 256 8 1 0 1 1 fXX 512 9 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Setting prohibited Cautions 1 If BRGMCn0 or n1 is written during...

Page 443: ...ings Operation stopped mode settings are made via bits TXEn and RXEn of asynchronous serial interface mode register n ASIMn Figure 11 43 ASIMn Setting Operation Stopped Mode After reset 00H R W Address ASIM0 FFFFF300H ASIM1 FFFFF310H ASIM2 FFFFF230H ASIM3 FFFFF2B0H 7 6 5 4 3 2 1 0 ASIMn TXEn RXEn PS1n PS0n UCLn SLn ISRMn 0 n 0 to 3 TXEn RXEn Operating mode RXDn Pxx pin function TXDn Pxx pin functi...

Page 444: ... RXDn Pxx pin function TXDn Pxx pin function 0 1 UARTn mode receive only Serial function Port function 1 0 UARTn mode transmit only Port function Serial function 1 1 UARTn mode transmit and receive Serial function Serial function PS1n PS0n Parity bit specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd ...

Page 445: ...raming errorNote 1 Stop bit not detected OVEn Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if the stop bit length has been set as two bits by setting bit 2 SLn in the asynchronous serial interface mode register n ASIMn stop bit detection during a receive operation only applies to a st...

Page 446: ... 0 0 1 0 1 0 fSCK 10 10 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255 Cautions 1 Reset input sets BRGCn to 00H Before starting operation select a setting other than Setting prohibited Selecting Setting prohibited setting in stop mode does not cause any pr...

Page 447: ...lock ASCKn 0 0 0 1 fXX 0 0 0 1 0 fXX 2 1 0 0 1 1 fXX 4 2 0 1 0 0 fXX 8 3 0 1 0 1 fXX 16 4 0 1 1 0 fXX 32 5 0 1 1 1 at n 0 2 TM6 output at n 1 3 TM5 output 1 0 0 0 fXX 64 6 1 0 0 1 fXX 128 7 1 0 1 0 fXX 256 8 1 0 1 1 fXX 512 9 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Setting prohibited Cautions 1 If BRGMCn0 or n1 is written during communication processing the output of the baud rate generator is disturbed a...

Page 448: ...hows the relationship between the main clock and the baud rate and Figure 11 48 shows an example of the allowable baud rate error range Table 11 13 Relationship Between Main Clock and Baud Rate fXX 20 MHz fXX 18 87 MHz fXX 16 MHz Baud Rate bps k m Error k m Error k m Error 32 64 244 9 0 06 128 152 9 0 39 144 9 0 02 244 8 0 06 300 130 8 0 16 123 8 0 12 208 7 0 16 600 130 7 0 16 123 7 0 12 208 6 0 1...

Page 449: ... High speed clock clock cycle T enabling normal reception START D0 D7 P STOP Low speed clock clock cycle T enabling normal reception START D0 D7 P STOP 32T 64T 256T 288T 320T 352T Ideal sampling point 304T 336T 30 45T 60 9T 304 5T 15 5T 15 5T 0 5T Sampling error 33 55T 67 1T 301 95T 335 5T Remark T 8 bit counter s source clock cycle Allowable baud rate error range when k 16 100 4 8438 15 5 320 ...

Page 450: ...6 D7 Start bit Parity bit Stop bit 1 data frame Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Even parity odd parity zero parity or no parity Stop bit s 1 bit or 2 bits When 7 bits is selected as the number of character bits only the lower 7 bits from bit 0 to bit 6 are valid so during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 must be s...

Page 451: ...d including a parity bit and a parity error is generated when the result is an odd number ii Odd parity During transmission The number of bits in transmit data including a parity bit is controlled so that the number of 1 bits is odd The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits The parity bit value is 0 If the transmit data contains an even number ...

Page 452: ...ure 11 50 Timing of Asynchronous Serial Interface Transmission Completion Interrupt TxDn output D0 D1 D2 D6 D7 Parity STOP START INTSTn a Stop bit length 1 TxDn output D0 D1 D2 D6 D7 Parity START INTSTn b Stop bit length 2 STOP Caution Do not write to asynchronous serial interface mode register n ASIMn during a transmit operation Writing to ASIMn during a transmit operation may disable further tra...

Page 453: ...eive buffer register n RXBn and a reception completion interrupt INTSRn occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXBn When an error occurs INSTRn is generated if bit 1 ISRMn of ASIMn is cleared 0 On the other hand INTSRn is not generated if the ISRMn bit is set 1 The receive error type can be ascertained by reading the contents of AS...

Page 454: ...o not match 04H Framing error Stop bit is not detected 02H Overrun error Reception of subsequent data was completed before data was read from the receive buffer register 01H Figure 11 52 Receive Error Timing RxDn input INTSRnNote D7 D6 D2 D1 D0 Parity STOP START Note Even if a receive error occurs when the ISRMn bit of ASIMn is set 1 INTSRn is not generated The receive error type can be ascertaine...

Page 455: ...transmit shift register n TXSn and receive buffer register n RXBn are stopped and their values immediately before the clock stopped are held The TXDn pin output holds the data immediately before the clock is stopped in STOP mode during transmission When the clock is stopped during reception the receive data until the clock stopped is stored and subsequent receive operations are stopped Reception r...

Page 456: ...arted by trigger input ADTRG rising edge falling edge or both rising and falling edges can be specified 2 Software start Conversion is started by setting A D converter mode register 1 ADM1 One analog input channel is selected from ANI0 to ANI11 and A D conversion is performed If A D conversion has been started by a hardware start conversion stops once it has been completed and an interrupt request...

Page 457: ...CGND INTAD 4 ADS3 ADS2 ADS1 ADS0 ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS Selector Sample hold circuit ADCGND Voltage comparator Tap selector ADTRG Edge detector Controller A D conversion result register ADCR Trigger enable Analog input channel specification register ADS A D converter mode register 1 ADM1 Internal bus IEAD A D converter mode register 2 ADM2 Successive approximation register SAR ADCVDD ...

Page 458: ... of the conversion is loaded to this register from the successive approximation register The higher 10 bits of this register hold the result of the A D conversion the lower 6 bits are fixed to 0 This register is read using a 16 bit memory manipulation instruction RESET input sets ADCR to 0000H When using only higher 8 bits of the result of the A D conversion ADCRH is read using an 8 bit memory man...

Page 459: ...exceed the rated values If a voltage higher than ADCVDD or lower than ADCGND even within the range of the absolute maximum ratings is input to a channel the conversion value of the channel is undefined and the conversion values of the other channels may also be affected 7 ADCGND pin This is the ground pin of the A D converter Always make the potential at this pin the same as that at the GND0 pin e...

Page 460: ...ister specifies the conversion time of the input analog signal to be converted into a digital signal starting or stopping the conversion and an external trigger ADM1 is set by an 8 bit or 1 bit memory manipulation instruction RESET input sets ADM1 to 00H 1 2 After reset 00H R W Address FFFFF3C0H 7 6 5 4 3 2 1 0 ADM1 ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS ADCS A D conversion control 0 Conversion stopp...

Page 461: ...fXX 30 fXX Setting prohibited Setting prohibited Setting prohibited 1 1 0 0 48 fXX 24 fXX Setting prohibited Setting prohibited Setting prohibited 1 1 0 1 36 fXX 18 fXX Setting prohibited Setting prohibited Setting prohibited 1 1 1 0 Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1 1 1 1 12 fXX 6 fXX Setting prohibited Setting prohibited Setting prohibited EGA1 EGA0 Va...

Page 462: ... 0 ANI0 0 0 0 1 ANI1 0 0 1 0 ANI2 0 0 1 1 ANI3 0 1 0 0 ANI4 0 1 0 1 ANI5 0 1 1 0 ANI6 0 1 1 1 ANI7 1 0 0 0 ANI8 1 0 0 1 ANI9 1 0 1 0 ANI10 1 0 1 1 ANI11 Other than above Setting prohibited Caution Always set bits 7 to 4 to 0 3 A D converter mode register 2 ADM2 This register specifies connection disconnection of ADCVDD and the series resistor string ADM2 is set by a 1 bit or 8 bit memory manipulat...

Page 463: ...If the analog input voltage is less than 1 2 ADCVDD the MSB is reset 6 Next bit 8 of the SAR is automatically set and the analog input voltage is compared again Depending on the value of bit 9 to which the result of the preceding comparison has been set the voltage tap of the series resistor string is selected as follows Bit 9 1 3 4 ADCVDD Bit 9 0 1 4 ADCVDD The analog input voltage is compared wi...

Page 464: ...ersion result Conversion result A D conversion is successively executed until bit 7 ADCS of A D converter mode register 1 ADM1 is reset 0 by software If ADM1 and the analog input channel specification register ADS are written during A D conversion the conversion is initialized If ADCS is set 1 at this time conversion is started from the beginning RESET input sets the A D conversion result register...

Page 465: ...Function that returns integer of value in VIN Analog input voltage ADCVDD A D converter reference voltage ADCR Value of the A D conversion result register ADCR The relationship between the analog input voltage and A D conversion result is shown below Figure 12 3 Relationship Between Analog Input Voltage and A D Conversion Result 1 1 3 2 5 3 2043 1022 20451023 2047 1 2048 102420481024 2048 1024 204...

Page 466: ...A D conversion is executed A D conversion can be started in the following two ways Hardware start Started by trigger input ADTRG rising edge falling edge or both rising and falling edges can be specified Software start Started by setting A D converter mode register 1 ADM1 The result of the A D conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is ...

Page 467: ...een started and completed conversion is not started again unless a new external trigger signal is input If data with ADCS set to 1 is written to ADM during A D conversion the conversion under execution is stopped and the A D converter stands by until a new external trigger signal is input If the external trigger signal is input A D conversion is executed again from the beginning If data with ADCS ...

Page 468: ... is generated Once A D conversion has been started and completed the next conversion is started immediately A D conversion is repeated until new data is written to ADS If ADS is rewritten during A D conversion the conversion under execution is stopped and conversion of the newly selected analog input channel is started If data with ADCS set to 0 is written to ADM1 during A D conversion the convers...

Page 469: ...g the conversion by re setting bit 7 ADCS of A D converter mode register 1 ADM1 to 0 2 Input range of ANI0 to ANI11 Keep the input voltage of the ANI0 through ANI11 pins to within the rated range If a voltage greater than ADCVDD or lower than ADCGND even within the range of the absolute maximum ratings is input to a channel the converted value of the channel becomes undefined Moreover the values o...

Page 470: ... Clamp with diode with a low VF 0 3 V MAX if noise higher than ADCVDD or lower than ADCGND may be generated C 100 to 1000 pF 5 ANI0 to ANI11 The analog input ANI0 to ANI11 pins function alternately as port pins To execute A D conversion with any of ANI0 to ANI11 selected do not execute an instruction that inputs data to the port during conversion otherwise the resolution may drop If a digital puls...

Page 471: ...est flag may be set immediately before ADS is rewritten If ADIF is read immediately after ADS has been rewritten it may be set despite the fact that conversion of the newly selected analog input signal has not been completed yet When stopping A D conversion and then resuming clear ADIF before resuming conversion Figure 12 7 A D Conversion End Interrupt Generation Timing Rewriting ADS ANIn conversi...

Page 472: ...voltage as the VDD0 pin to the ADCVDD pin as shown below Figure 12 8 Handling of ADCVDD Pin VDD0 GND0 ADCVDD ADCGND Main power supply Back up capacitor 8 Reading out A D converter result register ADCR Writing to A D converter mode register 1 ADM1 and the analog input channel specification register ADS may cause the ADCR contents to be undefined Therefore read the conversion result during A D conve...

Page 473: ... After a DMA transfer has occurred a specified number of times DMA transfer completion interrupt INTDMA0 to INTDMA5 requests are output individually from the various channels The priority levels of the DMA channels are fixed as follows for simultaneous generation of multiple DMA transfer requests DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 13 2 Transfer Completion Interrupt Request After a DMA transfer has occu...

Page 474: ...DMA transfer start factor INT signal specified by DMA channel control register n DCHCn and the DMA start factor expansion register DMAS is input When the DMA transfer request signal is acknowledged the CPU generates a DMA transfer acknowledge signal for the channel control block and interface control block after the current CPU processing has finished 2 Channel control block The channel control bl...

Page 475: ...A5 These registers set DMA channel n internal RAM addresses n 0 to 5 Since each product has a different internal RAM capacity the internal RAM areas that are usable for DMA differ depending on the product The internal RAM areas that can be set in the DRAn register for each product are shown below Table 13 1 Internal RAM Area Usable in DMA Product Internal RAM Capacity RAM Size Usable in DMA RAM Ar...

Page 476: ...H or 1000H to 3FFFH n 0 to 5 Figure 13 2 Correspondence Between DRAn Setting Value and Internal RAM xxFFFFFFH xxFF9000H xxFF8FFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral I O area Internal RAM area DRAn setting value 0FFFH 1000H 0000H 3FFFH xxFFC000H xxFFBFFFH 12 KB usable for DMA 4 KB usable for DMA xxFFE000H xxFFDFFFH Caution Do not se...

Page 477: ...d be set for 16 bit transfers These registers can be read written in 8 bit units After reset Undefined R W Address DBC0 FFFFF184H DBC3 FFFFF1B4H DBC1 FFFFF194H DBC4 FFFFF1C4H DBC2 FFFFF1A4H DBC5 FFFFF1D4H 7 6 5 4 3 2 1 0 DBCn BCn7 BCn6 BCn5 BCn4 BCn3 BCn2 BCn1 BCn0 n 0 to 5 Caution Values set to bit 0 are ignored during 16 bit transfers 4 DMA start factor expansion register DMAS This is an 8 bit r...

Page 478: ...ddress count direction control 0 Increment 1 Address is fixed TDIRn Transfer direction control between peripheral I O and internal RAMNote 2 0 From internal RAM to peripheral I O 1 From peripheral I O to internal RAM DSn Control of transfer data size for DMA transferNote 2 0 8 bit transfer 1 16 bit transfer ENn Control of DMA transfer enable disable statusNote 3 0 Disabled 1 Enabled reset to 0 aft...

Page 479: ...e 13 2 shows the DMA start factor settings Cautions 1 If the interrupt that is the DMA start factor is not masked interrupt servicing is performed each time DMA starts To prevent interrupt servicing from being performed mask the interrupt 2 If an interrupt source is generated asynchronously to the internal system clock do not set the interrupt source as a multiple DMA start trigger for example whe...

Page 480: ...IC1 1 0 0 INTCSI3 INTSR1 0 1 INTP6 1 0 INTIE1 setting prohibited for other than V850 SC2 2 x x x 1 1 INTAD 0 0 0 INTCSI6 1 0 0 INTCSI3 INTSR1 0 1 INTST2 1 0 INTIE1 setting prohibited for other than V850 SC2 3 x x x 1 1 INTTM70 0 0 INTST1 0 1 INTCSI4 INTSR0 1 0 INTCSI6 4 x x x 1 1 INTSR2 0 0 INTST3 0 1 INTCSI4 INTSR0 1 0 INTCSI2 INTIIC1 5 x x x 1 1 INTTM6 INTP9 Remarks 1 DMAS2 to DMAS0 Bits 2 to 0 ...

Page 481: ...er borrow occurs DMA transfer processing signal DMA transfer acknowledge signal Processing format Access destination for transfer from internal RAM to peripheral I O Access destination for transfer from peripheral I O to internal RAM CPU processing DMA transfer processing CPU processing Remark n 0 to 5 If two or more DMA transfer requests are generated simultaneously the DMA transfer requests are ...

Page 482: ...e at the same register as the register used in i Remark xx Identifying name of peripheral unit see Table 7 2 n Peripheral unit number see Table 7 2 For example when using the DMA function if an unmasked INTCSI0 interrupt occurs during bit manipulation of the interrupt request flag CSIF0 of the CSIC0 register by the CLR1 instruction INTCSI0 interrupt servicing occurs twice Under such conditions bec...

Page 483: ...is cleared 0 b Interrupt servicing when interrupt servicing occurs twice EI RETI RETI Interrupt request flag xxIFn is cleared 0 Main routine Interrupt servicing routine Interrupt request flag xxIFn is not cleared and remains 1 Bit manipulation instruction to xxIFn Interrupt request Since the interrupt request flag xxIFn remains 1 the interrupt is serviced again Remark xx Identifying name of periph...

Page 484: ...on execution Main routine Interrupt servicing routine Interrupt request flag xxIFn is cleared 0 Bit manipulation instruction to xxIFn Interrupt request d Countermeasure use condition ii EI EI RETI Interrupt request Main routine Interrupt servicing routine Interrupt request flag xxIFn is not cleared 0 and remains 1 Bit manipulation instruction to xxIFn xxIFn is cleared 0 at the start of the interru...

Page 485: ...ialized In addition the main clock stops oscillation during the reset period although the subclock continues oscillation The reset by the watchdog timer is released immediately after reset and the CPU resumes program execution after the oscillation stabilization time has elapsed 2 18 fXX 3 Internal reset by power on clear POC When either of the following conditions is satisfied a system reset is p...

Page 486: ...ge the data in memory devices Likewise make sure the pins are handled so as to prevent such effects at the signal outputs by on chip peripheral I O functions and output ports Figure 14 1 System Reset Timing by RESET Signal Input Hi Z Analog delay Analog delay Analog delay Eliminated as noise Internal system reset signal RESET X1 Reset is accepted Reset is canceled 13 1 ms 20 MHz operation Oscillat...

Page 487: ...ode Normal operation Normal operation reset processing Stop status oscillation stopped Reset period oscillation stopped Oscillation stabilization time wait Power on clear voltage 2 2 V STOP instruction execution Hi Z Hi Z 3 5 V 2 2 V X1 I O port pin Internal reset signal VDD c In normal operating mode including HALT mode Normal operation Normal operation reset processing Reset period oscillation s...

Page 488: ...he VDD0 pin In the case of a reset generated by the RESET pin however the POCM and VM45 bits retain their previous statuses A low voltage state can be detected by reading the POCS register following reset cancellation The POCS register is read only using an 8 bit memory manipulation instruction This register is reset when read After reset RetainedNote R Address FFFFF07AH 7 6 5 4 3 2 1 0 POCS 0 0 0...

Page 489: ...necessary to set the PM176 bit of the port 17 mode register PM17 to 0 output mode or the P176 bit of port 17 P17 to 0 0 output 3 POC control register POCC This register sets whether the 3 5 V power on clear reset detection voltage is enabled disabled However detection of less than 2 5 V in STOP mode cannot be disabled Reset by power on clear when the initial power supply is applied is enabled and ...

Page 490: ... for the power supply corresponding to each pin Figure 15 1 Regulator µ µ µ µPD70F3089Y VDD1 system I O buffer PORTVDD0 system I O buffer 4 0 V to 5 5 V 4 0 V to 5 5 V 3 0 V to 5 5 V 3 0 V to 5 5 V 3 0 V to 5 5 V Internal digital circuit 3 3 V Main Sub oscillator Flash memory A D converter 4 5 V to 5 5 V ADCVDD VDD1 PORTVDD2 VPP PORTVDD1 Regulator VDD0 CPUREG 1 F Recommended PORTVDD0 PORTVDD2 syst...

Page 491: ...0 to 3 Instruction bugs found in the mask ROM can be avoided and program flow can be changed by using the ROM correction function Up to four correction addresses can be specified Cautions 1 The ROM correction function cannot be used for the data in the internal ROM it can only be used for instruction codes If the ROM correction is carried out on data that data will replace the instruction code of ...

Page 492: ... CORENn CORADn register and fetch address match detection control n 0 to 3 0 Match detection disabled 1 Match detection enabled Remark n 0 to 3 16 2 2 Correction request register CORRQ CORRQ saves the channel in which ROM correction occurred The JMP r0 instruction makes the program jump to 00000000H after the correction address matches the fetch address At this time the program can judge the follo...

Page 493: ...ints of the program can be corrected at once since the V850 SC1 V850 SC2 and V850 SC3 have four correction address registers CORADn n 0 to 3 Set 00000000H to 0007FFFEH since the V850 SC1 V850 SC2 and V850 SC3 incorporate a 512 KB ROM Bits 0 and 18 to 31 should be fixed to 0 After reset 00000000H R W Address CORAD0 FFFFF370H CORAD2 FFFFF378H CORAD1 FFFFF374H CORAD3 FFFFF37CH 31 18 17 1 0 CORADn Fix...

Page 494: ... address of the internal RAM that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal ROM Executed by a program stored in the internal ROM Executed by a program stored in the internal RAM Executed by the ROM correction function Caution Check the ROM correction generation from a vector table with a hig...

Page 495: ...nment and the applications using flash memory Software can be altered after the V850 SC1 V850 SC2 and V850 SC3 are solder mounted on the target system Small scale production of various models is made easier by differentiating software Data adjustment in starting mass production is made easier 17 1 Features 4 byte 1 clock access in instruction fetch access All area batch erase area unit erase Commu...

Page 496: ...ash programmer 1 On board programming The contents of the flash memory is rewritten after the V850 SC1 V850 SC2 and V850 SC3 are mounted on the target system Mount connectors etc on the target system to connect the dedicated flash programmer 2 Off board programming Writing to a flash memory is performed by the dedicated program adapter FA Series etc before mounting the V850 SC1 V850 SC2 and V850 S...

Page 497: ...N D G N D V D D G N D VD D V D D G N D 128 143 5 1 22 131 144 102 75 74 73 92 37 72 38 41 40 42 43 48 1 F 44 39 60 Connect to GND Connect to VDD Note µ µ Note The µPD70F3089Y cannot be supplied with the clock from the CLK pin of the flash programmer PG FP3 Supply the clock by creating an oscillator on the flash writing adapter broken line portion An example of the oscillator is shown below Example...

Page 498: ... 44 P12 SCK0 SCL0 44 Unnecessary Unnecessary CLK Note Unused Unnecessary Unnecessary Unnecessary Unnecessary Unnecessary Unnecessary RESET Output Reset signal RESET 40 RESET 40 RESET 40 VPP Output Writing voltage MODE VPP 41 MODE VPP 41 MODE VPP 41 HS Input Handshake signal of CSI0 HS communication P15 SCK4 ASCK0 48 Unnecessary Unnecessary Unnecessary Unnecessary VDD0 39 VDD0 39 VDD0 39 VDD1 128 V...

Page 499: ...cated flash programmer UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850 SC1 V850 SC2 and V850 SC3 to perform writing erasing etc A dedicated program adapter FA Series is required for off board writing 17 4 Communication Mode Communication between the dedicated flash programmer and the V850 SC1 V850 SC2 and V850 SC3 is serial communication performed using ...

Page 500: ...clock Up to 1 MHz MSB first Figure 17 5 Communication with Dedicated Flash Programmer CSI0 HS VPP VDD0 VDD1 PORTVDD0 to PORTVDD2 GND0 to GND2 PORTGND0 PORTGND1 RESET SO0 SI0 SCK0 P15 VPP VDD GND RESET SI SO SCK HS Dedicated flash programmer V850 SC1 V850 SC2 V850 SC3 The dedicated flash programmer outputs the transfer clock and the V850 SC1 V850 SC2 and V850 SC3 operate as a slave When the PG FP3 ...

Page 501: ...nused X1 RESET Output Reset signal RESET SI RxD Input Receive signal SO0 TXD0 SO TxD Output Transmit signal SI0 RXD0 SCK Output Transfer clock SCK0 HS Input Handshake signal of CSI0 HS P15 Note The µPD70F3089Y cannot be supplied with the clock from the CLK pin of the flash programmer PG FP3 Supply the clock by creating an oscillator on the flash writing adapter FA 144GJ UEN For an example of the o...

Page 502: ...e flash memory programming become the same status as that immediately after reset Therefore all the ports become output high impedance status so that pin handling is required when the external device does not acknowledge the output high impedance status 17 5 1 VPP pin In the normal operating mode 0 V is input to VPP pin In the flash memory programming mode a 7 8 V writing voltage is supplied to VP...

Page 503: ... etc 1 Conflict of signals When connecting a dedicated flash programmer output to a serial interface pin input that is connected to another device output conflict of signals occurs To avoid the conflict of signals isolate the connection to the other device or set the other device to the output high impedance status Figure 17 7 Conflict of Signals Serial Interface Input Pin V850 SC1 V850 SC2 V850 S...

Page 504: ...e input signal to the other device is ignored Figure 17 8 Malfunction of Other Device V850 SC1 V850 SC2 V850 SC3 Pin In the flash memory programming mode if the signal the V850 SC1 V850 SC2 and V850 SC3 outputs affects the other device isolate the signal on the other device side Other device Input pin Dedicated flash programmer connection pin V850 SC1 V850 SC2 V850 SC3 Pin In the flash memory prog...

Page 505: ...the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs Therefore isolate the signals on the reset signal generator side Dedicated flash programmer connection pin 17 5 4 Port pins including NMI When the flash memory programming mode is set all the port pins except the pins that communicate with the dedicated flash programmer become output high...

Page 506: ...late flash memory End No Yes End Start 17 6 2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer set the V850 SC1 V850 SC2 and V850 SC3 in the flash memory programming mode When switching modes set the VPP pin before canceling reset When performing on board writing switch modes using a jumper etc Figure 17 11 Flash Memory Programming Mode...

Page 507: ...V850 SC1 V850 SC2 and V850 SC3 perform slave operation MSB first 8 UART0 Communication rate 9600 bps at reset LSB first Other RFU Setting prohibited Caution When UART0 is selected the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the VPP pulse 17 6 4 Communication command The V850 SC1 V850 SC2 and V850 SC3 communicate with the dedic...

Page 508: ...ify check Data write Continuous write command Writes data from the address following the high speed write command executed immediately before and executes verify check Status read out command Acquires the status of operations Oscillating frequency setting command Sets the oscillating frequency Erasure time setting command Sets the erasing time of batch erase Write time setting command Sets the wri...

Page 509: ...its All unit broadcast communication Broadcast communication to all units 3 Effective transfer rate The effective transfer rate is in mode 1 the V850 SC2 does not support modes 0 and 2 of effective transfer rate Mode 1 Approx 17 Kbps Caution Different modes must not be mixed on one IEBus 4 Communication mode Data transfer is executed in a half duplex asynchronous communication mode 5 Access contro...

Page 510: ...and unit FFFH having the lowest priority 18 1 3 Communication mode Although the IEBus has three communication modes each having a different transfer rate the V850 SC2 supports only communication mode 1 The transfer rate and the maximum number of transfer bytes in one communication frame in communication mode 1 are as shown in Table 18 1 Table 18 1 Transfer Rate and Maximum Number of Transfer Bytes...

Page 511: ...ast communication is performed to all the units regardless of the value of the group number 18 1 6 Transfer format of IEBus Figure 18 1 shows the transfer signal format of the IEBus Figure 18 1 IEBus Transfer Signal Format Header Master address field Slave address field Control field Telegraph length field Data field Start bit Broad casting bit Master address bit P Frame format Slave address bit P...

Page 512: ...s field The master address field is output by the master to inform a slave of the master s address The configuration of the master address field is as shown in Figure 18 2 If two or more units start transmitting the broadcast bit at the same time the master address field makes a judgment of arbitration The master address field compares the data it outputs with the data on the bus each time it has ...

Page 513: ...al if its slave address matches and if the slave detects that the parities of both the master address and slave address are even The slave unit judges that the master address or slave address has not been correctly received and does not output the acknowledge signal if the parities are odd At this time the master unit is in the standby monitor status and communication ends During broadcast communi...

Page 514: ...acknowledge signal and starts outputting the telegraph length field Table 18 2 shows the contents of the control bits Table 18 2 Contents of Control Bits Bit 3Note 1 Bit 2 Bit 1 Bit 0 Function 0 0 0 0 Reads slave status 0 0 0 1 Undefined 0 0 1 0 Undefined 0 0 1 1 Reads data and locksNote 2 0 1 0 0 Reads lock address lower 8 bits Note 3 0 1 0 1 Reads lock address higher 4 bits Note 3 0 1 1 0 Reads ...

Page 515: ...lock address lower 8 bits 0 0 0 1 Reads lock address higher 4 bits Moreover units for which lock is not set by the master unit reject acknowledgement and do not output an acknowledge bit when the control data shown in Table 18 4 is acknowledged Table 18 4 Control Field for Unlocked Slave Unit Bit 3 Bit 2 Bit 1 Bit 0 Function 0 1 0 0 Lock address read lower 8 bits 0 1 0 1 Lock address read higher 4...

Page 516: ... 5H 6H 7H Received control data Communication type ALL TRANS Individual communication 1 Broadcast communication 1 Communication target SLVRQ Slave specification 1 No specification 0 Lock status LOCK Locked 1 Unlocked 0 Master unit judgment match with PAR Lock request unit 1 Other 0 Slave transmission enable ENSLVTX Slave reception enable ENSLVRX 0H 3H 4H 5H 6H 7H 0 1 0 don t care 0 don t care 1 1 ...

Page 517: ...nd parity bit are output by the master unit When the slave unit detects that the parity is even it outputs the acknowledge signal and starts outputting the data field During broadcast communication however the slave unit does not output the acknowledge signal If the parity is odd the slave unit judges that the telegraph length bit has not been correctly received does not output the acknowledge sig...

Page 518: ...rom the slave unit or the data exceeds the maximum number of transmit bytes If the data has continuation and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the acknowledge signal the master unit transmits the next data During broadcast communication the slave unit does not output the acknowledge signal and the master unit transfers 1 by...

Page 519: ...cates that the transmit data is not recognized NACK During broadcast communication however the content of the acknowledge bit is ignored a Last acknowledge bit of slave field The last acknowledge bit of the slave field serves as NACK in any of the following cases and transmission is stopped If the parity of the master address bit or slave address bit is incorrect If a timing error error in bit for...

Page 520: ... bit of data field The last acknowledge bit of the data field serves NACK in any of the following cases and transmission is stopped If the parity of the data bit is incorrect Note If a timing error occurs after the proceeding acknowledge bit has been transmitted If the receive data is stored in the IEBus data register DR and no more data can be received Note Note In this case when the communicatio...

Page 521: ...ister DR Bit 2 Meaning 0 Unit is not locked 1 Unit is locked Bit 3 Meaning 0 Fixed to 0 Bit 4Note 3 Meaning 0 Slave transmission is stopped 1 Slave transmission is ready Bit 5 Meaning 0 Fixed to 0 Bit 7 Bit 6 Meaning 0 0 Mode 0 0 1 Mode 1 1 0 Mode 2 1 1 Not used Indicates the highest mode supported by unitNote 4 Notes 1 After reset bit 0 is set to 1 2 The receive buffer size is 1 byte 3 When the V...

Page 522: ...han the one that has locked the unit does not receive broadcast communication A unit is locked or unlocked as follows a Locking If the communication frame is completed without succeeding in transmission or reception of the data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received ACK 0 by the control bit that specifies locki...

Page 523: ...nit is repeated up to the maximum number of transfer bytes without being output 18 1 8 Bit format The format of the bits constituting the communication frame of the IEBus is shown below Figure 18 9 Bit Format of IEBus Logic 1 Logic 0 Preparation period Synchronization period Data period Stop period Preparation period First low level logic 1 period Synchronization period Next high level logic 0 per...

Page 524: ...mparator Conflict detection ACK generation Parity generation error detection TX RX Interrupt controller Interrupt control block INT request CPU interface block Internal registers handler DMA transfer IEBus interface block CLK Bit processing block Field processing block Internal bus R W PSR 8 bits 8 5 8 12 12 12 Internal bus 8 12 1 Hardware configuration and function The IEBus mainly consists of th...

Page 525: ...internal registers refer to 18 3 Internal Registers of IEBus Controller d Bit processing block This block generates and disassembles bit timing and mainly consists of a bit sequence ROM 8 bit preset timer and comparator e Field processing block This block generates each field in the communication frame and mainly consists of a field sequence ROM 4 bit down counter and comparator f IEBus interface ...

Page 526: ...Bus unit address register UAR FFFFF3E4H IEBus slave address register SAR R W FFFFF3E6H IEBus partner address register PAR R 0000H FFFFF3E8H IEBus control data register CDR FFFFF3EAH IEBus telegraph length register DLR 01H FFFFF3ECH IEBus data register DR R W FFFFF3EEH IEBus unit status register USR R FFFFF3F0H IEBus interrupt status register ISR R W 00H FFFFF3F2H IEBus slave status register SSR 41...

Page 527: ...s the master writing to the BCR register including bit manipulation instructions is disabled until either the end of that communication or frame or until communication is stopped by the occurrence of an arbitration loss communication error Master requests cannot therefore be multiplexed However if the IEBus is specified as a slave while a master request is being held pending the BCR can be written...

Page 528: ...est should be resent by software following a loss in arbitration When resending the master request in this case set 1 the MSTRQ flag after securing the required wait period This flag is unable to be set 1 before the end of this wait period INTIE2 interrupt signal Start interrupt generation Forcible reset period Wait period 61 7 s MAX µ MSTRQ flag reset signal 2 When a master request has been sent ...

Page 529: ...enerated and communication continued when the control data of a slave status request is returned even if the ENSLVTX flag is in the reset status e Slave reception enable flag ENSLVRX Bit 3 Set reset conditions Set By software Reset By software Caution If the ENSLVRX flag is reset when the IEBus is busy with other CPU processing NACK will be returned via the acknowledge bit of the control field mak...

Page 530: ...s written to this register If a request 4H to read the lock address lower 8 bits is received from the master the CPU must read the value of this register and write it to the lower 8 bits IEBus data register DR If a request 5H to read the lock address higher 4 bits is received from the master the CPU must read the value of this register and write the data of the higher 4 bits to DR Sets the partner...

Page 531: ...Writes command 1 1 1 1 Writes data Cautions 1 Because the slave unit must judge whether the received data is a command or data it must read the value of this register after completing communication 2 If the master unit sets an undefined value NACK is returned from the slave unit and communication is aborted During broadcast communication however the master unit continues communication without reco...

Page 532: ...r than the unit that sent the lock request ACK returned 5 If 6H control data was received in the locked state from other than the unit that sent the lock request ACK not returned In all of the above cases the acknowledgement of a slave status or lock request will cause the STATUSF flag bit 4 of the ISR register to be set and the status interrupt INTIE2 to be generated The generation timing is at t...

Page 533: ...lave status or lock address request is acknowledged Note that even if the same control data is received while the IEBus is in the locked state the interrupt generation timing for INTIE2 differs depending on whether the master unit 3 or another unit 4 is requesting the locked state Figure 18 13 Timing of INTIE2 Interrupt Generation in Locked State for 4 and 5 INTIE2 IEBus sequence Status interrupt ...

Page 534: ...g it impossible for the written data to be readout as is Only data received via IEBus communication can be readout After reset 01H R W Address FFFFF3EAH 7 6 5 4 3 2 1 0 DLR Bit 7 6 5 4 3 2 1 0 Setting value Number of communication data bytes 0 0 0 0 0 0 0 1 01H 1 byte 0 0 0 0 0 0 1 0 02H 2 bytes 0 0 1 0 0 0 0 0 20H 32 bytes 1 1 1 1 1 1 1 1 FFH 255 bytes 0 0 0 0 0 0 0 0 00H 256 bytes Cautions 1 If ...

Page 535: ...Bus data register value However when the last byte and 32nd byte the last byte of 1 communication frame is stored in the shift register INTIE1 is not issued b When reception unit One byte of the data received by the shift register of the IEBus interface block is stored to this register Each time 1 byte has been correctly received an interrupt INTIE1 is issued When transmit receive data is transfer...

Page 536: ... 6 This flag indicates whether there was a slave request from the master Set reset conditions Set When the IEBus unit has been sent a slave request during individual communication reception when the received slave address and local UAR match during broadcast reception when the higher 4 bits of the received slave address match or the received slave address is FFFH the flag is set by hardware at the...

Page 537: ...ether the unit is performing broadcast communication The contents of the flag are updated in the broadcast field of each frame Except for initialization reset by system reset the set reset conditions vary depending on the receive data of the broadcast field bit Set reset conditions Set When broadcast is received by the broadcast field Reset When individual is received by the broadcast field or upo...

Page 538: ...ion is a slave status request 9 IEBus interrupt status register ISR This register indicates the status when the IEBus issues an interrupt The ISR is read to generate an interrupt after which the specified interrupt servicing is carried out Reset the ISR register after reading it Until it is reset the INTIE2 interrupt signal is not generated nor held pending To reset the ISR register reset each fla...

Page 539: ... does not end after the number of bytes set in the telegraph length field have been transferred 1 Communication ends after the number of bytes set in the telegraph length field have been transferred ENDFRAM Frame end flag 0 The frame transfer of the maximum number of bytes 32 bytes prescribed by mode 1 does not end 1 The frame transfer of the maximum number of bytes 32 bytes prescribed by mode 1 e...

Page 540: ...esting a lock Reset By software c Status transmission flag STATUSF Bit 4 A flag indicating that the transmission status is either the master to slave status or the lock address higher 4 bits lower 8 bits when the IEBus is a slave unit Set reset conditions Set When 0H 4H 5H or 6H is received in the control field from the master when the IEBus is a slave unit Reset By software d Communication end fl...

Page 541: ...in individual communication ACK and NACK are not discriminated in broadcast communication Remark An interrupt is generated if NACK is received in a field other than the data field Underrun Occurrence conditions Occurs during data transmission if there was insufficient time to write the next transmit data to the IEBus data register DR before ACK reception Remark An interrupt is generated if an unde...

Page 542: ...s in the overrun state the cause of the overrun NACK is not returned in the ACK period of the slave address control or telegraph length field the DR register is not updated If the next communication is not to the IEBus unit the DR register is not updated until it is read Because the IEBus unit is not a communication target the data interrupt INTIE1 and communication error interrupt INTIE2 are not ...

Page 543: ...1 mode 1 After reset 41H R Address FFFFF3F2H 7 6 5 4 3 2 1 0 SSR 0 1 0 STATSLV 0 STATLOCK STATRX STATTX STATSLV Slave transmission status flag 0 Slave transmission stops 1 Slave transmission enabled STATLOCK Lock status flag 0 Unlock status 1 Lock status STATRX DR receive status 0 Receiving data not stored in DR 1 Receiving data stored in DR STATTX DR transmit status 0 Transmission data not stored...

Page 544: ...FFFF3F4H 7 6 5 4 3 2 1 0 SCR Bit 7 6 5 4 3 2 1 0 Setting value Remaining number of communication data bytes 0 0 0 0 0 0 0 1 01H 1 byte 0 0 0 0 0 0 1 0 02H 2 bytes 0 0 1 0 0 0 0 0 20H 32 bytes 1 1 1 1 1 1 1 1 FFH 255 bytes 0 0 0 0 0 0 0 0 00H 0 bytes end of communication or 256 bytesNote Note The bit length of the actual hard counter consists of 9 bits When 00H is read it cannot be judged whether t...

Page 545: ...l communication ACK CCR is decremented upon each 1 byte communication regardless of ACK NACK When the count value has reached 00H the frame end flag ENDFRAM of the IEBus interrupt status register ISR is set The maximum number of transfer bytes of the preset value of mode 1 per frame is 20H 32 bytes After reset 20H R Address FFFFF3F6H 7 6 5 4 3 2 1 0 CCR 13 IEBus clock select register IECLK This re...

Page 546: ... of the above interrupt requests are assigned to the interrupt status register ISR For details refer to Table 18 9 Interrupt Source List The configuration of the interrupt control block is illustrated below Figure 18 16 Configuration of Interrupt Control Block IEERR STARTF STATUSF ENDTRNS ENDFRAM STATTX STATRX IEBus macro Interrupt control block V850 SC2 CPU INTIE1 INTIE2 Cautions 1 OR output of S...

Page 547: ...st judgment Contention judgment If loses remaster processing Communication preparation processing Interrupt always occurs if loss in contention occurs for master request Start interrupt Slave Slave address Slave request judgment Communication preparation processing Generated only for slave request Status transmission Slave Control Refer to transmission processing example such as slave status Inter...

Page 548: ... Reception stopped INTIE2 generated NACK returned To start bit wait status Transmission stopped INTIE2 generated To start bit wait status During individual communication Software processing Error processing resend request etc Error processing resend request etc NACK Reception Error Local node status During reception During transmission Occurrence condition Local node NACK transmission NACK recepti...

Page 549: ...processing INTIE2 not generated NACK returned Data reset from other node Remark Data reception is not possible until the overrun status is cancelled Transmission stopped INTIE2 generated To start bit wait status During individual communication Software processing Execute DR read to cancel overrun status Error processing resend request etc Error processing resend request etc Parity Error Local node...

Page 550: ...ode 1 µ µ 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave reception processing See 18 5 1 1 Slave reception processing Judgment of contention result Remaster request processing 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end ...

Page 551: ... received from the slave in the data field an interrupt INTIE1 is not issued to the CPU but the same data is retransmitted by hardware If the transmit data is not written within the period of writing the next data a communication error interrupt occurs due to the occurrence of an underrun and communication ends midway 3 Re communication processing The vector interrupt servicing in 2 in Figure 18 1...

Page 552: ...t Broad casting M address P S address P A Control A P Telegraph length A P Data 1 Approx 390 s mode 1 µ Data 1 P A Data 2 P A Data n 1 P A Data n P A 2 1 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave processing Judgment of collision result Remaster request processing 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error...

Page 553: ...the receive data is not read by the time the next data is received the hardware automatically transmits NACK 2 Frame end processing The vector interrupt servicing in 2 in Figure 18 18 judges whether the data has been correctly received within one frame If the data has not been correctly received if the number of data to be received in one frame could not be received a request to retransmit the dat...

Page 554: ...ment of slave request 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end of frame Frame end processing See 18 5 3 2 Frame end processing Remarks 1 Interrupt INTIE1 occurrence See 18 5 3 1 Interrupt INTIE1 occurrence The transmit data of the second byte and those that follow are written to t...

Page 555: ... writing the next data a communication error interrupt occurs due to the occurrence of an underrun and communication ends abnormally 2 Frame end processing The vector interrupt processing in 2 in Figure 18 19 judges whether the data has been correctly transmitted within one frame If the data has not been correctly transmitted if the number of data to be transmitted in one frame could not be transm...

Page 556: ...occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end of frame Frame end processing See 18 5 4 2 Frame end processing Remarks 1 Interrupt INTIE1 occurrence See 18 5 4 1 Interrupt INTIE1 occurrence The receive data stored in the IEBus data register DR is read by DMA transfer At this time the data transfer direction is SFR peripheral RA...

Page 557: ... the following interrupt does not occur in that communication frame 1 Master transmission Figure 18 21 Master Transmission Interval of Interrupt Occurrence Start bit T t1 T Broad casting Master address T t2 P Slave address T P A A T T t3 Control P A A t4 T A T Telegraph length P A Data P A Communication starts Communication start interrupt P A Data Data A P Data T T t4 End of communication End of ...

Page 558: ...munication End of frame Communication start Communication start interrupt A Remarks 1 T Timing error P Parity error A ACK error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 93 µs Communication starts communication start interrupt t2 Approx 1282 µs Communication start interrupt timing er...

Page 559: ...rt interrupt Status request A Remarks 1 T Timing error P Parity error A ACK error U Underrun error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 96 µs Communication starts communication start interrupt t2 Approx 1192 µs Communication start interrupt timing error t3 Approx 15 µs Communica...

Page 560: ...d of frame Communication start Communication start interrupt P O A P O P A Remarks 1 T Timing error P Parity error A ACK error O Overrun error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 96 µs Communication starts communication start interrupt t2 Approx 1192 µs Communication start inte...

Page 561: ... four patterns is possible for each CAN module Global masks and local masks can be used in common Message configuration Can be declared as transmit message or receive message No of messages 32 messages Message storage method Storage in message buffer with unique ID Storage in buffer specified by receive mask function Remote reception Remote frames can be received in either the receive message buff...

Page 562: ... O bus interface and a means of transmitting and receiving signals 2 MAC Memory Access Controller This functional block controls access to the CAN module within the FCAN and to the CAN RAM 3 CAN module This functional block is involved in the operation of the CAN protocol layer and its related settings 4 CAN RAM This is the CAN memory functional block which is used to store message IDs message dat...

Page 563: ... 2 b Port alternate function control register PAC 2 When the P114 CANTX1 and P116 CANTX2 pins are used as CANTX1 CANTX2 set both the P11 and PM11 registers to 0 refer to 5 3 Using Port Pins as Alternate Function Pins 3 When the P115 CANRX1 and P117 CANRX2 pins are used as CANRX1 and CANRX2 set the P11 register to 0 and the PM11 register to 1 4 If the FCAN register is read written when the external...

Page 564: ...e buffer 14 field xx3FF9E0H to xx3FF9FFH Message buffer 15 field xx3FFA00H to xx3FFA1FH Message buffer 16 field xx3FFA20H to xx3FFA3FH Message buffer 17 field xx3FFA40H to xx3FFA5FH Message buffer 18 field xx3FFA60H to xx3FFA7FH Message buffer 19 field xx3FFA80H to xx3FFA9FH Message buffer 20 field xx3FFAA0H to xx3FFABFH Message buffer 21 field xx3FFAC0H to xx3FFADFH Message buffer 22 field xx3FFA...

Page 565: ... register 01 M_DLC01 xx3FF825H CAN message control register 01 M_CTRL01 xx3FF826H CAN message time stamp register 01 M_TIME01 xx3FF828H CAN message data register 010 M_DATA010 xx3FF829H CAN message data register 011 M_DATA011 xx3FF82AH CAN message data register 012 M_DATA012 xx3FF82BH CAN message data register 013 M_DATA013 xx3FF82CH CAN message data register 014 M_DATA014 xx3FF82DH CAN message da...

Page 566: ...3 M_IDL03 xx3FF872H CAN message ID register H03 M_IDH03 xx3FF874H CAN message configuration register 03 M_CONF03 R W xx3FF875H CAN message status register 03 M_STAT03 R Undefined xx3FF876H CAN status set clear register 03 SC_STAT03 W 0000H xx3FF884H CAN message data length register 04 M_DLC04 xx3FF885H CAN message control register 04 M_CTRL04 xx3FF886H CAN message time stamp register 04 M_TIME04 x...

Page 567: ...er 064 M_DATA064 xx3FF8CDH CAN message data register 065 M_DATA065 xx3FF8CEH CAN message data register 066 M_DATA066 xx3FF8CFH CAN message data register 067 M_DATA067 xx3FF8D0H CAN message ID register L06 M_IDL06 xx3FF8D2H CAN message ID register H06 M_IDH06 xx3FF8D4H CAN message configuration register 06 M_CONF06 R W xx3FF8D5H CAN message status register 06 M_STAT06 R Undefined xx3FF8D6H CAN stat...

Page 568: ...N message data register 090 M_DATA090 xx3FF929H CAN message data register 091 M_DATA091 xx3FF92AH CAN message data register 092 M_DATA092 xx3FF92BH CAN message data register 093 M_DATA093 xx3FF92CH CAN message data register 094 M_DATA094 xx3FF92DH CAN message data register 095 M_DATA095 xx3FF92EH CAN message data register 096 M_DATA096 xx3FF92FH CAN message data register 097 M_DATA097 xx3FF930H CA...

Page 569: ...tus set clear register 11 SC_STAT11 W 0000H xx3FF984H CAN message data length register 12 M_DLC12 xx3FF985H CAN message control register 12 M_CTRL12 xx3FF986H CAN message time stamp register 12 M_TIME12 xx3FF988H CAN message data register 120 M_DATA120 xx3FF989H CAN message data register 121 M_DATA121 xx3FF98AH CAN message data register 122 M_DATA122 xx3FF98BH CAN message data register 123 M_DATA1...

Page 570: ...4 M_IDL14 xx3FF9D2H CAN message ID register H14 M_IDH14 xx3FF9D4H CAN message configuration register 14 M_CONF14 R W xx3FF9D5H CAN message status register 14 M_STAT14 R Undefined xx3FF9D6H CAN status set clear register 14 SC_STAT14 W 0000H xx3FF9E4H CAN message data length register 15 M_DLC15 xx3FF9E5H CAN message control register 15 M_CTRL15 xx3FF9E6H CAN message time stamp register 15 M_TIME15 x...

Page 571: ...er 174 M_DATA174 xx3FFA2DH CAN message data register 175 M_DATA175 xx3FFA2EH CAN message data register 176 M_DATA176 xx3FFA2FH CAN message data register 177 M_DATA177 xx3FFA30H CAN message ID register L17 M_IDL17 xx3FFA32H CAN message ID register H17 M_IDH17 xx3FFA34H CAN message configuration register 17 M_CONF17 R W xx3FFA35H CAN message status register 17 M_STAT17 R Undefined xx3FFA36H CAN stat...

Page 572: ...N message data register 200 M_DATA200 xx3FFA89H CAN message data register 201 M_DATA201 xx3FFA8AH CAN message data register 202 M_DATA202 xx3FFA8BH CAN message data register 203 M_DATA203 xx3FFA8CH CAN message data register 204 M_DATA204 xx3FFA8DH CAN message data register 205 M_DATA205 xx3FFA8EH CAN message data register 206 M_DATA206 xx3FFA8FH CAN message data register 207 M_DATA207 xx3FFA90H CA...

Page 573: ...tus set clear register 22 SC_STAT22 W 0000H xx3FFAE4H CAN message data length register 23 M_DLC23 xx3FFAE5H CAN message control register 23 M_CTRL23 xx3FFAE6H CAN message time stamp register 23 M_TIME23 xx3FFAE8H CAN message data register 230 M_DATA230 xx3FFAE9H CAN message data register 231 M_DATA231 xx3FFAEAH CAN message data register 232 M_DATA232 xx3FFAEBH CAN message data register 233 M_DATA2...

Page 574: ...25 M_IDL25 xx3FFB32H CAN message ID register H25 M_IDH25 xx3FFB34H CAN message configuration register 25 M_CONF25 R W xx3FFB35H CAN message status register 25 M_STAT25 R Undefined xx3FFB36H CAN status set clear register 25 SC_STAT25 W 0000H xx3FFB44H CAN message data length register 26 M_DLC26 xx3FFB45H CAN message control register 26 M_CTRL26 xx3FFB46H CAN message time stamp register 26 M_TIME26 ...

Page 575: ...er 284 M_DATA284 xx3FFB8DH CAN message data register 285 M_DATA285 xx3FFB8EH CAN message data register 286 M_DATA286 xx3FFB8FH CAN message data register 287 M_DATA287 xx3FFB90H CAN message ID register L28 M_IDL28 xx3FFB92H CAN message ID register H28 M_IDH28 xx3FFB94H CAN message configuration register 28 M_CONF28 R W xx3FFB95H CAN message status register 28 M_STAT28 R Undefined xx3FFB96H CAN stat...

Page 576: ...stamp register 31 M_TIME31 xx3FFBE8H CAN message data register 310 M_DATA310 xx3FFBE9H CAN message data register 311 M_DATA311 xx3FFBEAH CAN message data register 312 M_DATA312 xx3FFBEBH CAN message data register 313 M_DATA313 xx3FFBECH CAN message data register 314 M_DATA314 xx3FFBEDH CAN message data register 315 M_DATA315 xx3FFBEEH CAN message data register 316 M_DATA316 xx3FFBEFH CAN message d...

Page 577: ...1BRP R W 0000H xx3FFC5CH CAN1 bus diagnostic information register C1DINF R xx3FFC5EH CAN1 synchronization control register C1SYNC 0218H xx3FFC80H CAN2 address mask 0 register LNote C2MASKL0 xx3FFC82H CAN2 address mask 0 register HNote C2MASKH0 xx3FFC84H CAN2 address mask 1 register LNote C2MASKL1 xx3FFC86H CAN2 address mask 1 register HNote C2MASKH1 xx3FFC88H CAN2 address mask 2 register LNote C2M...

Page 578: ... 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes Other than above 8 bytes regardless of DLC value Note RFU Reserved for Future Use indicates a reserved bit Always set this bit to 0 when writing the M_DLCn register Table 19 3 Addresses of M_DLCn n 00 to 31 Register Name Address Register Name Address M_DLC00 xx3FF804H M_DLC16 xx3FFA04H M_DLC01 xx3FF824H M_DLC17 xx3FFA24H M_DLC02 xx3FF844H M_DLC18 xx3FFA44H ...

Page 579: ...ction set The RMDE0 bit s setting is used only for transmit message buffers When the RTR bit has been set 1 when the receive message or transmit message has a remote frame the RMDE0 bit is processed as RMDE0 0 This prevents transmission of the same remote frame during remote frame reception If the same remote frame is transmitted under the worst conditions the bus load reaches 100 ATS Specifies wh...

Page 580: ...ge buffer when the auto acknowledge function has been set RMDE0 bit 1 An interrupt request occurs when the IE bit is 0 under the following conditions When a remote frame is received by the receive message buffer when the auto acknowledge function has not been set RMDE0 bit 0 MOVR Message buffer overwrite 0 Overwrite does not occur after DN bit is cleared 1 Overwrite occurs at least once after DN b...

Page 581: ...M_CTRL15 xx3FF9E5H M_CTRL31 xx3FFBE5H 19 5 3 CAN message time stamp registers 00 to 31 M_TIME00 to M_TIME31 The M_TIMEn register is the area where the time stamp counter value is written upon completion of data reception n 00 to 31 These registers can be read written in 16 bit units When a data frame or remote frame is received in the receive message buffer the new data is stored in the message bu...

Page 582: ...3FF866H M_TIME19 xx3FFA66H M_TIME04 xx3FF886H M_TIME20 xx3FFA86H M_TIME05 xx3FF8A6H M_TIME21 xx3FFAA6H M_TIME06 xx3FF8C6H M_TIME22 xx3FFAC6H M_TIME07 xx3FF8E6H M_TIME23 xx3FFAE6H M_TIME08 xx3FF906H M_TIME24 xx3FFB06H M_TIME09 xx3FF926H M_TIME25 xx3FFB26H M_TIME10 xx3FF946H M_TIME26 xx3FFB46H M_TIME11 xx3FF966H M_TIME27 xx3FFB66H M_TIME12 xx3FF986H M_TIME28 xx3FFB86H M_TIME13 xx3FF9A6H M_TIME29 xx3...

Page 583: ...the M_DLCn register is less than 8 bytes The values of data bytes that have not been received on the CAN bus may be updated but they are ignored Remark n 00 to 31 x 0 to 7 7 6 5 4 3 2 1 0 Address After reset M_DATAn0 D07 D06 D05 D04 D03 D02 D01 D00 See Table 19 6 Undefined n 00 to 31 7 6 5 4 3 2 1 0 Address After reset M_DATAn1 D17 D16 D15 D14 D13 D12 D11 D10 See Table 19 6 Undefined n 00 to 31 7 ...

Page 584: ...xx3FF9ACH xx3FF9ADH xx3FF9AEH xx3FF9AFH 14 xx3FF9C8H xx3FF9C9H xx3FF9CAH xx3FF9CBH xx3FF9CCH xx3FF9CDH xx3FF9CEH xx3FF9CFH 15 xx3FF9E8H xx3FF9E9H xx3FF9EAH xx3FF9EBH xx3FF9ECH xx3FF9EDH xx3FF9EEH xx3FF9EFH 16 xx3FFA08H xx3FFA09H xx3FFA0AH xx3FFA0BH xx3FFA0CH xx3FFA0DH xx3FFA0EH xx3FFA0FH 17 xx3FFA28H xx3FFA29H xx3FFA2AH xx3FFA2BH xx3FFA2CH xx3FFA2DH xx3FFA2EH xx3FFA2FH 18 xx3FFA48H xx3FFA49H xx3FF...

Page 585: ...econd byte of receive data Note is stored ID1 ID0 Third byte higher two bits of receive data Note is stored Note See 19 5 4 CAN message data registers n0 to n7 M_DATAn0 to M_DATAn7 After reset Undefined R W Address See Table 19 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M_IDHn n 00 to 31 IDE 0 0 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 ID 20 ID 19 ID 18 ID 17 ID 16 15 14 13 12 11 10 9 8 7 6 5 ...

Page 586: ...B0H M_IDH05 xx3FF8B2H M_IDH21 xx3FFAB2H M_IDL06 xx3FF8D0H M_IDL22 xx3FFAD0H M_IDH06 xx3FF8D2H M_IDH22 xx3FFAD2H M_IDL07 xx3FF8F0H M_IDL23 xx3FFAF0H M_IDH07 xx3FF8F2H M_IDH23 xx3FFAF2H M_IDL08 xx3FF910H M_IDL24 xx3FFB10H M_IDH08 xx3FF912H M_IDH24 xx3FFB12H M_IDL09 xx3FF930H M_IDL25 xx3FFB30H M_IDH09 xx3FF932H M_IDH25 xx3FFB32H M_IDL10 xx3FF950H M_IDL26 xx3FFB50H M_IDH10 xx3FF952H M_IDH26 xx3FFB52H ...

Page 587: ...Setting prohibited 1 1 1 Receive message used in diagnostic processing mode When bits MT2 to MT0 have been set as 111 processing can be performed only when the FCAN has been set to diagnostic processing mode In such cases all messages received are stored regardless of the following conditions Storage to other message buffer Identifier type standard frame or extended frame Data frame or remote fram...

Page 588: ...3FF874H M_CONF19 xx3FFA74H M_CONF04 xx3FF894H M_CONF20 xx3FFA94H M_CONF05 xx3FF8B4H M_CONF21 xx3FFAB4H M_CONF06 xx3FF8D4H M_CONF22 xx3FFAD4H M_CONF07 xx3FF8F4H M_CONF23 xx3FFAF4H M_CONF08 xx3FF914H M_CONF24 xx3FFB14H M_CONF09 xx3FF934H M_CONF25 xx3FFB34H M_CONF10 xx3FF954H M_CONF26 xx3FFB54H M_CONF11 xx3FF974H M_CONF27 xx3FFB74H M_CONF12 xx3FF994H M_CONF28 xx3FFB94H M_CONF13 xx3FF9B4H M_CONF29 xx3...

Page 589: ...ndicates that the message buffer has received a remote frame When this message is sent the DN bit is automatically cleared 0 When a frame is again received in the message buffer for which the DN bit has been set 1 an overwrite condition occurs and the M_CTRLn register s MOVR bit is set 1 TRQ Transmit request flag 0 Message transmission prohibited 1 Message transmission enabled A transmit request i...

Page 590: ...3FF875H M_STAT19 xx3FFA75H M_STAT04 xx3FF895H M_STAT20 xx3FFA95H M_STAT05 xx3FF8B5H M_STAT21 xx3FFAB5H M_STAT06 xx3FF8D5H M_STAT22 xx3FFAD5H M_STAT07 xx3FF8F5H M_STAT23 xx3FFAF5H M_STAT08 xx3FF915H M_STAT24 xx3FFB15H M_STAT09 xx3FF935H M_STAT25 xx3FFB35H M_STAT10 xx3FF955H M_STAT26 xx3FFB55H M_STAT11 xx3FF975H M_STAT27 xx3FFB75H M_STAT12 xx3FF995H M_STAT28 xx3FFB95H M_STAT13 xx3FF9B5H M_STAT29 xx3...

Page 591: ...1 0 0 0 0 0 0 clear DN clear TRQ clear RDY set DN clear DN Message update flag setting 0 1 Clear Clear 0 DN bit 1 0 Set Set 1 DN bit Other than above No change in DN bit value set TRQ clear TRQ Transmit request flag setting 0 1 Clear Clear 0 TRQ bit 1 0 Set Set 1 TRQ bit Other than above No change in TRQ bit value set RDY clear RDY Message ready flag setting 0 1 Clear Clear 0 RDY bit 1 0 Set Set 1...

Page 592: ...SC_STAT19 xx3FFA76H SC_STAT04 xx3FF896H SC_STAT20 xx3FFA96H SC_STAT05 xx3FF8B6H SC_STAT21 xx3FFAB6H SC_STAT06 xx3FF8D6H SC_STAT22 xx3FFAD6H SC_STAT07 xx3FF8F6H SC_STAT23 xx3FFAF6H SC_STAT08 xx3FF916H SC_STAT24 xx3FFB16H SC_STAT09 xx3FF936H SC_STAT25 xx3FFB36H SC_STAT10 xx3FF956H SC_STAT26 xx3FFB56H SC_STAT11 xx3FF976H SC_STAT27 xx3FFB76H SC_STAT12 xx3FF996H SC_STAT28 xx3FFB96H SC_STAT13 xx3FF9B6H ...

Page 593: ...Note 1 interrupts GINT2 GINT1 0 Not pending 1 Pending CAN2ERRNote 2 Pending status of CAN2 access error interrupt C2INT6 to C2INT2 0 Not pending 1 Pending CAN2RECNote 2 Pending status of CAN2 receive completion interrupt C2INT1 0 Not pending 1 Pending CAN2TRXNote 2 Pending status of CAN2 transmit completion interrupt C2INT0 0 Not pending 1 Pending CAN1ERR Pending status of CAN1 access error interr...

Page 594: ...e errors that are set only when an interrupt source has occurred for the CAN global interrupt pending register CGINTP 2 µPD703089Y and 70F3089Y only Remark GINT2 GINT1 Bits 2 and 1 of the CAN global interrupt pending register CGINTP CnINT6 to CnINT0 Bits 6 to 0 of the CANn interrupt pending register CnINTP n 1 2 ...

Page 595: ...1 is cleared 0 at the appropriate timing or not is controlled by an interrupt service routine The earlier the interrupt service routine clears 0 the interrupt pending bit the more quickly the interrupt occurs without losing any new interrupts of the same type Remark For details of interrupt sources generated at GINT1 and GINT2 see 19 15 2 Interrupts that occur for global CAN interface After reset ...

Page 596: ...rresponding interrupt request is enabled and when no interrupt pending bit has been set 1 for a new interrupt The interrupt pending bit can be set 1 only when the interrupt ready bit has been set 1 by the CANn interrupt enable register CnIE However the interrupt pending bit is not automatically cleared 0 just because the interrupt enable bit has been cleared 0 Use software processing to clear the ...

Page 597: ...ding CnINT5 Pending status of CAN bus error interrupt 0 Not pending 1 Pending CnINT4 Pending status of wakeup interrupt from CAN sleep mode 0 Not pending 1 Pending CnINT3 Pending status of CAN receive error passive status interrupt 0 Not pending 1 Pending CnINT2 Pending status of CAN transmit error passive or bus off status interrupt 0 Not pending 1 Pending CnINT1 Pending status of CAN receive com...

Page 598: ...he CSTP bit is set 1 undefined value is read and writing is not possible 3 When the CSTP bit is set 1 wakeup from the CAN sleep mode SLEEP bit of CANn control register CnCTRL 1 can be performed in accordance with a change on the CAN bus 4 If the CAN main clock fMEM1 is stopped in other than CAN sleep mode first set the CAN module to initial mode INIT bit of CnCTRL register 1 clear 0 the GOM bit of...

Page 599: ...RR 0 0 0 EFSD TSM 0 GOM b Write 15 14 13 12 11 10 9 8 CGST 0 0 0 0 set EFSD set TSM 0 set GOM 7 6 5 4 3 2 1 0 clear MERR 0 0 0 clear EFSD clear TSM 0 clear GOM a Read MERR MAC error status flag 0 Error does not occur after the MERR bit has been cleared 1 Error occurs at least once after MERR bit has been cleared MAC errors occur under the following conditions When invalid address is accessed When ...

Page 600: ... Access to temporary buffer prohibited if accessed a MAC error interrupt occurs Access to message buffer area enabled The GOM bit is cleared 0 only when all the CAN modules are in the initial mode the INIT bit of the CnCTRL register is 1 Even if the GOM bit is cleared when there is a CAN module not in the initial mode the GOM bit remains set 1 To clear 0 the GOM bit first set 1 the INIT bit of the...

Page 601: ... than above No change in EFSD bit s value set TSM clear TSM TSM bit setting 0 1 TSM bit cleared 0 1 0 TSM bit set 1 Other than above No change in TSM bit s value set GOM clear GOM GOM bit setting 0 1 GOM bit cleared 0 1 0 GOM bit set 1 Other than above No change in GOM bit s value clear MERR MERR bit setting 0 No change in MERR bit s value 1 MERR bit cleared 1 ...

Page 602: ...ress xx3FFC12H a Read 15 14 13 12 11 10 9 8 CGIE 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 G_IE2 G_IE1 0 b Write 15 14 13 12 11 10 9 8 CGIE 0 0 0 0 0 set G_IE2 set G_IE1 0 7 6 5 4 3 2 1 0 0 0 0 0 0 clear G_IE2 clear G_IE1 0 a Read G_IE2 Write access error interrupt enable status for CAN module registerNote when GOM bit is 0 or write access error interrupt enable status for temporary buffer when th...

Page 603: ... 0 0 0 0 0 0 fGTS fGTS1 1 1 0 0 0 0 0 0 0 1 fGTS fGTS1 2 fGTS fGTS1 n 1 127 0 1 1 1 1 1 1 1 fGTS fGTS1 128 after reset fGTS fGTS1 n 1 254 1 1 1 1 1 1 1 0 fGTS fGTS1 255 255 1 1 1 1 1 1 1 1 fGTS fGTS1 256 The global timer system clock fGTS is the source clock for the time stamp counterNote 2 that is used for the time stamp function GTCS1 GTCS0 Global timer clock selection fGTS1 0 0 fMEM 2 0 1 fMEM ...

Page 604: ...er register CnBRP CAN main clock select register CGCS Global timer clock prescaler Baud rate generator Global timer system clock CANn synchronization control register CnSYNC Time stamp counter MCP1 MCP0 BRP0 BRP1 BRP2 BRP3 BRP4 BRP5 BTYPE BRP6Note BRP7Note fMEM1 fMEM fGTS1 fBTL fGTS Note Only when the TLM bit of the CANn bit rate prescaler register CnBRP is 1 Remarks 1 fMEM1 fXX Clock supply to CA...

Page 605: ...counter This register can be read at any time This register can be written to only when clearing bits The clear function writes 0 to all bits in the CGTSC register This register is read only in 16 bit units After reset 0000H R Address xx3FFC18H 15 14 13 12 11 10 9 8 CGTSC TSC15 TSC14 TSC13 TSC12 TSC11 TSC10 TSC9 TSC8 7 6 5 4 3 2 1 0 TSC7 TSC6 TSC5 TSC4 TSC3 TSC2 TSC1 TSC0 ...

Page 606: ...3 2 1 0 0 0 0 STRT4 STRT3 STRT2 STRT1 STRT0 a Read MM Confirmation of multiple hits from message search 0 No messages or only one message meets the search criteria 1 Several messages meet the search criteria If several message buffers that meet the search criteria are detected the MM bit is set AM Confirmation of hits from message search 0 No messages meet the search criteria 1 At least one messag...

Page 607: ...earch module setting 0 0 1 CAN module 1 is set as the searched target 0 1 0 CAN module 2 is set as the searched target Other than above Setting prohibited STRTn Message search start position n 0 to 4 0 to 31 Message search start position message number Search starts from the message number defined by bits STRT4 to STRT0 Search continues until it reaches the message buffer having the highest number...

Page 608: ...ASKLa CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 a 0 to 3 n 1 2 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 CMIDE Mask setting for identifier ID format 0 ID format standard or extended checked 1 ID format standard or extended not checked When the CMIDE bit is set 1 the higher 11 bits of ID are compared The receive message and ID format stored in a message buffer are ...

Page 609: ... Name Address Register Name Address C1MASKL0 xx3FFC40H C2MASKL0 xx3FFC80H C1MASKH0 xx3FFC42H C2MASKH0 xx3FFC82H C1MASKL1 xx3FFC44H C2MASKL1 xx3FFC84H C1MASKH1 xx3FFC46H C2MASKH1 xx3FFC86H C1MASKL2 xx3FFC48H C2MASKL2 xx3FFC88H C1MASKH2 xx3FFC4AH C2MASKH2 xx3FFC8AH C1MASKL3 xx3FFC4CH C2MASKL3 xx3FFC8CH C1MASKH3 xx3FFC4EH C2MASKH3 xx3FFC8EH ...

Page 610: ...e same time 1 4 After reset 0101H R W Addresses C1CTRL xx3FFC50H C2CTRL xx3FFC90H a Read 15 14 13 12 11 10 9 8 CnCTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT n 1 2 7 6 5 4 3 2 1 0 0 DLEVR DLEVT OVM TMR STOP SLEEP INIT b Write 15 14 13 12 11 10 9 8 CnCTRL 0 set DLEVR set DLEVT set OVM set TMR set STOP set SLEEP set INIT n 1 2 7 6 5 4 3 2 1 0 0 clear DLEVR clear DLEVT clear OVM clear TMR clea...

Page 611: ...counter see 19 5 22 CANn error count register CnERC is cleared 0 and the error status TECS1 TECS0 RECS1 or RECS0 bit is reset DLEVR Dominant level control bit for receive pin 0 A low level to a receive pin is acknowledged as dominant 1 A high level to a receive pin is acknowledged as dominant DLEVT Dominant level control bit for transmit pin 0 A low level is transmitted from transmit pin as domina...

Page 612: ...sleep mode is canceled under the following conditions When the CPU has cleared the SLEEP bit 0 When the CAN bus changes this occurs only when CAN stop mode has not been set The WAKE bitNote is set 1 only when CAN sleep mode is cancelled by the change of the CAN bus and an error interrupt occurs To check the settings of the SLEEP bit read the CnCTRL register INIT Initialization request bit 0 Normal...

Page 613: ... setting 0 1 OVM bit cleared 0 1 0 OVM bit set 1 Other than above OVM bit not changed set TMR clear TMR TMR bit setting 0 1 TMR bit cleared 0 1 0 TMR bit set 1 Other than above TMR bit not changed set STOP clear STOP STOP bit setting 0 1 STOP bit cleared 0 1 0 STOP bit set 1 Other than above STOP bit not changed set SLEEP clear SLEEP SLEEP bit setting 0 1 SLEEP bit cleared 0 1 0 SLEEP bit set 1 Ot...

Page 614: ... 7 6 5 4 3 2 1 0 DGM MOM SSHT PBB BERR VALID WAKE OVR b Write 15 14 13 12 11 10 9 8 CnDEF set DGM set MOM set SSHT set PBB 0 0 0 0 n 1 2 7 6 5 4 3 2 1 0 clear DGM clear MOM clear SSHT clear PBB clear BERR clear VALID clear WAKE clear OVR a Read DGM Specification of diagnostic processing mode 0 Valid messages are stored in the message buffer used for diagnostic processing modeNote only when receivi...

Page 615: ...error has occurred due to a transmission it is processed as a transmission error In single shot mode even if the CAN lost in the arbitration phase it is handled as a completed message transmission In this mode the BERR bit is set 1 but the error counter see 19 5 22 CANn error count register CnERC value does not change since there are no CAN bus errors In single shot mode even when transmission is ...

Page 616: ...d an error interrupt occurs While the WAKE bit is set 1 the error interrupt signal holds the active status Therefore always clear 0 the WAKE bit after recognition OVR Overrun error status 0 Normal operation 1 Overwrite occurred during RAM access When an overrun error has occurred the OVR bit is set 1 and an error interrupt occurs at the same time The source of the overrun error may be that the RAM...

Page 617: ...HT clear SSHT SSHT bit setting 0 1 SSHT bit cleared 0 1 0 SSHT bit set 1 Other than above SSHT bit not changed set PBB clear PBB PBB bit setting 0 1 PBB bit cleared 0 1 0 PBB bit set 1 Other than above PBB bit not changed clear BERR BERR bit setting 1 BERR bit cleared 0 0 BERR bit not changed clear VALID VALID bit setting 1 VALID bit cleared 0 0 VALID bit not changed clear WAKE WAKE bit setting 1 ...

Page 618: ...0 LERR3 LERR2 LERR1 LERR0 n 1 2 7 6 5 4 3 2 1 0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 LERR3 LERR2 LERR1 LERR0 Last error information 0 0 0 0 Error not detected 0 0 0 1 Bit error 0 0 1 0 Stuff error 0 0 1 1 CRC error 0 1 0 0 Form error 0 1 0 1 ACK error 0 1 1 0 Arbitration lost only during single shot mode CnDEF SSHT 1 0 1 1 1 CAN overwrite error 1 0 0 0 Wakeup from CAN bus Other than abo...

Page 619: ...x3FFC56H C2ERC xx3FFC96H 15 14 13 12 11 10 9 8 CnERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 n 1 2 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 to REC0 Reception error counter 0 to 255 Number of reception error counts This reflects the current status of the reception error counter The count value is defined by the CAN protocol TEC7 to TEC0 Transmission error counter 0 to 255 Number...

Page 620: ...uration shown in part b Write of the following figure 1 3 After reset 0000H R W Addresses C1IE xx3FFC58H C2IE xx3FFC98H a Read 15 14 13 12 11 10 9 8 CnIE 0 0 0 0 0 0 0 0 n 1 2 7 6 5 4 3 2 1 0 0 E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 b Write 15 14 13 12 11 10 9 8 CnIE 0 set E_INT6 set E_INT5 set E_INT4 set E_INT3 set E_INT2 set E_INT1 set E_INT0 n 1 2 7 6 5 4 3 2 1 0 0 clear E_INT6 clear ...

Page 621: ... interrupt enable flag 0 Interrupt disabled 1 Interrupt enabled When IE bit of the M_CTRLn register is 1 a reception completion interrupt occurs regardless of the setting of the E_INT1 bit if the transmit message buffer receives a remote frame while the auto response function is not set RMDE0 bit of the M_CTRLn register 0 E_INT0 CAN transmit completion interrupt enable flag 0 Interrupt disabled 1 ...

Page 622: ..._INT4 interrupt set 1 Other than above E_INT4 interrupt not changed set E_INT3 clearE_INT3 E_INT3 bit setting 0 1 E_INT3 interrupt cleared 0 1 0 E_INT3 interrupt set 1 Other than above E_INT3 interrupt not changed set E_INT2 clearE_INT2 E_INT2 bit setting 0 1 E_INT2 interrupt cleared 0 1 0 E_INT2 interrupt set 1 Other than above E_INT2 interrupt not changed set E_INT1 clearE_INT1 E_INT1 bit settin...

Page 623: ... 0 Reset state 0 0 0 0 1 Bus idle wait 0 0 0 1 0 Bus idle state 0 0 0 1 1 Start of frame 0 0 1 0 0 Standard identifier area 0 0 1 0 1 Data length code area 0 0 1 1 0 Data field area 0 0 1 1 1 CRC field area 0 1 0 0 0 CRC delimiter 0 1 0 0 1 ACK slot 0 1 0 1 0 ACK delimiter 0 1 0 1 1 End of frame area 0 1 1 0 0 Intermission state 0 1 1 0 1 Suspend transmission 0 1 1 1 0 Error frame 0 1 1 1 1 Error ...

Page 624: ...etermined by the value set to the CnSYNC register While in normal operating mode CnDEF register s MOM bit 0 writing to the CnBRP register is enabled only when the initialization mode has been set CnCTRL register s INIT bit 1 This register can be read written in 16 bit units The C2BRP register is valid only in models µPD703089Y and 70F3089Y Caution While in diagnostic processing mode CnDEF register...

Page 625: ...BRP4 BRP3 BRP2 BRP1 BRP0 a When TLM 0 TLM Transfer layer mode specification 0 6 bit prescaler mode BTYPE CAN bus type specification 0 Low speed 125 Kbps 1 High speed 125 Kbps a BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN protocol layer basic system clock fBTL 0 0 0 0 0 0 0 fMEM 2 1 0 0 0 0 0 1 fMEM 4 2 0 0 0 0 1 0 fMEM 6 3 0 0 0 0 1 1 fMEM 8 fMEM a 1 2 60 1 1 1 1 0 0 fMEM 122 61 1 1 1 1 0 1 fMEM 124 62 1 1 ...

Page 626: ... BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN protocol layer basic system clock fBTL 0 0 0 0 0 0 0 0 0 Setting prohibited 1 0 0 0 0 0 0 0 1 fMEM 2 2 0 0 0 0 0 0 1 0 fMEM 3 3 0 0 0 0 0 0 1 1 fMEM 4 fMEM a 1 252 1 1 1 1 1 1 0 0 fMEM 253 253 1 1 1 1 1 1 0 1 fMEM 254 254 1 1 1 1 1 1 1 0 fMEM 255 255 1 1 1 1 1 1 1 1 fMEM 256 Remark fBTL fMEM a 1 CAN protocol layer basic system clock a 0 to 255 set by bits BR...

Page 627: ...ic processing mode CnDEF register s MOM bit 1 and in normal operating mode CnCTRL register s INIT bit 0 2 Storage of the last 8 bits is automatically stopped if an error or a valid message ACK delimiter is detected on the CAN bus Storage is automatically reset each time when SOF is detected on the CAN bus After reset 0000H R Addresses C1DINF xx3FFC5CH C2DINF xx3FFC9CH 15 14 13 12 11 10 9 8 CnDINF ...

Page 628: ...int 17 BTL 4 set values of SPTR4 to SPTR0 16 8 BTL DBT data bit time 25 BTL 7 set values of DBTR4 to DBTR0 24 SJW synchronization jump width DBT SPT 2 DBT SPT 8 Remark BTL 1 fBTL fBTL CAN protocol layer basic system clock 1 2 After reset 0218H R W Addresses C1SYNC xx3FFC5EH C2SYNC xx3FFC9EH 15 14 13 12 11 10 9 8 CnSYNC 0 0 0 SAMP SJWR1 SJWR0 SPTR4 SPTR3 n 1 2 7 6 5 4 3 2 1 0 SPTR2 SPTR1 SPTR0 DBTR...

Page 629: ...t within bit timing is selected DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 Data bit time 0 0 1 1 1 BTL 8 0 1 0 0 0 BTL 9 0 1 0 0 1 BTL 10 0 1 0 1 0 BTL 11 0 1 0 1 1 BTL 12 0 1 1 0 0 BTL 13 0 1 1 0 1 BTL 14 0 1 1 1 0 BTL 15 0 1 1 1 1 BTL 16 1 0 0 0 0 BTL 17 1 0 0 0 1 BTL 18 1 0 0 1 0 BTL 19 1 0 0 1 1 BTL 20 1 0 1 0 0 BTL 21 1 0 1 0 1 BTL 22 1 0 1 1 0 BTL 23 1 0 1 1 1 BTL 24 1 1 0 0 0 BTL 25 Other than above Set...

Page 630: ...ter CnIE Remark n 1 2 All 16 bits in the above registers can be read via the usual method Use the procedure described in Figure 19 3 below to set or clear the lower 8 bits in these registers Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits see Figure 19 4 Figure 19 3 shows how the values of set bits or clear bits relate to set clear no c...

Page 631: ...ta During Write Operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Status of bit n after bit set clear operation 0 0 No change 0 1 0 1 0 1 1 1 No change Remark n 0 to 7 ...

Page 632: ... be selected for message reception in the FCAN controller Use bit 3 TMR of the CANx control register CxCTRL to set the desired time stamp function x 1 2 When the TMRT bit is 0 the time stamp counter value is captured after the SOF is sent via the CAN bus see Figure 19 5 and when the TMR bit is 1 the time stamp counter value is captured after the EOF is sent via the CAN bus a valid message is confi...

Page 633: ...stem the time value must be captured using the SOF In addition the ability to capture the counter value when data is stored in a message buffer is useful for evaluating the FCAN controller s performance The captured time stamp counter value is stored in CAN message buffer n so CAN message buffer n has its own time stamp function n 00 to 31 When the SOF is sent via the CAN bus while transmitting a ...

Page 634: ...egister value 2 Note 2 Note 3 3 M_DATAn0 register value Note 2 Note 3 4 M_DATAn0 register value M_DATAn1 register value Note 2 Note 3 5 M_DATAn0 register value M_DATAn1 register value M_DATAn2 register value Note 2 Note 3 6 M_DATAn0 register value M_DATAn1 register value M_DATAn2 register value M_DATAn3 register value Note 2 Note 3 7 M_DATAn0 register value M_DATAn1 register value M_DATAn2 registe...

Page 635: ... U15109EJ3V0UD 633 19 8 Message Processing A modular system is used for the FCAN controller Consequently messages can be placed at any location within the message area The messages can be linked to mask functions that are in turn linked to CAN modules ...

Page 636: ...s waiting to be transmitted in the message buffer that can be set simultaneously by application software is up to five messages per CAN module Note The number of message buffers when the TRQ bit of the M_STATn register 1 When the PBB bit is set to 1 see Figure 19 9 Transmission priority is controlled by the message numbers The number Note of messages waiting to be transmitted in the message buffer...

Page 637: ... 2 6 Low Message buffer linked to mask 3 A message data frame or remote frame is always stored in a receive message buffer with a higher priority not in a receive buffer with a lower priority For example when the unmasked receive message buffer and the message buffer linked to the mask 0 have the same ID a message is always stored in the unmasked receive message buffer even if the unmasked receive...

Page 638: ...ned as 0 by masking For example let us assume that all messages that have a standard format ID in which bit ID27 to ID25 0 and bits ID24 and ID22 1 are to be stored in message buffer 14 which is linked by CAN module 1 or mask 1 as was explained in 19 5 6 The procedure for this example is shown below 1 Identifier bits to be stored in message buffer ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ...

Page 639: ...D27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 1 0 0 0 0 1 0 1 1 1 1 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 1 1 1 1 1 1 1 1 1 1 1 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 1 1 1 1 1 1 1 1 Do not compare mask 0 Compare Values are written to mask 1 see 19 5 18 bits CMID27 to CMID24 and CMID22 0 and bits CMID28 CMID23 and CMID21 to CMID0 1 ...

Page 640: ...ormat 2048 different identifiers can be set The standard format frame uses 11 bit identifiers which means that it can handle up to 2048 messages 2 Extended format frame This format is used to set the identifiers of approx 5 3 million types The extended format frame uses 29 bit 11 bits 18 bits identifiers which increases the number of messages that can be handled to 2048 2 18 messages Extended form...

Page 641: ...rame or remote frame 1 Bus value The bus values are divided into dominant and recessive Dominant level is indicated by logical 0 Recessive level is indicated by logical 1 When a dominant level and a recessive level are transmitted simultaneously the bus value becomes dominant level 19 10 3 Data frame and remote frame 1 Data frame A data frame is composed of seven fields Figure 19 11 Data Frame R D...

Page 642: ...ield s data length code is not 0000B 2 D Dominant 0 R Recessive 1 3 Description of fields 1 Start of frame SOF The start of frame field is located at the start of a data frame or remote frame Figure 19 13 Start of Frame SOF R D 1 bit Start of frame Interframe space or bus idle Arbitration field Remark D Dominant 0 R Recessive 1 If the dominant level is detected in bus idle mode the start of frame ...

Page 643: ...9 15 Arbitration Field in Extended Format Mode R D r1 r0 RTR IDE SRR Identifier Identifier Arbitration field Control field 11 bits 18 bits ID28 ID18 ID17 ID0 1 bit 1 bit 1 bit Cautions 1 ID28 to ID0 are identifier bits 2 Identifier bits are transferred in MSB first order Remark D Dominant 0 R Recessive 1 Table 19 17 RTR Frame Settings Frame Type RTR Bit Data frame 0 D Remote frame 1 R Table 19 18 ...

Page 644: ...t 0 R Recessive 1 In a standard format frame the control field s IDE bit is the same as the r1 bit Table 19 19 Data Length Code Settings Data Length Code DLC3 DLC2 DLC1 DLC0 Data Byte Count 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes Other than above 8 bytes regardless of the value of DLC3 to DLC0 Ca...

Page 645: ...ence CRC delimiter 1 bit 15 bits CRC field ACK field Data field or control field Remark D Dominant 0 R Recessive 1 The polynomial P X used to generate the 15 bit CRC sequence is expressed as follows P X X 15 X 14 X 10 X 8 X 7 X 4 X 3 1 Transmitting node The CRC sequence calculated from the data before bit stuffing in the start of frame arbitration field control field or data field is the transferr...

Page 646: ...frame CRC field Remark D Dominant 0 R Recessive 1 If no CRC error is detected the receiving node set the ACK slot to the dominant level The transmitting node outputs two recessive level bits 7 End of frame EOF The end of frame field indicates the end of data frame remote frame Figure 19 20 End of Frame EOF R D End of frame 7 bits Interframe space or overload frame ACK field Remark D Dominant 0 R R...

Page 647: ...rframe space Intermission 3 or 2 bits Bus idle 0 or more bits Frame Frame Remarks 1 Bus idle Status in which the bus is not used by nodes 2 D Dominant 0 R Recessive 1 b Error passive node The error passive node is composed of an intermission field suspend transmission field and bus idle field Figure 19 22 Interframe Space Error Passive Node R D Interframe space Intermission 3 or 2 bits Suspend tra...

Page 648: ...nable mode is set Receive mode is set if a transmission starts from a different node in bus idle mode the transmission priority of the local node is lowered Operation when the third bit of the intermission field is dominant level Table 19 21 Operation When Third Bit of Intermission Is Dominant Level Error Status Operation No pending transmissions A receive operation is performed when start of fram...

Page 649: ...evel bits When the other node outputs a dominant level during output of the passive error flag the passive error flag does not end until 6 same level bits are detected consecutively 2 Error flag 2 0 to 6 A node that receives error flag 1 is a node in which bit stuffing errors are detected after which error flag 2 is output 3 Error delimiter 8 8 consecutive recessive level bits are output If a domi...

Page 650: ...ame Overload frame Remarks 1 Node n node m Each node n m 2 D Dominant 0 R Recessive 1 Table 19 23 Field Definition of Overload Frame No Name Bit count Definition 1 Overload flag starting from node m 6 Consecutive output of 6 dominant level bits Output when node m is not ready to receive 2 Overload flag starting from node n 0 to 6 Node n which has received an overload flag in the interframe space o...

Page 651: ...rame and a remote frame the data frame takes priority because its last bit RTR is dominant level 19 11 2 Bit stuffing Bit stuffing is when one bit of inverted data is added for resynchronization to prevent burst errors when the same level is maintained for five consecutive bits Table 19 25 Bit Stuffing Transmit When transmitting data frames and remote frames if the same level is maintained for at ...

Page 652: ...of frame error frame or overload frame Stuff error Use stuff bits to check receive data Six consecutive bits of same level data Transmitting receiving nodes Start of frame to CRC sequence CRC error Comparison of CRC generated from receive data and received CRC sequence CRC mismatch Receiving node Start of frame to data field Form error Check fixed format field frame Detection of inverted fixed for...

Page 653: ...he bus may become seriously damaged During start up if only one node is active the error frame and data are repeatedly resent because no ACK is returned even data has been transmitted Table 19 28 Types of Error Statuses Error Status Type Operation Error Counter Value Type of Output Error Flag Error active Transmit receive 0 to 127 Active error flag 6 consecutive dominant level bits Transmit 128 to...

Page 654: ...put of active error flag or overload flag transmitting node with error active status 8 No change Detection of bit error during output of active error flag or overload flag receiving node with error active status No change 8 14 consecutive dominant level bits were detected from the start of each node s active error flag or overload flag followed by detection of eight consecutive dominant level bits...

Page 655: ...n bit rate prescaler register CnBRP 2 Nominal bit time 8 to 25 time quanta The definition of 1 data bit time 1 time quantum is shown below Caution When selecting fMEM1 as the clock fMEM to the memory access controller using the CAN main clock select register CGCS and fMEM 2 as the CAN protocol layer base system clock fBTL using the CANn bit rate prescaler register CnBRP set fXX 16 MHz to make one ...

Page 656: ...s the range for bit synchronization Note IPT Information Processing Time IPT is a period in which the current bit level is referenced and judgement for the next processing is performed IPT is indicated by the expression below using the supply clock fMEM1 to CAN IPT fMEM1 3 3 Data bit synchronization Since the receiving node has no synchronization signal synchronization is performed using level cha...

Page 657: ... point phase error Negative Edge is after sample point phase error When the edge is detected as within the bit timing specified by the SJW synchronization is performed in the same way as hardware synchronization When the edge is detected as extending beyond the bit timing specified by the SJW synchronization is performed on the following basis When phase error is positive Phase segment 1 is length...

Page 658: ... Register CnSYNC Settings See setting shown in Figure 19 34 CANn Interrupt Enable Register CnIE Settings See setting shown in Figure 19 35 CANn Definition Register CnDEF Settings See setting shown in Figure 19 36 CANn Control Register CnCTRL Settings See Figure 19 37 CANn Address Mask a Registers L and H CnMASKLa and CnMASKHa Settings See Figure 19 38 Message Buffer Settings Set CAN global interru...

Page 659: ... Clock supply to CAN fGTS1 Global timer clock fGTS System timer prescaler Figure 19 30 Setting of CAN Global Interrupt Enable Register CGIE Remark GOM Bit of CAN global status register CGST EFSD Bit of CAN global status register CGST ISTAT Bit of CANn control register CnCTRL START No Enable interrupt for G_IE1 bit Yes set G_IE1 1 clear G_IE1 0 No Enable interrupt for G_IE2 bit Yes set G_IE2 1 clea...

Page 660: ... GOM 0 Figure 19 32 Setting of CANn Bit Rate Prescaler CnBRP START No Transfer speed is 125 Kbps or less Yes BTYPE 0 low speed fBTL setting When TLM 0 BRP5 to BRP0 When TLM 1 BRP7 to BRP0 When TLM 0 fBTL fMEM m 1 2 m 0 to 63 set using bits BRP5 to BRP0 When TLM 1 fBTL fMEM m 1 m 0 to 255 set using bits BRP7 to BRP0 fBTL BTYPE 1 high speed Remarks 1 fBTL CAN protocol layer basic system clock fMEM C...

Page 661: ... m 2 to 16 set using bits SPTR4 to SPTR0 Note Set sample point SPTR4 to SPTR0 Set SJW SJWR1 SJWR0 SAMP 1 Yes Set once only single shot sampling Set sampling for one location only Set sampling for three locations SJW BTL m 1 m 0 to 3 set using bits SJWR1 and SJWR0 Note The setting of m 2 3 is reserved for setting sample point extension and is not compliant with the CAN protocol specifications Remar...

Page 662: ...No clear E_INT2 1 set E_INT2 0 Enable interrupt for E_INT2 Interrupt enable flag for error passive or bus off by TEC set E_INT3 1 clear E_INT3 0 No clear E_INT3 1 set E_INT3 0 Enable interrupt for E_INT3 Interrupt enable flag for error passive by REC set E_INT4 1 clear E_INT4 0 No clear E_INT4 1 set E_INT4 0 Enable interrupt for E_INT4 Interrupt enable flag for wake up from CAN sleep mode set E_IN...

Page 663: ...bers Diagnostic processing mode Transmit priority is determined based on identifiers Single shot mode Transmit only once Do not retransmit clear DGM 1 set DGM 0 No set DGM 1 clear DGM 0 Store to buffer used for diagnostic processing modeNote clear PBB 1 set PBB 0 No set PBB 1 clear PBB 0 Determine transmit priority based on identifiers set SSHT 1 clear SSHT 0 No clear SSHT 1 set SSHT 0 Set single ...

Page 664: ...pins Set dominant level for receive pins Store timer value at EOF Do not overwrite message in DN flag delete new message Set dominant level to high level Set dominant level to high level set OVM 1 clear OVM 0 Yes clear OVM 1 set OVM 0 Store message in DN flag set DLEVT 1 clear DLEVT 0 Yes clear DLEVT 1 set DLEVT 0 Set dominant level to low level set DLEVR 1 clear DLEVR 0 Yes No No No No clear DLEV...

Page 665: ...H CnMASKLa and CnMASKHa START Standard frame Mask setting for standard frame x 18 to 28 Mask setting for extended frame x 0 to 28 Mask setting for message ID format Yes CMIDx 0 CMIDy 1 CMIDx 1 Compare with received ID bit No Yes No Yes CMIDE 0 CMIDE 1 Check ID type No Yes CMIDx 0 CMIDx 1 Compare with received ID bit No y 0 to 17 ...

Page 666: ... See Figure 19 39 Setting of CAN Message Configuration Registers 00 to 31 M_CONF00 to M_CONF31 See Figure 19 40 Setting of CAN Message Control Registers 00 to 31 M_CTRL00 to M_CTRL31 IDE 1 extended M_IDHm Set identifier standard extended Set message control byte Set message length See Figure 19 41 Setting of Message Status Registers 00 to 31 M_STAT00 to M_STAT31 Set message status Remark m 00 to 3...

Page 667: ...0 MA2 to MA0 010 MA2 to MA0 001 Yes No No No No No No No MT2 to MT0 111 used in diagnostic processing mode MT2 to MT0 000 MT2 to MT0 001 MT2 to MT0 010 MT2 to MT0 011 MT2 to MT0 100 MT2 to MT0 101 CAN module 2 Message buffer address specification CAN module 1 Yes Yes Yes Yes Transmit message Receive message no mask setting Receive message set mask 0 Receive message set mask 1 Receive message set m...

Page 668: ...RL31 START Yes No No RTR 0 RTR 1 Transmit receive remote frame Transmit receive data frame Set remote frame auto acknowledge function Yes No IE 0 IE 1 Enable interrupt Disable interrupt Yes No RMDE0 1 RMDE0 0 Remote frame auto acknowledge Yes No RMDE1 1 RMDE1 0 ATS 1 ATS 0 Set DN flag Yes Apply time stamp Set DN flag when remote frame is received ...

Page 669: ...09EJ3V0UD 667 Figure 19 41 Setting of CAN Message Status Registers 00 to 31 M_STAT00 to M_STAT31 START Clear DN flag clear DN 1 set DN 0 SC_STATm Clear TRQ flag clear TRQ 1 set TRQ 0 SC_STATm Clear RDY flag clear RDY 1 set RDY 0 SC_STATm Remark m 00 to 31 ...

Page 670: ...ansmit messages are output from the target message buffer Figure 19 42 Transmit Setting START End of transmit operation Set RDY flag set RDY 1 clear RDY 0 SC_STATm Set data M_DATAmn Select transmit message buffer Set transmit request flag set TRQ 1 clear TRQ 0 SC_STATm Remark n 0 to 7 m 00 to 31 ...

Page 671: ... operation Yes Receive data frame No Yes Receive data frame Receive remote frame Detection methods 1 Detect using CANn information register CnLAST 2 Detect using CAN message search start result register CGMSS CGMSR see Figure 19 45 Setting of CAN Message Search Start Result Register CGMSS CGMSR No DN 0 M_STATm Detect target message buffer Clear DN flag clear DN 1 set DN 0 SC_STATm Get data length ...

Page 672: ...e data frame No Yes Receive data frame CnINT1 1 CnINTP Receive remote frame Detection methods 1 Detect using CANn information register CnLAST 2 Detect using CAN message search start result register CGMSS CGMSR see Figure 19 45 Setting of CAN Message Search Start Result Register CGMSS CGMSR No No DN 0 M_STATm Detect target message buffer Clear DN flag clear DN 1 set DN 0 SC_STATm Get data length Tr...

Page 673: ...GMSS CGMSR START Yes Yes Search non mask linked messages only Search all messages regardless of mask setting Do not check message ID format Search standard ID only Check message ID No No CIDE 1 CGMSS CIDE 0 CGMSS CMSK 0 CGMSS Get search results Check DN flag CDN 1 Check masked messages CMSK 1 CGMSS Set start position and start search ...

Page 674: ...occurs when there is a bus operation Figure 19 46 CAN Sleep Mode Setting START End of CAN sleep mode setting No Yes SLEEP 1 CnCTRL set SLEEP 1 clear SLEEP 0 CnCTRL Remark n 1 2 Figure 19 47 Clearing CAN Sleep Mode by CAN Bus Active Status START CAN bus active SLEEP 0 CnCTRL WAKE 1 CnDEF Wake up interrupt occurs End of CAN sleep mode clearing operation Remark n 1 2 ...

Page 675: ...9 FCAN CONTROLLER V850 SC3 User s Manual U15109EJ3V0UD 673 Figure 19 48 Clearing CAN Sleep Mode by CPU clear SLEEP 1 set SLEEP 0 CnCTRL SLEEP 0 CnCTRL START End of CAN sleep mode clearing operation Remark n 1 2 ...

Page 676: ...on stop mode is controlled by CPU access only Figure 19 49 CAN Stop Mode Setting START End of CAN stop mode setting Yes Yes SLEEP 1 CnCTRL STOP 1 CnCTRL No No set STOP 1 clear STOP 0 CnCTRL Set CAN sleep mode see Figure 19 46 Remark n 1 2 Figure 19 50 Clearing CAN Stop Mode START End of CAN stop mode clearing operation clear STOP 1 set STOP 0 clear SLEEP 1 set SLEEP 0 CnCTRL STOP 0 SLEEP 0 CnCTRL ...

Page 677: ...ntrol register CnSYNC 1 Example of FCAN baud rate setting when CnBRP register s TLM bit 0 The following is an example of how correct settings for the CnBRP register and CnSYNC register can be calculated Conditions from CAN bus 1 CAN base clock frequency fMEM 16 MHz 2 CAN bus baud rate 83 Kbps 3 Sample point 80 or more 4 Synchronization jump width 3 BTL First calculate the ratio between the CAN bas...

Page 678: ... 8 4 48 9 3 64 10 The settings that can actually be made for the V850 SC3 are in the range from 4 to 7 above the section enclosed in broken lines Among these options in the range from 4 to 7 above option 6 is the ideal setting when actually setting the register i Prescaler CAN protocol layer basic system clock fBTL setting fBTL is calculated as shown below fBTL fMEM a 1 2 0 a 63 Value a is set usi...

Page 679: ...DBT SPT 3 16 SPT SPT 13 Therefore SPT is set as 13 max SPT is calculated as shown below SPT BTL a 1 4 a 16 Value a is set using bits 9 to 5 SPTR4 to SPTR0 of the CnSYNC register SPT BTL 13 BTL 12 1 thus a 12 Therefore the CnSYNC register s bits SPTR4 to SPTR0 01100B iv SJW Synchronization Jump Width setting SJW is calculated as shown below SJW BTL a 1 0 a 3 Value a is set using bits11 and 10 SJWR1...

Page 680: ... s Manual U15109EJ3V0UD 678 Figure 19 51 CnSYNC Register Settings 15 14 13 12 11 10 9 8 CnSYNC 0 0 0 SAMP SJWR1 SJWR0 SPTR4 SPTR3 Setting 0 0 0 0 1 0 0 1 7 6 5 4 3 2 1 0 SPTR2 SPTR1 SPTR0 DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 Setting 1 0 0 0 1 1 1 1 ...

Page 681: ...U performs sequential access of a message buffer data is read from the buffer in the order shown in Figure 19 74 below Only the FCAN internal operation can set the M_STATn register s DN bit 1 and only the CPU can clear it 0 so during the read operation the CPU must be able to check whether or not any new data has been stored in the message buffer Figure 19 52 Sequential Data Read Read CPU End of C...

Page 682: ...wing order M_DLCn register M_CTRLn register M_TIMEn register M_DATAn0 to M_DATAn7 registers M_IDLn M_IDHn register and reads more data If these linear access rules are not followed or if access is attempted to an address that is lower than the MIDHn register s address such as the M_CONFn register or M_STATn register burst read mode becomes invalid Cautions 1 16 bit read access is required for the ...

Page 683: ... Bit stuff error Form error CRC error ACK error 3 When the CAN bus mode has been changed Error passive status elapsed while FCAN was transmitting Bus off status was set while FCAN was transmitting Error passive status elapsed while FCAN was receiving 4 Internal error Overrun error 19 15 2 Interrupts that occur for global CAN interface Interrupts occur for the global CAN interface under the followi...

Page 684: ...errupt requests may not be generated Note also that if an interrupt is generated at the same time as a CPU clear operation that interrupt request flag will not be cleared 0 It is therefore important to confirm that interrupt request flags have been properly cleared 0 Note See 19 5 9 CAN interrupt pending register CCINTP 19 5 10 CAN global interrupt pending register CGINTP and 19 5 11 CANn local in...

Page 685: ...i Poll the corresponding interrupt request flag ii If the value of the bit in procedure i is 1 clear 0 the corresponding interrupt pending bit iii After executing procedure ii clear 0 the interrupt request flag Example CAN reception i Poll until the CANIFm bit of the CANICm register becomes 1 m 2 5 ii Clear 0 the CnINT1 bit of the CnINTP register n 1 2 iii Clear 0 the CANIFm bit of the CANICm regi...

Page 686: ...nt temperature TA Flash memory programming modeNote 2 20 to 85 C Note 3 65 to 150 C Storage temperature Tstg Note 2 40 to 125 C Notes 1 Be sure not to exceed the absolute maximum ratings MAX value of each supply voltage 2 µPD70F3089Y 3 µPD703068Y 703069Y 703088Y 703089Y Cautions 1 Avoid direct connections among the IC device output or I O pins and between VDD or VCC and GND However direct connecti...

Page 687: ...3069Y 703088Y 703089Y 2 µPD70F3089Y 3 When using the FCAN controller PORTVDD1 PORTVDD2 due to the supply voltage conditions of the in circuit emulator Remark I O buffer power supply of each pin is shown below Power Supply Corresponding Pins PORTVDD0 P40 to P47 P50 to P57 P60 to P65 P90 to P96 CLKOUT PORTVDD1 P00 to P03 P10 to P17 P30 to P37 P100 to P107 P110 to P117 PORTVDD2 P04 to P07 P20 to P27 ...

Page 688: ...xternal clock input is prohibited 2 When using the main clock oscillator wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make t...

Page 689: ...ea enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor ...

Page 690: ... V IOH 100 µA VDD 0 5 V VOH1 Note 3 4 0 V VDD 5 5 V IOH 1 mA VDD 1 0 V 3 0 V PORTVDD 4 0 V IOH 100 µA PORTVDD 0 5 V Output voltage high VOH2 Note 4 4 0 V PORTVDD 5 5 V IOH 1 mA PORTVDD 1 0 V 3 5 V VDD 5 5 V IOH 100 µA 0 5 V VOL1 Note 3 4 0 V VDD 5 5 V IOH 1 mA 0 5 V 3 0 V PORTVDD 4 0 V IOH 100 µA 0 5 V Output voltage low VOL2 Note 4 4 0 V PORTVDD 5 5 V IOH 1 mA 0 5 V Notes 1 P11 P14 P16 P21 P25 P2...

Page 691: ...2 60 mA IDD2 In HALT modeNote 7 14 28 mA IDD3 In IDLE modeNote 8 1 4 mA IDD4 In software STOP modeNote 9 15 100 µA IDD5 In normal mode subclock operation Note 10 300 600 µA Supply current µPD70F3089Y IDD6 In IDLE mode subclock operation Note 11 170 340 µA Notes 1 P170 to P176 RESET and their alternate function pins 2 All input pins other than P170 to P176 RESET and their alternate function pins 3 ...

Page 692: ...e time tRVD 200 µs Supply voltage fall time tFVD 200 µs Supply voltage hold time from STOP mode setting tHVD 0 ms STOP release signal input time tDREL 0 ns Data retention high level input voltage VIHDR All input ports 0 9VDDDR VDDDR V Data retention low level input voltage VILDR All input ports 0 0 1VDDDR V Note Subclock stopped tHVD VDDDR tDREL VIHDR VIHDR tFVD tRVD VDD Stop mode release interrup...

Page 693: ... VIL Test points Input signal AC Test Output Test Points VDD VDD PORTVDD Load Conditions DUT Device under test CL 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration lower the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means VOH VOL VOH VOL Test points Output signal VDD 0 V ...

Page 694: ... width 3 tWKL 0 4 tCYK tKR tKF ns CLKOUT rise time 4 tKR 12 ns CLKOUT fall time 5 tKF 12 ns b TA 40 to 85 C PORTVDD 3 0 to 4 0 V PORTGND 0 V µ µ µ µPD703068Y 703069Y 703088Y 703089Y VDD 3 5 to 5 5 V µ µ µ µPD70F3089Y VDD 4 0 to 5 5 V Parameter Symbol Conditions MIN MAX Unit CLKOUT output cycle 1 tCYK 58 8 ns 31 µs CLKOUT high level width 2 tWKH 0 4 tCYK tKR tKF ns CLKOUT low level width 3 tWKL 0 4...

Page 695: ...V PORTGND 0 V µ µ µ µPD703068Y 703069Y 703088Y 703089Y VDD 3 5 to 5 5 V µ µ µ µPD70F3089Y VDD 4 0 to 5 5 V Parameter Symbol Conditions MIN MAX Unit Output rise time 6 tOR 35 ns Output fall time 7 tOF 35 ns 3 Reset timing TA 40 to 85 C PORTVDD 3 0 to 5 0 V µ µ µ µPD703068Y 703069Y 703088Y 703089Y VDD 3 5 to 5 5 V µ µ µ µPD70F3089Y VDD 4 0 to 5 5 V Parameter Symbol Conditions MIN MAX Unit RESET pin ...

Page 696: ... 22 tWSTH T 15 ns Data output time from DSTB 23 tDDOD 10 ns Data output setup time to DSTB 24 tSODD 1 n T 25 ns Data output hold time from DSTB 25 tHDOD T 20 ns 26 tSAWT1 n 1 1 5T 40 ns WAIT setup time to address 27 tSAWT2 1 5 n T 40 ns 28 tHAWT1 n 1 0 5 n T ns WAIT hold time from address 29 tHAWT2 1 5 n T ns 30 tSSTWT1 n 1 T 32 ns WAIT setup time to ASTB 31 tSSTWT2 1 n T 32 ns 32 tHSTWT1 n 1 nT n...

Page 697: ... 1 n T 35 ns ASTB high level width 22 tWSTH T 18 ns Data output time from DSTB 23 tDDOD 20 ns Data output setup time to DSTB 24 tSODD 1 n T 35 ns Data output hold time from DSTB 25 tHDOD T 30 ns 26 tSAWT1 n 1 1 5T 55 ns WAIT setup time to address 27 tSAWT2 1 5 n T 55 ns 28 tHAWT1 n 1 0 5 n T ns WAIT hold time from address 29 tHAWT2 1 5 n T ns 30 tSSTWT1 n 1 T 45 ns WAIT setup time to ASTB 31 tSSTW...

Page 698: ...es in the above specifications are values for when clocks with a 1 1 duty ratio are input from X1 d Clock synchronous TA 40 to 85 C PORTVDD 3 0 to 4 0 V µ µ µ µPD703068Y 703069Y 703088Y 703089Y VDD 3 5 to 5 5 V µ µ µ µPD70F3089Y VDD 4 0 to 5 5 V Parameter Symbol Conditions MIN MAX Unit Delay time from CLKOUT to address 39 tDKA 0 40 ns Delay time from CLKOUT to address float 40 tFKA 16 10 ns Delay ...

Page 699: ... asynchronous 1 wait CLKOUT output ASTB output T1 T2 TW 39 16 21 46 DSTB output WAIT input AD0 to AD15 I O 40 10 44 41 T3 43 13 22 17 14 20 18 19 42 12 30 32 26 28 27 29 31 47 46 47 Data Address 41 11 42 33 A16 to A21 output Note output 15 Note R W UBEN LBEN Remark Broken lines indicate high impedance ...

Page 700: ...nchronous asynchronous 1 wait CLKOUT output ASTB output T1 T2 TW 39 16 21 46 A16 to A21 output Note output DSTB output WAIT input AD0 to AD15 I O 45 10 41 T3 22 24 25 19 42 23 30 32 26 28 27 29 31 47 46 47 Data Address 41 11 42 33 Note R W UBEN LBEN Remark Broken lines indicate high impedance ...

Page 701: ...09EJ3V0UD 699 g Bus hold timing CLKOUT output TH 48 49 TH TH TH TI 48 37 51 51 35 38 34 50 36 A16 to A19 output Note output HLDRQ input HLDAK output ASTB output DSTB output AD0 to AD15 I O Data Note R W UBEN LBEN Remark Broken lines indicate high impedance ...

Page 702: ...NIH 500 ns NMI low level width 53 tWNIL 500 ns n 0 to 3 7 to 9 analog noise elimination 500 ns n 4 5 digital noise elimination 3T 20 ns INTPn high level width 54 tWITH n 6 digital noise elimination 3Tsmp 20 ns 55 tWITL n 0 to 3 7 to 9 analog noise elimination 500 ns n 4 5 digital noise elimination 3T 20 ns INTPn low level width n 6 digital noise elimination 3Tsmp 20 ns Remarks 1 T 1 fXX 2 Tsmp Noi...

Page 703: ...TIHm m 5 6 3T 20 ns TIm low level width 59 tTILm m 5 6 3T 20 ns Note The following cycles can be selected for Tsam count clock cycle by setting the PRMn2 to PRMn0 bits of prescaler mode registers n0 and n1 PRMn0 PRMn1 When n 0 TM0 Tsam 2T 4T 16T 64T 256T or 1 INTWTNI cycle When n 1 7 TM1 TM7 Tsam 2T 4T 16T 32T 128T or 256T cycle When n 8 10 12 TM8 TM10 TM12 Tsam 2T 8T 16T 32T 128T or 256T cycle Wh...

Page 704: ...40 to 85 C PORTVDD 3 0 to 5 5 V µ µ µ µPD703068Y 703069Y 703088Y 703089Y VDD 3 5 to 5 5 V µ µ µ µPD70F3089Y VDD 4 0 to 5 5 V Parameter Symbol Conditions MIN MAX Unit ASCKn cycle time 60 tKCY13 200 ns ASCKn high level width 61 tKH13 80 ns ASCKn low level width 62 tKL13 80 ns Remark n 0 to 3 63 62 60 ASCKn input Remark n 0 to 3 ...

Page 705: ... 140 ns SCKn low level width 65 tKL1 140 ns SIn setup time to SCKn 66 tSIK1 50 ns SIn hold time from SCKn 67 tKSI1 50 ns ns Delay time from SCKn to SOn output 68 tKSO1 60 ns Remark n 0 2 3 b Slave mode Parameter Symbol Conditions MIN MAX Unit SCKn cycle 63 tKCY2 400 ns SCKn high level width 64 tKH2 140 ns SCKn low level width 65 tKL2 140 ns SIn setup time to SCKn 66 tSIK2 50 ns SIn hold time from ...

Page 706: ...CHAPTER 20 ELECTRICAL SPECIFICATIONS 704 User s Manual U15109EJ3V0UD 67 68 66 63 64 65 Remarks 1 Broken lines indicate high impedance 2 n 0 2 3 SCKn I O SIn input SOn output Input data Output data ...

Page 707: ...KL1 Note 2 140 ns Note 1 25 ns SI4 setup time to SCK4 72 tSIK1 Note 2 50 ns SI4 hold time from SCK4 73 tKSI1 20 ns Delay time from SCK4 to SO4 output 74 tKSO1 55 ns Notes 1 PORTVDD 4 0 to 5 5 V 2 PORTVDD 3 0 to 4 0 V b Slave mode Parameter Symbol Conditions MIN MAX Unit Note 1 200 ns SCK4 cycle 69 tKCY2 Note 2 400 ns Note 1 60 ns SCK4 high level width 70 tKH2 Note 2 140 ns Note 1 60 ns SCK4 low le...

Page 708: ...CHAPTER 20 ELECTRICAL SPECIFICATIONS 706 User s Manual U15109EJ3V0UD 69 71 70 72 73 74 SI4 input SO4 output SCK4 I O Output data Input data Remark Broken lines indicate high impedance ...

Page 709: ...ote 1 30 ns SIn setup time to SCKn 78 tSIK1 Note 2 60 ns SIn hold time from SCKn 79 tKSI1 30 ns Delay time from SCKn to SOn output 80 tKSO1 55 ns Notes 1 PORTVDD 4 0 to 5 5 V 2 PORTVDD 3 0 to 4 0 V Remark n 5 6 b Slave mode Parameter Symbol Conditions MIN MAX Unit Note 1 200 ns SCKn cycle 75 tKCY2 Note 2 400 ns Note 1 60 ns SCKn high level width 76 tKH2 Note 2 140 ns Note 1 60 ns SCKn low level wi...

Page 710: ...CHAPTER 20 ELECTRICAL SPECIFICATIONS 708 User s Manual U15109EJ3V0UD 75 77 76 78 79 80 SIn input SOn output SCKn I O Output data Input data Remarks 1 Broken lines indicate high impedance 2 n 5 6 ...

Page 711: ...s Stop condition setup time 90 tSU STO 4 0 0 6 µs Pulse width of spike suppressed by input filter 91 tSP 0 50 ns Capacitance load of each bus line Cb 400 400 pF Notes 1 At the start condition the first clock pulse is generated after the hold time 2 The system requires a minimum of 300 ns hold time internally for the SDAn signal at VIHmin of SCLn signal in order to occupy the undefined area at the ...

Page 712: ... 0 LSB Differential linearity errorNote 2 DNL 6 0 LSB Analog power supply voltage AVDD 4 5 5 5 V Analog input voltage VIAN 0 ADCVDD V ADCVDD current AIDD 4 8 mA Notes 1 Excluding quantization error 0 05 FSR 2 Excluding quantization error 0 5LSB Remark LSB Least Significant Bit FSR Full Scale Range Regulator Power on Clear Circuit 4 5 V Detection Flag Characteristics TA 40 to 85 C µ µ µ µPD703068Y ...

Page 713: ...rase 1 write after erase 1 rewrite Note 2 100 Count area Notes 1 The prewrite time prior to erasure and the erase verify time write back time are not included 2 When writing initially to shipped products it is counted as one rewrite for both erase to write and write only Example P Write E Erase Shipped product P E P E P 3 rewrites Shipped product E P E P E P 3 rewrites Remarks 1 The operating cloc...

Page 714: ...TE A 22 0 0 2 B 20 0 0 2 C 20 0 0 2 D F 1 25 22 0 0 2 S144GJ 50 UEN S 1 5 0 1 K 1 0 0 2 L 0 5 0 2 R 3 4 3 G 1 25 H 0 22 0 05 I 0 08 J 0 5 T P M 0 17 N 0 08 P 1 4 Q 0 10 0 05 0 03 0 07 Each lead centerline is located within 0 08 mm of its true position T P at maximum material condition S S M detail of lead end I J F G H Q R P K M L N C D S A B ...

Page 715: ...User s Manual U15109EJ3V0UD 713 CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS TBD ...

Page 716: ...ontrol register IEBus 525 BRGC0 Baud rate generator control register 0 BRG 439 BRGC1 Baud rate generator control register 1 BRG 439 BRGC2 Baud rate generator control register 2 BRG 439 BRGC3 Baud rate generator control register 3 BRG 439 BRGCK4 Baud rate generator output clock select register 4 BRG 337 BRGCN4 Baud rate generator source clock select register 4 BRG 336 BRGMC00 Baud rate generator mo...

Page 717: ... diagnostic information register FCAN 625 C2ERC CAN2 error count register FCAN 617 C2IE CAN2 interrupt enable register FCAN 618 C2INTP CAN2 interrupt pending register FCAN 594 C2LAST CAN2 information register FCAN 616 C2MASKH0 CAN2 address mask 0 register H FCAN 606 C2MASKH1 CAN2 address mask 1 register H FCAN 606 C2MASKH2 CAN2 address mask 2 register H FCAN 606 C2MASKH3 CAN2 address mask 3 regist...

Page 718: ... RPU 258 CR100 16 bit capture compare register 100 RPU 258 CR101 16 bit capture compare register 101 RPU 259 CR11 16 bit capture compare register 11 RPU 259 CR110 16 bit capture compare register 110 RPU 258 CR111 16 bit capture compare register 111 RPU 259 CR120 16 bit capture compare register 120 RPU 258 CR121 16 bit capture compare register 121 RPU 259 CR5 16 bit compare register 5 RPU 297 CR6 1...

Page 719: ...terface mode register 6 CSI 346 CSIS0 Serial clock select register 0 CSI 326 CSIS2 Serial clock select register 2 CSI 326 CSIS3 Serial clock select register 3 CSI 326 CSTOP CAN stop register FCAN 596 DBC0 DMA byte counter register 0 DMAC 475 DBC1 DMA byte counter register 1 DMAC 475 DBC2 DMA byte counter register 2 DMAC 475 DBC3 DMA byte counter register 3 DMAC 475 DBC4 DMA byte counter register 4...

Page 720: ...4 ECR Interrupt source register CPU 89 EGN0 Falling edge specification register 0 INTC 143 226 EGN1 Falling edge specification register 1 INTC 155 240 EGP0 Rising edge specification register 0 INTC 142 226 EGP1 Rising edge specification register 1 INTC 155 240 IEBIC1 Interrupt control register INTC 233 IEBIC2 Interrupt control register INTC 233 IECLK IEBus clock select register IEBus 543 IIC0 IIC ...

Page 721: ... FCAN 581 M_DLC00 to M_DLC31 CAN message data length registers 00 to 31 FCAN 576 M_IDH00 to M_IDH31 CAN message ID registers H00 to H31 FCAN 583 M_IDL00 to M_IDL31 CAN message ID registers L00 to L31 FCAN 583 M_STAT00 to M_STAT31 CAN message status registers 00 to 31 FCAN 587 M_TIME00 to M_TIME31 CAN message time stamp registers 00 to 31 FCAN 579 NCC Noise elimination control register INTC 239 OST...

Page 722: ...egister INYC 233 PIC5 Interrupt control register INTC 233 PIC6 Interrupt control register INTC 233 PIC7 Interrupt control register INTC 233 PM0 Port 0 mode register Port 142 PM1 Port 1 mode register Port 145 PM10 Port 10 mode register Port 169 PM11 Port 11 mode register Port 172 PM12 Port 12 mode register Port 177 PM13 Port 13 mode register Port 180 PM14 Port 14 mode register Port 183 PM15 Port 15...

Page 723: ...register 0 UART 435 RXB1 Receive buffer register 1 UART 435 RXB2 Receive buffer register 2 UART 435 RXB3 Receive buffer register 3 UART 435 SAR IEBus slave address register IEBus 528 SCR IEBus communication success register IEBus 542 SC_STAT00 to SC_STAT31 CAN status set clear registers 00 to 31 FCAN 589 SIO0 Serial I O shift register 0 CSI 325 SIO2 Serial I O shift register 2 CSI 325 SIO3 Serial ...

Page 724: ... INTC 233 SRIC3 Interrupt control register INTC 233 SSR IEBus slave status register IEBus 541 STIC0 Interrupt control register INTC 233 STIC1 Interrupt control register INTC 233 STIC2 Interrupt control register INTC 233 STIC3 Interrupt control register INTC 233 SVA0 Slave address register 0 I2 C 373 387 SVA1 Slave address register 1 I2 C 373 387 SYC System control register Port 201 SYS System stat...

Page 725: ...ister INTC 233 TMIC121 Interrupt control register INTC 233 TMIC5 Interrupt control register INTC 233 TMIC6 Interrupt control register INTC 233 TMIC70 Interrupt control register INTC 233 TMIC71 Interrupt control register INTC 233 TMIC80 Interrupt control register INTC 233 TMIC81 Interrupt control register INTC 233 TMIC90 Interrupt control register INTC 233 TMIC91 Interrupt control register INTC 233...

Page 726: ...k select register WDT 319 WDTIC Interrupt control register INTC 233 WDTM Watchdog timer mode register WDT 238 320 WTNCS Watch timer clock select register WT 312 WTNHC Watch timer high speed clock select register WT 312 WTNIC Interrupt control register INTC 233 WTNIIC Interrupt control register INTC 233 WTNM Watch timer mode control register WT 311 ...

Page 727: ...hows flag statuses refer to Table B 4 This column shows instruction codes op code in binary format 32 bit instructions are displayed in 2 lines refer to Table B 2 Instruction group Table B 1 Symbols in Operand Description Symbol Description reg1 General purpose register r0 to r31 Used as source register reg2 General purpose register r0 to r31 Mainly used as destination register ep Element pointer ...

Page 728: ...load memory a b Reads data of size b from address a store memory a b c Writes data b of size c to address a load memory bit a b Reads bit b from address a store memory bit a b c Writes c to bit b of address a saturated n Performs saturated processing of n n is 2 s complements Result of calculation of n If n is n 7FFFFFFFH as result of calculation 7FFFFFFFH If n is n 80000000H as result of calculat...

Page 729: ... OV 1 Overflow NV 1000 OV 0 No overflow C L 0001 CY 1 Carry Lower Less than NC NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY OR Z 1 Not higher Less than or equal H 1011 CY OR Z 0 Higher Greater than N 0100 S 1 Negative P 1100 S 0 Positive T 0101 Always unconditional SA 1101 SAT 1 Saturated LT 0110 S XOR OV 1 Less than sign...

Page 730: ... ep rrrrr0111ddddddd adr ep zero extend disp7 Store memory adr GR reg2 Byte SST H reg2 disp8 ep rrrrr1001ddddddd Note 1 adr ep zero extend disp8 Store memory adr GR reg2 Halfword SST W reg2 disp8 ep rrrrr1010dddddd1 Note 2 adr ep zero extend disp8 Store memory adr GR reg2 Word ST B reg2 disp16 reg1 rrrrr111010RRRRR dddddddddddddddd adr GR reg1 sign extend disp16 Store memory adr GR reg2 Byte ST H ...

Page 731: ...11RRRRR result GR reg2 GR reg1 CMP imm5 reg2 rrrrr010011iiiii result GR reg2 sign extend imm5 Arithmetic operation SETF cccc reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H SATADD reg1 reg2 rrrrr000110RRRRR GR reg2 saturated GR reg2 GR reg1 SATADD imm5 reg2 rrrrr010001iiiii GR reg2 saturated GR reg2 sign extend imm5 SATSUB reg1 reg2 ...

Page 732: ...010101iiiii GR reg2 GR reg2 arithmetically shift right by zero extend imm5 0 JMP reg1 00000000011RRRRR PC GR reg1 JR disp22 0000011110dddddd ddddddddddddddd0 Note 1 PC PC sign extend disp22 JARL disp22 reg2 rrrrr11110dddddd ddddddddddddddd0 Note 1 GR reg2 PC 4 PC PC sign extend disp22 Jump Bcond disp9 ddddd1011dddcccc Note 2 if conditions are satisfied then PC PC sign extend disp9 SET1 bit 3 disp1...

Page 733: ... RETI 0000011111100000 0000000101000000 if PSW EP 1 then PC EIPC PSW EIPSW else if PSW NP 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW R R R R R HALT 0000011111100000 0000000100100000 Stops DI 0000011111100000 0000000101100000 PSW ID 1 Maskable interrupt disabled EI 1000011111100000 0000000101100000 PSW ID 0 Maskable interrupt enabled Special NOP 0000000000000000 Uses 1 clock cycle without doin...

Page 734: ...Notes in 4 3 1 2 Power save control register PSC Modification of description on operation status of A16 to A21 pins in Table 4 1 Operating Statuses in HALT Mode Modification of description on operation of UART0 to UART3 in Table 4 2 Operating Statuses in IDLE Mode Addition of description in 4 4 4 1 Settings and operating states Modification of description on operation status of UART0 to UART3 in T...

Page 735: ...RBEL5 SIRBEL6 Modification of description on manipulatable bits in 11 4 3 8 Clocked serial interface transmit buffer registers L5 L6 SOTBL5 SOTBL6 Modification of description on manipulatable bits in 11 4 3 10 Clocked serial interface initial transmit buffer registers L5 L6 SOTBFL5 SOTBFL6 Modification of description on manipulatable bits in 11 4 3 12 Serial I O shift registers L5 L6 SIOL5 SIOL6 M...

Page 736: ...gure 17 1 Example of Wiring of Adapter for Flash Programming FA 144GJ UEN Addition of Table 17 1 Table for Wiring of Adapter for µ µ µ µPD70F3089Y Flash Programming FA 144GJ UEN CHAPTER 17 FLASH MEMORY µPD70F3089Y Addition of description in Table 18 5 Control Field Acknowledge Signal Output Conditions CHAPTER 18 IEBus CONTROLLER V850 SC2 Addition of 19 1 Features Modification of description in Tab...

Page 737: ...n in 19 7 Time Stamp Function Modification of description in 19 8 Message Processing Change of Figure 19 10 Composition of Layers Addition of Caution in 19 11 7 2 Nominal bit time 8 to 25 time quanta Addition to Note in Figure 19 25 Nominal Bit Time Addition of description in Figure 19 28 Initialization Processing Addition of Note in Figure 19 33 Setting of CANn Synchronization Control Register Cn...

Page 738: ... U15109EJ3V0UD 5 5 Edition Major Revision from Previous Edition Applied to Addition of CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS 3rd Addition of APPENDIX C REVISION HISTORY APPENDIX C REVISION HISTORY ...

Page 739: ...Fax 86 21 6841 1137 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Taiwan Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 886 2 2719 5951 Fax 65 250 3583 Japan NEC Semiconductor Technic...

Search results

Summary of Contents for V850/SC1

Reviews:

Related manuals for V850/SC1

Brands by name

Popular brands

NEC V850/SC1, User Manual

Search results

Summary of Contents for V850/SC1

Reviews:

Related manuals for V850/SC1

Brands by name

Popular brands