CHAPTER 19 FCAN CONTROLLER (V850/SC3)
User’s Manual U15109EJ3V0UD
683
[When CAN communication is performed by polling of bits, not using interrupt routines]
•
The following interrupt mask flags and interrupt enable bits are used when set (1) (do not clear (0)
them).
•
CANMKn bit of CANICn register (n= 1 to 7)
•
E_INTm bit of CnIE register (n = 1, 2, m = 0 to 6)
•
G_IEn bit of CGIE register (n = 1, 2)
•
IE bit of M_CTRLn register (n = 00 to 31)
•
Clear (0) the following interrupt pending bits in accordance with procedures (i) to (iii) below.
•
CnINTm bit of CnINTP register (n = 1, 2, m = 0 to 6)
•
GINTn bit of CGINTP register (n = 1 to 3)
(i)
Poll the corresponding interrupt request flag.
(ii) If the value of the bit in procedure (i) is 1, clear (0) the corresponding interrupt pending bit.
(iii) After executing procedure (ii), clear (0) the interrupt request flag.
Example
CAN reception
(i)
Poll until the CANIFm bit of the CANICm register becomes 1 (m = 2, 5).
(ii) Clear (0) the CnINT1 bit of the CnINTP register (n = 1, 2).
(iii) Clear (0) the CANIFm bit of the CANICm register.
<5> In the V850/SC3, the time stamp function by SOF detection during message transmission/reception cannot
be used.
Only the time stamp function by EOF detection during message reception can be used for the V850/SC3.
However, only the value captured by the M_TIME register is valid when the TSM bit of the CGST register is
set to 1 and the TMR bit of the CnCTRL register is set to 1.
