CHAPTER 6 BUS CONTROL FUNCTION
User’s Manual U15109EJ3V0UD
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6.9 Bus Priority
There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch
(continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch
(branch), and instruction fetch (continuous) in that order.
The instruction fetch cycle may be inserted in between the read access and write access in read-modify-write
access.
No instruction fetch cycle and bus hold are inserted between the lower halfword access and higher halfword
access of word access operations.
Table 6-3. Bus Priority
External Bus Cycle
Priority
Bus hold
1
Operand data access
2
Instruction fetch (branch)
3
Instruction fetch (continuous)
4
6.10 Memory Boundary Operation Condition
6.10.1 Program space
(1) Do not execute a branch to the on-chip peripheral I/O area or a continuous fetch from the internal RAM area to
peripheral I/O area. If a branch or instruction fetch is executed, the NOP instruction code is continuously fetched
and fetching from external memory is not performed.
(2) A prefetch operation extending over the on-chip peripheral I/O area (invalid fetch) does not take place if a branch
instruction exists at the upper-limit address of the internal RAM area.
6.10.2 Data space
Only the address aligned at the halfword boundary (when the least significant bit of the address is “0”)/word
boundary (when the lowest 2 bits of the address are “0”) is accessed by halfword (16 bits)/word (32 bits) access,
respectively.
Therefore, access that extends over the memory or memory block boundary does not take place.
For details, refer to the
V850 Series Architecture User’s Manual
.
