CHAPTER 11 SERIAL INTERFACE FUNCTION
User’s Manual U15109EJ3V0UD
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(4) IIC clock expansion registers 0, 1 (IICCE0, IICCE1), IIC function expansion registers 0, 1 (IICX0, IICX1),
IIC clock select registers 0, 1 (IICCL0, IICCL1)
These registers are used to set the transfer clock for the I
2
Cn bus.
IICCEn can be set by an 8-bit memory manipulation instruction, and IICXn and IICCLn can be set by an 8-bit
or 1-bit memory manipulation instruction (n = 0, 1).
RESET input sets these registers to 00H.
(1/2)
After reset: 00H
R/W
Address: FFFFF34CH, FFFFF35CH
7
6
5
4
3
2
1
0
IICCEn
0
0
0
0
0
0
IICCEn1
IICCEn0
(n = 0, 1)
After reset: 00H
R/W
Address: FFFFF34AH, FFFFF35AH
7
6
5
4
3
2
1
<0>
IICXn
0
0
0
0
0
0
0
CLXn
(n = 0, 1)
After reset: 00H
R/W
Note
Address: FFFFF344H, FFFFF354H
7
6
<5>
<4>
3
2
1
0
IICCLn
0
0
CLDn
DADn
SMCn
DFCn
CLn1
CLn0
(n = 0, 1)
CLDn
Detection of SCLn line level (valid only when IICEn = 1)
0
SCLn line was detected at low level.
1
SCLn line was detected at high level.
Condition for clearing (CLDn = 0)
Condition for setting (CLDn = 1)
•
When the SCLn line is at low level
•
When IICEn = 0
•
When RESET is input
•
When the SCLn line is at high level
DADn
Detection of SDAn line level (valid only when IICEn = 1)
0
SDAn line was detected at low level.
1
SDAn line was detected at high level.
Condition for clearing (DADn = 0)
Condition for setting (DADn = 1)
•
When the SDAn line is at low level
•
When IICEn = 0
•
When RESET is input
•
When the SDAn line is at high level
Note
Bits 4 and 5 of IICCLn are read-only bits.
Caution
Always set bits 7 and 6 of IICCLn to 0.
Remark
IICEn: Bit 7 of IIC control register n (IICCn)
