26
User’s Manual U15109EJ3V0UD
LIST OF FIGURES (5/8)
Figure No.
Title
Page
11-37
Master Operation Flowchart (1) .....................................................................................................................424
11-38
Master Operation Flowchart (2) .....................................................................................................................425
11-39
Slave Operation Flowchart ............................................................................................................................426
11-40
Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) ........................................................................428
11-41
Example of Slave to Master Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) ........................................................................431
11-42
Block Diagram of UARTn ..............................................................................................................................435
11-43
ASIMn Setting (Operation Stopped Mode) ....................................................................................................441
11-44
ASIMn Setting (Asynchronous Serial Interface Mode) ..................................................................................442
11-45
ASISn Setting (Asynchronous Serial Interface Mode) ...................................................................................443
11-46
BRGCn Setting (Asynchronous Serial Interface Mode).................................................................................444
11-47
BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial Interface Mode).................................................445
11-48
Allowable Baud Rate Error Range (When k = 16), Including Sampling Errors ..............................................447
11-49
Format of Transmit/Receive Data in Asynchronous Serial Interface .............................................................448
11-50
Timing of Asynchronous Serial Interface Transmission Completion Interrupt ...............................................450
11-51
Timing of Asynchronous Serial Interface Reception Completion Interrupt ....................................................451
11-52
Receive Error Timing.....................................................................................................................................452
12-1
Block Diagram of A/D Converter ...................................................................................................................455
12-2
Basic Operation of A/D Converter .................................................................................................................462
12-3
Relationship Between Analog Input Voltage and A/D Conversion Result .....................................................463
12-4
A/D Conversion by Hardware Start (with Falling Edge Specified) .................................................................465
12-5
A/D Conversion by Software Start .................................................................................................................466
12-6
Handling of Analog Input Pin .........................................................................................................................468
12-7
A/D Conversion End Interrupt Generation Timing .........................................................................................469
12-8
Handling of ADCV
DD
Pin................................................................................................................................470
13-1
DMA Block Diagram ......................................................................................................................................472
13-2
Correspondence Between DRAn Setting Value and Internal RAM ...............................................................474
13-3
DMA Transfer Operation Timing....................................................................................................................479
13-4
Processing When Transfer Requests DMA0 to DMA5 Are Generated Simultaneously ................................480
13-5
When Interrupt Servicing Occurs Twice During DMA Operation ...................................................................481
14-1
System Reset Timing by RESET Signal Input...............................................................................................484
14-2
System Reset Timing by Watchdog Timer Overflow .....................................................................................484
14-3
System Reset Timing by Power-on-Clear......................................................................................................485
