APPENDIX C REVISION HISTORY
734
User’s Manual U15109EJ3V0UD
(3/5)
Edition
Major Revision from Previous Edition
Applied to:
Addition to
Cautions
in
Figure 11-47 BRGMCn0 and BRGMCn1 Settings
(Asynchronous Serial Interface Mode)
Addition of description in
11.6.3 (3) (d) Reception
Deletion of description in
11.6.3 (3) (e) Receive error
Modification of
Note
in
Figure 11-52 Receive Error Timing
CHAPTER 11
SERIAL
INTERFACE
FUNCTION
Modification of
Caution
in
12.2 (2) A/D conversion result register (ADCR), A/D
conversion result register H (ADCRH)
Addition of
Caution
in
12.3 (2) Analog input channel specification register (ADS)
Modification of description in
12.6 (3) <3> Conflict between writing of ADCR and writing
A/D converter mode register 1 (ADM1) or analog input channel specification register
(ADS)
Modification of description in
12.6 (8) Reading out A/D converter result register (ADCR)
CHAPTER 12 A/D
CONVERTER
Addition of
13.3 Configuration
Addition to
Cautions
in
13.4 (6) Start factor settings
Addition of
13.5 Operation
Addition of
13.6 Cautions
CHAPTER 13 DMA
FUNCTIONS
Modification of description in
14.1
(3) Internal reset by power-on-clear (POC)
Modification of description in
14.3 (3) POC control register (POCC)
CHAPTER 14
RESET FUNCTION
Addition of
Figure 17-1 Example of Wiring of Adapter for Flash Programming (FA-
144GJ-UEN)
Addition of
Table 17-1 Table for Wiring of Adapter for
µµµµ
PD70F3089Y Flash
Programming (FA-144GJ-UEN)
CHAPTER 17
FLASH MEMORY
(
µ
PD70F3089Y)
Addition of description in
Table 18-5 Control Field Acknowledge Signal Output
Conditions
CHAPTER 18 IEBus
CONTROLLER
(V850/SC2)
Addition of
19.1 Features
Modification of description in
Table 19-1 Overview of Functions
Change of manipulatable bits and reset values in
19.4.2 List of FCAN registers
Modification of description in
19.5.1 CAN message data length registers 00 to 31
(M_DLC00 to M_DLC31)
Modification of description in
19.5.2 CAN message control registers 00 to 31
(M_CTRL00 to M_CTRL31)
Addition of description in
19.5.6 CAN message configuration registers 00 to 31
(M_CONF00 to M_CONF31)
Modification of description in
19.5.7 CAN message status registers 00 to 31 (M_STAT00
to M_STAT31)
Modification of description on manipulatable bits and modification of register format and bit
description in
19.5.10 CAN global interrupt pending register (CGINTP)
Modification of description on manipulatable bits and modification of register format in
19.5.11 CANn interrupt pending register (CnINTP)
Addition to
Cautions
in
19.5.12 CAN stop register (CSTOP)
3rd
Modification of description on manipulatable bits and modification of bit description in
19.5.13 CAN global status register (CGST)
CHAPTER 19 FCAN
CONTROLLER
(V850/SC3)
