CHAPTER 3 CPU FUNCTIONS
User’s Manual U15109EJ3V0UD
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3.4.9 Specific registers
Specific registers are registers that are protected from being written with illegal data due to erroneous program
execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store
operations occur, the system status register (SYS) is notified. The V850/SC1, V850/SC2, and V850/SC3 have two
specific registers, the power save control register (PSC) and processor clock control register (PCC). For details of the
PSC register, refer to
4.3.1 (2) Power save control register (PSC),
and for details of the PCC register, refer to
4.3.1
(1) Processor clock control register (PCC).
The following sequence shows data setting in the specific registers.
<1> Disable DMA operation.
<2> Set the PSW NP bit to 1 (interrupt disabled).
<3> Write any 8-bit data in the command register (PRCMD).
<4> Write the set data in the specific registers (by the following instructions).
•
Store instruction (ST/SST instruction)
•
Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<5> Return the PSW NP bit to 0 (interrupt disable canceled).
<6> If necessary, enable DMA operation.
No special sequence is required when reading the specific registers.
Cautions 1. If an interrupt request or a DMA request is acknowledged between the time PRCMD is
generated (<3>) and the specific register write operation (<4>) that follows immediately after,
the write operation to the specific register is not performed and a protection error (PRERR bit
of SYS register = 1) may occur. Therefore, set the NP bit of PSW to 1 (<2>) to disable the
acknowledgement of INT/NMI or to disable DMA transfer.
The above also applies when a bit manipulation instruction is used to set a specific register.
A description example is given below.
[Description example]: In case of PCC register
LDSR rX.5
;
NP bit = 1
ST.B r0, PRCMD[r0]
;
Write to PRCMD
ST.B rD, PCC[r0]
;
PCC register setting
LDSR rY, 5
;
NP bit = 0
.
.
.
Remark
The above example assumes that rD (PCC set value), rX (value to be written to PSW), and
rY (value rewritten to PSW) are already set.
When saving the value of the PSW, the value of the PSW prior to setting the NP bit must be
transferred to the rY register.
2. Always stop DMA prior to accessing specific registers.
3. If data is set to the PSC register to set IDLE mode or STOP mode, a dummy instruction needs
to be inserted for correct execution of the routine after IDLE or STOP mode is released. For
details, refer to 4.6 Cautions on Power Save Function.
