CHAPTER 4 I
2
C COMMUNICATIONS
User’s Manual U18438EJ2V0UD
56
(3) Operation
The operation flow when transmitting write data twice is shown below.
Steps <1> to <11> correspond to <1> to <11> in Figure 4-9.
<1> The start condition is transmitted.
<2> The slave ID is transmitted (from the 1st to 7th clocks).
<3> R/W information (0) is transmitted (at the 8th clock).
<4> An acknowledge signal is received (at the rising edge of the 9th clock).
<5> The write start address is transmitted (from the 1st to 8th clocks following <4>).
<6> An acknowledge signal is received (at the rising edge of the 9th clock).
<7> Write data is transmitted (first time) (from the 1st to 8th clocks following <6>).
<8> An acknowledge signal is received (at the rising edge of the 9th clock).
<9> Write data is transmitted (second time) (from the 1st to 8th clocks following <8>).
(The address is automatically incremented by 1.)
<10> An acknowledge signal is received (at the rising edge of the 9th clock).
<11> The stop condition is transmitted.
Figure 4-10 shows the timing chart of the write operation.
Figure 4-10. Timing Chart of Write Operation
1
8
9
1
ID6
R
ACK
0
1
8
9
1
ID6
ACK
xxH
xxH
xxH
xxH
xxH
xxH
xxH
Write to IIC shift register 0
Setup
8
9
A0
8
9
A0
ACK
ACK
xxH
xxH
xxH
xxH
1
8
9
1
8
9
WD0
WD0
xxH
xxH
xxH
xxH
xxH
xxH
Start condition
Stop condition
Start condition
1
8
9
1
8
9
8
1
9
0
xxH
W
WD7
ACK
ACK
WD7
SCL
SDA
SCL0
SDA0
SCL
SDA
Master
IIC shift
register 0
IIC bus
Slave
IIC shift
register
Write to IIC shift register 0
Write to IIC shift register 0
Stop condition
Setup
Setup