CHAPTER 3 LCD CONTROLLER/DRIVER
User’s Manual U18438EJ2V0UD
24
Cautions 1. Bits 3 and 4 must be set to 0.
2. When operating VLCON, follow the procedure described below.
A. To stop voltage boosting after switching display status from on to off:
1) Set to display off status by setting LCDON = 0.
2) Disable outputs of all the segment buffers and common buffers by setting
SCOC = 0.
3) Stop voltage boosting by setting VLCON = 0.
B. To stop voltage boosting during display on status:
Setting prohibited. Be sure to stop voltage boosting after setting display off.
C. To set display on from voltage boosting stop status:
1) Start voltage boosting by setting VLCON = 1, then wait for voltage boost wait time
(t
VAWAIT
) (see CHAPTER 5 ELECTRICAL SPECIFICATIONS).
2) Set all the segment buffers and common buffers to non-display output status
by setting SCOC = 1.
3) Set display on by setting LCDON = 1.
(3) LCD clock control register (LCDC)
LCDC specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDC to 00H.
Figure 3-7. Format of LCD Clock Control Register
Address: LCDCTL's 02H
After reset:
00H R/W
Symbol
7 6 5 4 3 2 1 0
LCDC
0 0 0 0
LCDC3 LCDC2 LCDC1 LCDC0
LCDC3
LCDC2
LCD source clock (f
LCD
) selection
Note
0
×
f
LCLK
(Clock input from the LCLK pin)
1
0
f
LCLK
/2
1
1
f
LCLK
/2
2
LCDC1
LCDC0
LCD clock (LCDCL) selection
0
0
f
LCD
/2
6
0
1
f
LCD
/2
7
1
0
f
LCD
/2
8
1
1
f
LCD
/2
9
Note
Specify an LCD source clock (f
LCD
) frequency of at least 32 kHz.
Cautions 1. Bits 4 to 7 must be set to 0.
2. Before changing the LCDC setting, be sure to stop voltage boosting (VLCON = 0).
3. Set the frame frequency to 128 Hz or lower.