CHAPTER 3 LCD CONTROLLER/DRIVER
User’s Manual U18438EJ2V0UD
21
Figure 3-3 shows the control register of LCD controller/driver and the memory map of display RAM, and Figure 3-4
shows the LCD display RAM.
Figure 3-3. Control Register of LCD Controller/Driver
Address
Register
Bit
7 6 5 4 3 2 1 0
LCDCTL's 03H
VLCG0
CTSEL1 CTSEL0
0 0 0 0 0
GAIN
02H
LCDC
0
0
0
0
LCDC3
LCDC2
LCDC1
LCDC0
01H
LCDM
LCDON SCOC VLCON
0 0
LCDM2
LCDM1
LCDM0
LCDCTL's 00H
LCDMD
SEGSET2 SEGSET1 SEGSET0
0 0 0
MDSET1
MDSET0
Figure 3-4. LCD Display RAM
Address
Bit
Segment
7 6 5 4 3 2 1 0
LCDSEG's 27H
Note
0 0 0 0
→
S39
Note
26H
Note
0 0 0 0
→
S38
Note
25H
Note
0 0 0 0
→
S37
Note
24H
Note
0 0 0 0
→
S36
Note
23H
0
0
0
0
→
S35
22H
0
0
0
0
→
S34
21H
0
0
0
0
→
S33
20H
0
0
0
0
→
S32
1FH
0
0
0
0
→
S31
1EH
0
0
0
0
→
S30
1DH
0
0
0
0
→
S29
1CH
0
0
0
0
→
S28
1BH
0
0
0
0
→
S27
1AH
0
0
0
0
→
S26
19H
0
0
0
0
→
S25
18H
0
0
0
0
→
S24
17H
0
0
0
0
→
S23
16H
0
0
0
0
→
S22
15H
0
0
0
0
→
S21
14H
0
0
0
0
→
S20
13H
0
0
0
0
→
S19
12H
0
0
0
0
→
S18
11H
0
0
0
0
→
S17
10H
0
0
0
0
→
S16
0FH
0
0
0
0
→
S15
0EH
0
0
0
0
→
S14
0DH
0
0
0
0
→
S13
0CH
0
0
0
0
→
S12
0BH
0
0
0
0
→
S11
0AH
0
0
0
0
→
S10
09H
0
0
0
0
→
S9
08H
0
0
0
0
→
S8
07H
0
0
0
0
→
S7
06H
0
0
0
0
→
S6
05H
0
0
0
0
→
S5
04H
0
0
0
0
→
S4
03H
0
0
0
0
→
S3
02H
0
0
0
0
→
S2
01H
0
0
0
0
→
S1
LCDSEG's 00H
0
0
0
0
→
S0
Common
↑
COM3
↑
COM2
↑
COM1
↑
COM0
Note
64-pin product only.
Remark
Bits 4 to 7 are fixed to 0.